Which one of the following portions of an instruction represents the operation to be performed?

ANS>> Opcode
Q; What is the working of Processor Status Word (PSW)?
ANs>>To hold the current status of the processor.
Q: What functionality is performed by the instruction lar R3, 36 of SRC?
Ans>> It will load the register R3 with the relative address itself (PC+36).
Q: Which one of the following is the highest level of abstraction in digital design in which the computer architect views the
system for the description of system components and their interconnections?
Ans>> Processor-Memory-Switch level (PMS level)
Q: Which one of the following circuit design levels is called the gate level?
Ans>> Logic Design Level
Q: Which field of the machine language instruction is the "type of operation that is to be performed?
ANs>> Op-code (or the operation code)
Q: Which one of the following is the memory organization of EAGLE processor?
Ans>> 2^16 * 8 bits
Q:

Question # 3 of 10 ( Start time: 07:21:14 PM )

Total M - 1

The data movement instructions ___________ data within the machine and to or from input/output devices.

Ans>> Move
Q; Which operator is used to name registers, or part of registers, in the Register Transfer Language?
Ans> :=

1. A collection of -----------is called a micro program.

Ans>>Microinstructions.

Q: ____is the time needed by the CPU to recognize (not service) an interrupt request
Ans. Interrupt Latency
Q:
3. ________ controls the sequence of the flow of microinstructions.
Ans>>Micro program controller.
4. Which one of the following is NOT a technique used when the CPU wants to exchange data with
a peripheral device?

Ans>> Virtual Memory

Q: 5. Identify the following type of serial communication error condition: The prior character that
was received was not still read by the CPU and is over written by a new received character.
Ans>> Overrun error.
Q: 6. In which one of the following methods, does the CPU poll to identify the interrupting module
and branches to an interrupt service routine on detecting an interrupt?
Ans>>.Software poll
Q: 7. An interface that can be used to connect the microcomputer bus to ________is called an I/O
Port.
Ans>> Peripheral devices.
Q: 8. In ________, a separate address space of the CPU is reserved for I/O operations.
A. Isolated I/O
Ans<< Isolated I/O.
Q: 9. In which one of the following methods for resolving the priority, the device with the highest
priority is placed in the first position, followed by lower-priority devices up to the device with the
lowest priority, which is placed last in the series?
Ans>> Parallel.
Q: 10. _________ is a technique in which some of the CPUs address lines forming an input to the
address decoder are ignored
Ans>> Partial decoding.
Q; 11. An interface that can be used to connect the microcomputer bus to ________is called an I/O
Port.
An>> Peripheral devices.
Q: 12. ______ is an electrical pathway through which the processor communicates with the internal
and external devices attached to the computer.
Ans>> Computer Bus.
Q: 13. Identify the type of serial communication error condition in which A 0 is received instead of a
stop bit (which is always a 1)?
Ans>>. Framing error

Q: 14. How can you define an interrupt?

Ans>> A process where an external device can get the attention of the microprocessor.

Q: 15. In which one of the following methods for resolving the priority, the device with the highest
priority is placed in the first position, followed by lower-priority devices up to the device with the
lowest priority, which is placed last in the series?
Ans>> parallel

Chapter 1: Assessing Computer Performance

MCQ MCQ 1: PerformanceX = 1/ Execution Time x the given relation shows that
A. Performance is increased when execution time is decreased
B. Performance is increased when execution time is increased
C. Performance is decreased when execution time is decreased
D. None
MCQ 2: The processor having Clock cycle of 0.25ns will have the clock rate of
A. 2GHz
B. 3GHz
C. 4GHz
D. 8GHz

MCQ 3: The valid and unimpeachable measurement of performa

nce of any computer is
C. Execution time
MCQ 4: The native MIPS has the MIPS measurement of A.
MIPS = Instruction count/(Execution time)10^6
MCQ 5: If computer A execute a program in 10 seconds and co
m- puter B runs the same in 15 seconds, how much faster is
computer
B. 1.5 times

MCQ 6: For two computers X and Y, if the performance of computer X is greater than the performance of computer Y, we have
D. PerformanceX > PerformanceY
MCQ 7: The total amount of work done during execution, in a gi
ven time is referred to as
C. Through put
MCQ 8: To increase the performance of the computer its throug
h put is increased by
A. Replacing processor with faster version
MCQ 9: Computer A having clock cycle time of 250 ps and cycl
e per instruction of 2.0 for some programs, and computer B
having clock cycle time of 500 ps and a cycle per instruction of
1.2 for the same program. Which one is faster for this program
A. Computer A
MCQ 10: When the PC having Clock rate of 2 and the CPU cloc
k cycle for a program is 4 then Execution time of this computer
for a program will be
D. 2
MCQ 1: A first goal of compiler writer
A. Correctness
MCQ 2: Optimizations on the sources with output leading to late
r optimization passes are known as
B. High-level optimizations

MCQ 3: In 32-bit addressing mode, the address field is either 1

byte or
C. 4 bytes
MCQ 6: One that is used to allocate local variables is
B. Stack
MCQ 7: Vector architectures are operated on vectors of
B. Data
MCQ 8: Graph coloring gives best results, when there are atleast
A. 16 general-purpose registers
MCQ 9: Compilers usually chooses which procedure calls has to
be expanded inline before knowing the size of the procedure,
that is being called, the stated problem is known as
C. Phase-ordering problem
MCQ 10: The operation is normally specified in one field, know
n as
D. Instruction count
MCQ 11: The length of 80x86 instructions can vary between D.
1 to 17 bytes
MCQ 12: Optimization, known as basic block, by the compiler
peo- ple is
C. Local optimizations

MCQ 13: The procedure when call procedure that has been call
ed, saving the registers it wants for using, when the caller has
been left unrestrained, is known as
C. Callee saving
MCQ 17: Register allocation algorithms are particularly based o
n the technique, named as
D. Graph coloring
MCQ 5: Floating-point numbers are normally a multiples of the
size of a
C. Word
MCQ 8: The Decimal representation of this binary (1011)two is
C. (11)10
MCQ 11: In the division, the two operands (dividend and divisor
) and the answer (quotient) of divide are accompanied by a
second answer called the
A. Reminder
MCQ 19: The floating point operation is also called
D. Overflow

MCQ 24: A number in scientific notation, that has no leading 0s

is called a
B. Normalized number
MCQ 28: The decimal value of this 32-bit two
D. (-4)10

MCQ 31: Instruction set less than immediate unsigned can be ex

e- cuted with the command
C. sltiu
MCQ 32: The first operand is called the multiplicand and the sec
- ond
D. Multiplier

1.Which one of the following is the memory organization of EAGLE processor?

2^8 * 8 bits
2^16 * 8 bits
2^32 * 8 bits
2^64 * 8 bits
2.Which of the following statements is/are true about RISC processors claimed advantages over
CISC processors?
(a) Keeping regularly accessed variables in registers as opposed to keeping them in memory
facilitates faster execution.
(b) RISC CPUs outperform CISC CPUs in procedural programming environments.
(c) Instruction pipelining has helped RISC CPUs to attain a target of 1 cycle per instruction.
(d) It is easier to maintain the family concept in RISC CPUs.
Select correct option:
(a), (b) &(c)
(b), (c) & (e)
(c), (d) & (e)
(a), (c) & (d)

3.Which operator is used to name registers, or part of registers, in the Register Transfer
Language?
Select correct option:
:=
&
%

4.What does the word D in the D-flip-Flop stands for?

Select correct option:
Data
Digital
Dynamic
Double
5.Which one of the following is a bi-stable device, capable of storing one bit of information?
Decoder
Flip-Flop
Multiplexer
Diplexer
6.The instruction ___________ will load the register R3 with the contenets of the m\emory
location M [PC+56]
Add R3, 56
lar R3, 56
ldr R3, 56
str R3, 56
7.Almost every commercial computer has its own particular ---------- language Select correct
option:
3GL
English language
Higher level language
assembly language
8.Which one of the following is the memory organization of EAGLE processor?

8-bits
16-bits

32-bit
64-bits
9. Which one of the following circuit design levels is called the gate level? Select correct option:
Logic Design Level
Circuit Level
Mask Level
None of the given

10.Which one of the following portions of an instruction represents the operation to be

performed?
Address

Instruction code
Opcode
Operand
Q 1 For any of the instructions that are a part of the instruction set of the SRC, there are
cerain_________required; which may be used to select the appropriate function for the
ALU to be performed, to select the appropriate registers, or the appropriate memory
location.

Register

Control signals

Memory

None of the given

Q 2 FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC _____wide.

8-bits

16-bits

32-bits

64-bits
Q 3 What is the instruction length of the FALCON-A processor?

8-bits
16-bits
32-bits
64-bits

Q 4 _________control signals enable the input to the PC for receiving a value that is
currently on the internal processor bus.

LPC

INC4

LC

I
Q 5 Which one of the following is a bi-stable device, capable of storing one bit of
information?

Decoder

Flip-Flop

Multiplexer

Diplexer
Q 6 Which instruction is used to store register to memory using relative address?

ld instruction

ldr instruction

lar instruction

str instruction
Q 7 Which field of the machine language instruction is the type of operation that is to be
performed?

Op-code (or the operation code)

CPU registers

Momory cells

I/O locations
Q 8 The instruction ___________ will load the register R3 with the contenets of the
m\emory location M [PC+56]
___Add R3, 56
___lar R3, 56
___ldr R3, 56
___str R3, 56
Q 9 _______ operation is required to change the processors state to a known, defined
value.

Change
Reset
Update
None of the given

Q 10 which type of instructions help in changing the flow of the program as and when
required?

Arithmetic

Control

Data transfer

Floating point
Question # 1
Where does the processor store the address of the first instruction of the
ISR?
Select correct option:
=>Interrupt vector (p277)
Interrupt request
Interrupt handler
All of the given options

Question # 2
In ________, a separate address space of the CPU is reserved for I/O
operations.
Select correct option:
=>Isolated I/O (p236)
Memory Mapped I/O
All of above
None of above

Question # 3
-------------- is the time needed by the CPU to recognize (not service) an
interrupt request.
Select correct option:
=>Interrupt Latency (p279)
Response Deadline
Timer delay
Throughput

Question # 4
_________ is a technique in which some of the CPUs address lines forming

an input to the address decoder are ignored.

Select correct option:
Microprogramming
Instruction pre-fetching
Pipelining
=>Partial decoding (p255)

Question # 5
How can you define an interrupt?
Select correct option:
A process where an external device can speedup the working of the
microprocessor
A process where memory can speed up programs execution speed
=>A process where an external device can get the attention of the
microprocessor (p198, 223, 273)
A process where input devices can takeover the working of the
microprocessor

Question # 6
An interface that can be used to connect the microcomputer bus to
________is called an I/O Port.
Select correct option:
Flip Flops
Memory
=>Peripheral devices (p234)
Multiplexers

Question # 7
Every time you press a key, an interrupt is generated. This is an example
of
Select correct option:
=>Hardware interrupt
Software interrupt
All of the given
None of the given

Question # 8
Identify the following type of serial communication error condition: The
prior character that was received was not still read by the CPU and is over
written by a new received character.

Select correct option:

Framing error
Parity error
=>Overrun error (p240)
Under-run error

Question # 9
A software routine performed when an interrupt is received by the
computer is called as --------Select correct option:
Interrupt
=>Interrupt handler
Exception
Trap

Question # 10
Which one of the following methods for resolving the priority makes use of
individual bits of a priority encoder?
Select correct option:
Daisy-Chaining Priority
Asynchronous Priority
=>Parallel Priority (p281)
Semi-synchronous Priority

1 The control signal allows the contents of the program counter register to be written onto
the internal processor bus
Pcout
2 Is the control signals to allow the contents of the MBR to be read out onto the cpu
internal bus
MBRout
3 Anything that interrupts the normal flow of execution of instructions in the processor is
called
EXCEPTION
4 These are the exceptions raised during the process of decoding and executing the
instruction
PROGRAM EXCEPTIONS

5 Is the technique of overlapping multiple instructions in time

PIPELINING
6 Pipelining kon si techinique hay
MULTIPLE
7 SRC OR FALCON KA THA KAY KITNEY BITS WIDE HAIN
( 32,16) AISAY THA
8 SPARC KA THA KAY INSTRUCTION FORMAT KIA HEY
32 BITS MAIN NAY ANS KIA I DONT KNOW THE EXACT ANS.
9 IRMBR is ka control signal btana tha
MBRout,c=b,LIR;

Question # 1 of 10 ( Start time: 01:52:33 PM ) Total Marks: 1

In CPU design, _________ creates or forms the interface between the data path and the
control unit. Select correct option:

Busses

ALU

Control Signal

Cache
Question # 2 of 10 ( Start time: 01:53:24 PM ) Total Marks: 1
Memory Address Register (MAR) and Memory Buffer Register (MBR) are also of
_____while in SRC these are of ______. Select correct option:

16-bits , 32 bit

24-bits , 32 bit

32-bits , 16 bit

32-bits , 64 bit
Question # 3 of 10 ( Start time: 01:54:24 PM ) Total Marks: 1
Which technique is used to overlapping multiple instructions in time? Select correct option:

Pipelining

Branch

delay Data forwarding

SRC

Question # 4 of 10 ( Start time: 01:55:04 PM ) Total Marks: 1

RISC stands for? Select correct option:

Registers internal system cache

Reduced Instruction Set Computer

Register Instruction Set Computer

Reduced Internal System Computers

Question # 5 of 10 ( Start time: 01:56:03 PM ) Total Marks: 1
In FALCON A Program Counter (PC) and Instruction Register (IR) are of _____ bits
Select correct option:

16-bits

24-bits

32-bits

64-bits
Question # 6 of 10 ( Start time: 01:57:10 PM ) Total Marks: 1
Which of the following register is used to enable the tri-state buffers with the MBR? Select
correct option:

MBRout

MARout

LMBR

INC4
Question # 7 of 10 ( Start time: 01:58:00 PM ) Total Marks: 1
____________is defined as the time required to process a single instruction. Select correct
option:

Memory access

ALU operation

Latency

Throughput
Question # 8 of 10 ( Start time: 01:58:46 PM ) Total Marks: 1
Program counter (PC) and Instruction register (IR) are 16-Bit registers while in SRC these
are __________. Select correct option:

31-Bit

16-Bit

32-Bit
64-Bit
Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
Select correct option:

iret

irq
int
nmi

Question 2 of 10
Identify the following type of serial communication error condition in which no
character is
available at the beginning of an interval.
Select correct option:
Framing error
Parity error

Overrun error

Under-run error

Question 3 of 10
In which one of the following methods, does the CPU poll to identify the
interrupting module
and branches to an interrupt service routine on detecting an interrupt?
Select correct option:
Daisy Chain

Software Poll

Multiple interrupt lines

All of the given options

Question 4 of 10
In which one of the following methods for resolving the priority, the device with the
highest
priority is placed in the first position, followed by lower-priority devices up to the
device with
the lowest priority, which is placed last in the series?
Select correct option:
Asynchronous
Daisy-Chaining Priority

Parallel

Semi-synchronous

Question 5 of 10
Where does the processor store the address of the first instruction of the ISR?
Select correct option:

Interrupt vector

Question 6 of 10
______ is an electrical pathway through which the processor communicates with the
internal and
external devices attached to the computer.
Select correct option:

Computer Bus

Hazard
Memory
Disk

Question 7 of 10
----------the device usually means reading its status register every so often until the
device's
status changes to indicate that it has completed the request.
Select correct option:

Executing

Interrupting

Masking
Polling

Question 8 of 10
A software routine performed when an interrupt is received by the computer is
called as --------Select correct option:
Interrupt

Interrupt handler

Exception
Trap
Question 9 of 10
Which one of the following is NOT a technique used when the CPU wants to
exchange data
with a peripheral device?
Select correct option:
Direct Memory Access (DMA)
Interrupt driven I/O
Programmed I/O

Virtual Memory

Question 10 of 10
Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
(Repeated this question)
Select correct option:

IRET

IRQ
INT

Permalink Reply by +!mn on January 28, 2014 at 2:01pm

uestion # 1
Where does the processor store the address of the first instruction of the ISR?
Select correct option:
=>Interrupt vector (p277)
Interrupt request
Interrupt handler
All of the given options
ADMIN TEAM

Question # 2
In ________, a separate address space of the CPU is reserved for I/O operations.
Select correct option:
=>Isolated I/O (p236)
Memory Mapped I/O
All of above
None of above

Question # 3
-------------- is the time needed by the CPU to recognize (not service) an interrupt
request.
Select correct option:

=>Interrupt Latency (p279)

Response Deadline
Timer delay
Throughput

Question # 4
_________ is a technique in which some of the CPUs address lines forming an input
to the address decoder are ignored.
Select correct option:
Microprogramming
Instruction pre-fetching
Pipelining
=>Partial decoding (p255)

Question # 5
How can you define an interrupt?
Select correct option:
A process where an external device can speedup the working of the
microprocessor
A process where memory can speed up programs execution speed
=>A process where an external device can get the attention of the microprocessor
(p198, 223, 273)
A process where input devices can takeover the working of the microprocessor

Question # 6
An interface that can be used to connect the microcomputer bus to ________is called
an I/O Port.
Select correct option:
Flip Flops
Memory
=>Peripheral devices (p234)
Multiplexers

Question # 7
Every time you press a key, an interrupt is generated. This is an example of
Select correct option:
=>Hardware interrupt

Software interrupt
All of the given
None of the given

Question # 8
Identify the following type of serial communication error condition: The prior
character that was received was not still read by the CPU and is over written by a
new received character.
Select correct option:
Framing error
Parity error
=>Overrun error (p240)
Under-run error

Question # 9
A software routine performed when an interrupt is received by the computer is
called as --------Select correct option:
Interrupt
=>Interrupt handler
Exception
Trap

Question # 10
Which one of the following methods for resolving the priority makes use of
individual bits of a priority encoder?
Select correct option:
Daisy-Chaining Priority
Asynchronous Priority
=>Parallel Priority (p281)
Semi-synchronous Priority

Permalink Reply by +!mn on January 29, 2014 at 10:16am

1. A collection of -----------is called a micro program.
A. large scale operations
ADMIN TEAM

B. Registers
C. DMA
D. Microinstructions
Microinstructions.
2. ____is the time needed by the CPU to recognize (not service) an interrupt request
A. Interrupt Latency
B. Response Deadline
C. Timer delay
D. Throughput
Interrupt Latency.
3. ________ controls the sequence of the flow of microinstructions.
A. Multiplexer
B. Micro program controller
C. DMA Controller
D. Virtual Memory
Micro program controller.
4. Which one of the following is NOT a technique used when the CPU wants to
exchange data with a peripheral device?
A. Direct Memory Access (DMA)
B. Interrupt driven I/O
C. Programmed I/O
D. Virtual Memory
Virtual Memory .
5. Identify the following type of serial communication error condition: The prior
character that was received was not still read by the CPU and is over written by a
new received character.
A. Framing error
B. Parity error
C. Overrun error
D. Under-run error
Overrun error.
6. In which one of the following methods, does the CPU poll to identify the
interrupting module and branches to an interrupt service routine on detecting an
interrupt?
A. Daisy Chain
B. Software Poll

C. Multiple interrupt lines

D. All of the given options
Software Poll.
7. An interface that can be used to connect the microcomputer bus to ________is
called an I/O Port.
A. Flip Flops
B. Memory
C. Peripheral devices
D. Multiplexers
Peripheral devices.
8. In ________, a separate address space of the CPU is reserved for I/O operations.
A. Isolated I/O
B. Memory Mapped I/O
C. All of above
D. None of above
Isolated I/O.
9. In which one of the following methods for resolving the priority, the device with
the highest priority is placed in the first position, followed by lower-priority devices
up to the device with the lowest priority, which is placed last in the series?
A. Asynchronous
B. Daisy-Chaining Priority
C. Parallel
D. Semi-synchronous
Parallel.
10. _________ is a technique in which some of the CPUs address lines forming an
input to the address decoder are ignored.
A. Microprogramming
B. Instruction pre-fetching
C. Pipelining
D. Partial decoding
Partial decoding.

Permalink Reply by Emblica(Mcs) 2nd on January 29, 2014 at 4:40pm

previous quiz q post kiye hn , today quiz kro na??/

Permalink Reply by +!mn on January 29, 2014 at 4:44pm

sis ye mera aj ka quiz hi hy sirf ak quiz hy previous :)
ADMIN TEAM

Permalink Reply by Irfan Khan MSCS on January 29, 2014 at 6:59pm

Good Aimen thanks for Sharing

Permalink Reply by +!mn on January 29, 2014 at 7:19pm

welcome G :)
ADMIN TEAM

Permalink Reply by Uzma Kanwal (MSCS 1) on January 29, 2014 at 11:38pm

Uzma
Question # 1 of 10 ( Start time: 10:44:38 PM ) Total Marks: 1
The ___________ can be determined from the number of platters and the number of
tracks.
Select correct option:
Speed of processing
execution time
storage capacity
Latency

Question # 2 of 10 ( Start time: 10:45:30 PM )

Total Marks: 1

A component connected to the _________ and with which the master component can
communicate during a particular bus cycle. Normally the CPU with its bus control
logic is the master component.
Select correct option:
Slave component
System bus
Master component
Bus component
Question # 3 of 10 ( Start time: 10:46:06 PM ) Total Marks: 1
The average latency to the desired data is halfway round the disk so, what will be
the average rotational latency if the disk rotates at 20,000 rpm.
Select correct option:
1.25ms
1.5ms324
1.0ms
2.0ms
Question # 4 of 10 ( Start time: 10:47:15 PM ) Total Marks: 1
_________ is a technique in which some of the CPUs address lines forming an input
to the address decoder are ignored.
Select correct option:
Microprogramming
Instruction pre-fetching
Pipelining
Partial decoding
Question # 5 of 10 ( Start time: 10:48:32 PM ) Total Marks: 1
Identify the following type of serial communication error condition: The prior
character that was received was not still read by the CPU and is over written by a
new received character.
Select correct option:
Framing error
Parity error
Overrun error
Under-run error

Question # 6 of 10 ( Start time: 10:49:10 PM ) Total Marks: 1

Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
Select correct option:
IRET
IRQ
INT
NMI
Question # 7 of 10 ( Start time: 10:49:45 PM ) Total Marks: 1
How can you define an interrupt?
Select correct option:
A process where an external device can speedup the working of the microprocessor
A process where memory can speed up programs execution speed
A process where an external device can get the attention of the microprocessor
A process where input devices can takeover the working of the microprocessor
Question # 8 of 10 ( Start time: 10:50:20 PM ) Total Marks: 1
Every time you press a key, an interrupt is generated. This is an example of
Select correct option:
Hardware interrupt
Software interrupt
All of the given
None of the given
Question # 9 of 10 ( Start time: 10:51:01 PM ) Total Marks: 1
Where does the processor store the address of the first instruction of the ISR?
Select correct option:
Interrupt vector
Interrupt request
Interrupt handler
All of the given options
Question # 10 of 10 ( Start time: 10:51:37 PM ) Total Marks: 1
An interface that can be used to connect the microcomputer bus to ________is called
an I/O Port.
Select correct option:
Flip Flops
Memory

Peripheral devices
Multiplexers
Which of the following bits of SRC instruction are used as short displacement or to
specify an immediate operand?
c2<11..0>: = IR<11..0>;
c2<21..0>: = IR<21..0>;
c2<16..0>: = IR<16..0>; Ans
c2<11..0>: = IR<11..0>;
Which one of the following portions of an instruction represents the operation to be
performed?
Address
Instruction code
Opcode Ans
Operand
While executing the RTL instruction A R3, which of the given below control signals
will be activated?
LA, R3in
R3out Ans
LA, R3out
R3in, Lout
What is the instruction length of the FALCON-A processor?
Select correct option
8 bits
16 bits Ans
32 bits
64 bits
In FALCON-A processor memory word size is of
Select correct option
1 byte
4 byte
2 byte ans
8 byte

In CPU design, _________ creates or forms the interface between the data path and the
control unit.
Select correct option
Busses
ALU
Control Signal
Cache
In RTL, which of the following symbols is used to store some data into a register?
Select correct option
:
<- := == All the members of the MC68000 family are __________ processors. Select
correct option 8-bit 16-bit 20-bit 32-bit

Reply

image: http://api.ning.com/files/MQlBiJ4*uRBT9oHMmJ0u4OfParCugF5eyACxdqfFmbFtnxyEJ4KlBsbnLFlcKmbPMpfl0J8VghBKPt7GQ-*tMa6Hj8WTQ4--/20160712_191720.jpg?width=48&height=48&crop=1%3A1

Permalink Reply by ( BScs 6th semest) on May 20, 2016 at 1:33am

cs501 quiz no 1 2016 koi galt ho to correction kar day

What is the instruction length of the FALCON-E processor?
Select correct option
8 bits
16 bits
32 bits
64 bits
Program counter (PC) and Instruction register (IR) are normally 16-Bit registers, however
in SRC, these are __________.
Select correct option
31-Bit
16-Bit
32-Bit
64-Bit
CISC Stands for?
Computer instruction set compiler
Complex instruction set computer Ans

Complex internal system computer

Complex instruction system compiler
Which operator is used to name registers, or part of registers, in the Register Transfer
Language?
:= Ans
&
%

All the members of the MC68000 family are __________ processors.

8-bit
16-bit
20-bit
32-bit Ans
Which one of the following registers holds the address of the next instruction to be
executed?
Accumulator
Address Mask
Instruction Register
Program Counter Ans
Which of the following bits of SRC instruction are used as short displacement or to
specify an immediate operand?
c2<11..0>: = IR<11..0>;
c2<21..0>: = IR<21..0>;
c2<16..0>: = IR<16..0>; Ans
c2<11..0>: = IR<11..0>;
While executing the RTL instruction A R3, which of the given below control signals
will be activated?
LA, R3in
R3out
LA, R3out
R3in, Lout
RISC stands for?
Registers internal system cache
Reduced Instruction Set Computer

Register Instruction Set Computer Ans

Reduced Internal System Computers
In MC68000, only the last __________ bits of 32-bit program counter (PC) register are
used to store memory addresses.
8
16
24
32
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