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Lecture 1
Information
Lectures time: Tuesdays 2-5 PM
Office hours:
By appointment (hmoustafa@aucegypt.edu)
Marking Scheme:
Midterm (20%)
Quizzes (20%) Each lectureProject (20%)
Final Exam (40%)
Reference books:
Analog Integrated Circuit Design (2nd edition), John Wiley & Sons, Inc.
By: Tony Chan Carusone, David A. Johns and Kenneth W. Martin
Design of Analog CMOS Integrated Circuits, McGraw-Hill. By: Behzad
Razavi
Microelectronic Circuits (6th edition), Oxford University Press, By K.
Smith and A. Sedra
2
Course outline
Review on CMOS
Basic current mirrors and single stage
amplifiers
Frequency response and differential
amplifiers
Feedback amplifiers
Op-amp design
Noise and Linearity analysis
Active filters
Data Converters
Oscillators and Phase Locked Loops
3
Why Analog???
Naturally-occurring signals, e.g., RF received
signal, voice and video, are analog.
System and environment non-idealities often
make it necessary to treat digital signals as
analog (Disk Drive Retrieved Data).
Why Analog???
Typical real world implementation:
Analog Front End
Review on CMOS
MOS device
MOS = Metal Oxide Semiconductor
Source/Drain are interchangeable
Channel length L represents the CMOS scaling
16nm CMOS technology is available currently
Review on CMOS
MOS device
nMOS symbols
pMOS symbols
Review on CMOS
VGS negative
VGS positive
Review on CMOS
Threshold voltage (Vtn) <nMOS>
VGS at which the concentration of the electrons under the
gate is equal to the concentration of the holes in the p
substrate far from the gate
11
Review on CMOS
Overdrive voltage: Veff = VGS Vt
Long channel transistors
12
Review on CMOS
Second order effects
Channel length modulation ()
Add [1+ (VDS - Veff)] to the saturation equation
Body effect
The body terminal affects Vt
Body bias is used to control Vt
The body terminal is called the back gate
Review on CMOS
Small signal model
gm = transconductance (A/V)
Circuit analysis
Circuit design
14
Review on CMOS
Example
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Review on CMOS
Solution
gm = ID/VGS
Vtn = 0.45V
n * Cox = 270 A/V2
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Review on CMOS
High frequency model
Main capacitances are:
gate capacitance
Miller capacitance
17
Review on CMOS
Analog circuits Figures of Merit (FoM)
is inversely proportional to L
How technology scaling affects on Ai ??
18
Review on CMOS
Analog circuits Figures of Merit (FoM)
Explain ????
19
20
Review on CMOS
Advanced MOS modeling
Sub-threshold Operation (Weak Inversion)
When Veff is negative (i.e., VGS < Vt)
Drain current is given by exponential relationship
21
Review on CMOS
Advanced MOS modeling
Sub-threshold slope (S)
S = ln(10) * n* KB T /q = 2.3
n KB T /q
Ideal value = 60mV/ decade
when n = 1
Practical value =
90mV/decade when
IOFF
n =1.5
VGS
22
Review on CMOS
Advanced MOS modeling
Velocity saturation and mobility degradation
W
V 2 min
I D nCox (Veff *Vmin
)
L
2
Vmin Minimum (VDS ,Veff ,VDS SAT )
23
Review on CMOS
Technology scaling
24
Review on CMOS
VARIABILITY AND MISMATCH
When integrated circuits are manufactured, a variety of
effects cause the effective sizes and electrical properties
of the components to differ from those intended by the
designer
Systematic variations
due to lithographic techniques
exhibits spatial correlation
25
Review on CMOS
Problems
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