International Journal of Science, Engineering and Technology Research (IJSETR)

Volume 1, Issue 1, July 2012

II. RELATED WORK

Performance comparison of 16x16 bit

Multiprecision Multiplier based on
the Vedic and Array Multiplication
Technique
P.Santhini1, B.Sahaya Jenila2, Dr.B.Elizabeth Caroline3
Abstract In this paper, we present a Multi-precision (MP)
multiplier based on vedic mathematics. This reconfigurable
multiplier that incorporates variable precision and parallel
processing (PP), to provide optimum performance for a variety
of operating conditions. The basic building blocks of the
proposed reconfigurable multiplier is 8x8 vedic multiplier. It
can either work as independent smaller-precision multipliers or
work in parallel to perform higher-precision multiplications.
Here we have compared the MP multiplier performance with
Array and Vedic technique .

Index Terms Array multiplication, carry look-ahead

adder(CLA), multi-precision multiplier, Vedic mathematics.

I.

INTRODUCTION

Multiplication is an important operation in many

arithmetic operations. But multiplier circuit consumes more
processor time and causes diminishing in processor
performance. Multiplication is the important thing in many
application so we need to select high performance multiplier
with less delay, less area and low power consumption. At the
same time, high speed multipliers are required to maintain
high throughput in arithmetic calculation.
In this paper we proposes a multi-precision multiplier,
that invoke variable precision as input and provides the
multiple number of output from a single multiplier.
Previously, separate multipliers were used to get the various
bit output. But, this MP multiplier is used to get the various
bit combination output. To increase the speed and to reduce
the area Vedic multiplier is used as the processing element.
Array multiplier is also used as the processing element to
compare the performance of the Vedic and array operation.
In array multiplication add and shift method was used.
Power consumption and delay was high in array
multiplication.
The paper is organized as follows. Section II illustrates
the Related work Section III describes the Multiprecision
multiplication method. Section IV employs Array
Multiplication Technique.Section V employs the Vedic
multiplication with UT technique. Section VI provides the
proposed Multiprecision multiplier based on both vedic and
array multiplication. Section VII describes the experimental
results. Section VIII will provide the conclusion and future
work.
Manuscript received Oct 15, 2011. P.Santhini Applied Electronics,
IFET College of Engineering, (santhini2622@gamil.com). Villupuram,
India, +919894144279
B.Sahaya Jenila Applied Electronics, IFET College of Engineering,
Villupuram, India, +919489694892., (jenisahaya92@gmail.com).
Dr,B.Elizabeth Caroline, Electronics and Communication Engineering,
IFET College of Engineering, Villupuram, India, +919944723773,
(becaroline05@yahoo.com).

The number of partial products are reduced to n/2 in

radix-4We can reduce the number of partial products even
further to n/3 by using a higher radix-8 in the multiplier
encoding, thereby obtaining a simpler CSA tree .This
implies less delay and a smaller area size[1]. Vedic
multiplier based on UT technique is implemented by using
karatsuba algorithm to reduce the area and delay[2].Low
power and less area square and cube architectures uses
Dwandwa yoga Duplex combination properties of Urdhva
Tiryagbhyam sutra and Anurupyena sutra of Vedic
mathematics. It provides 45%less power consumption.
[4].The conventional array multiplier is synthesised using
16T full adder cell. In conventional array multiplier the final
stage of addition is removed and the carry bits are given to
the input of the next left column input, thereby causing a
large trade off in power and area. The implemented array
multiplier is synthesised using 10T full adder cell. The
proposed array multiplier design uses 96 less transistor
count and saves 2.82% of total power[6].
Floating- point numbers are frequently used for numerical
calculations in computing systems for better accuracy, but
floating- point operations are complex and difficult to design
on FPGAs . This work attempts to design such hardware
architecture for single precision floating-point multiplication
that is easily implementable with high efficiency. The
multiplier unit is based on ancient vedic mathematics
technique[7].Modified Booths was twice as fast as Booths
algorithm. Modified Booth encoding algorithm was an
efficient way to reduce the number of partial products by
grouping consecutive bits in one of the two operands to
form the signed multiplies. It did not provide high
performance for higher bit multiplication[8].
Vedic mathematics based DSP operations reduce the
processing time as compare to inbuilt function of MATLAB.
It reduces the 40-60% time from inbuilt function[9]. A new
digit-level hybrid multiplier which performs two successive
multiplications with the same latency as the one for one
multiplication. Efficiency of the hybrid architecture in terms
of area and time delay for different digit sizes. The main
advantage of this new hybrid architecture is to speed up
exponentiation and point multiplication whenever doublemultiplication is required[10]. Vedic multiplier was
implemented by using carry save adder to improve the
performance[11].
I

MULTIPRECISION MULTIPLICATION
METHOD

In this section, we introduce various multi-precision

multiplication techniques, including operand scanning,
product scanning, hybrid scanning and operand
caching. Each method has unique features for reducing the
1

All Rights Reserved 2012 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR)

Volume 1, Issue 1, July 2012

number of load and store instructions.In particular, operand

caching reduces the number of memory accesses by
caching operands to the registers. However, after partial row
products, no common operands exist. Therefore, operands
should be reloaded for the next row computation. To
describe the multi-precision multiplication method, we use
the following notations.

n 1

n 1

i 1

j 1

P Xi Yj

2(i+j)

(1)

n 1

X Xi
i 1

2i

(2)

2j

(3)

n 1

Y Yi
j 1

(a)

(c)

(b)

(d)

Fig. 1. Multi-precision Multiplication Techniques. (a)Operand-Scanning.

(b)Product-Scanning. (c)Hybrid-Scanning. (d)Operand-Caching

Let A and B be two m-bit operands that are multiple-word

arrays. Each operand is written as follows: A = (A[n1], ...,
A[2], A[1], A[0]) and B = (B[n 1], ..., B[2], B[1], B[0]).
The division of operand-size(m) by word-size(w) represents
the number of elements(n) in the operand array. The result
of multiplication is twice as large as operand C = (C [2n
1], ..., C [2], C [1], C [0]). For clarity, we describe the
method using a multiplication structure and rhombus form,
as shown in Figure. 1. Each point represents a multiplication
A[i] B[j]. The rightmost corner of the rhombus represents
the lowest indices (i, j = 0), whereas the leftmost represents
corner the highest indices (i, j = n 1). The lowermost side
represents result indices C [k], which ranges from the
rightmost corner (k = 0) to the leftmost corner (k = 2n 1).
II

Figure 3 describes about the operation of Array

multiplication technique. In first row of adders carry in will
be assigned as 0. In subsequent rows, carry which is
generated by the previous adder rows can simply shifted
and bypassed to the next row. We can add these partial
products by using various adders like Ripple carry adder,
Carry look-ahead adder(CLA), Carry save adder etc. In this
paper, we are using Carry look-ahead addition to add the
partial products.

ARRAY MULTIPLICATION TECHNIQUE

A MxN array multiplier operates by calculating partial

products in parallel and then by shifting and accumulating
the partial products. The multiplier width corresponds to the
M data and multiplicand width corresponds to the N data of
the given input. Based on the co-effiicient k, number of bits
can be selected for multiplication. If k value is 0,the k-th
row of adders does not activated.
X3
Y3

X3Y3
P7-P6

Figure 3 Operation of Array multiplier

X2
X1
X0
Y2
Y1
Y0
X0Y3 X0Y2
X0Y1
X1Y3 X1Y2
X1Y1 X1Y0
X2Y3 X2Y2 X2Y1
X2Y0
X3Y2 X3Y1 X3Y0
P5
P4
P3
P2
P1

X0Y0

P0

Figure 2 Multiplier Architecture

Figure 2 describes about the general structure of the

multiplier. In this X is the multiplicand and Y is the
multiplier. One bit of the multiplicand is ANDed with every
bit of the multiplier and produces the partial product of the
first row and arrange the next row with next bit of the
multiplicand ANDed with all bits of multiplier. Likewise, it
repeatedly produces the partial product till the last bit of the
multiplicand.

III VEDIC MATHEMATICS

Vedic Mathematics is the part of four Vedas. It is part of
Sthapatya-Veda, which is an Upa Veda-Veda of Atharva
Veda. This system is based on 16 sutras, which is given in
word format to solve the mathematical problems in natural
ways. While compared to other multiplication technique, it
is very easiest and fastest method for calculation. This is so
because, Vedic formulae based on the natural principles in
which human mind works. This can be applied to various
branches of engineering such as computing and digital
signal processing.
A. URDHVA TRIYAGBHYAM TECHNIQUE:
Urdhva Triyagbhyam is a general sutra used for
multiplication. It means vertically and crosswise.
Step -1
a3 a2 a1 a0

Step-2
a3 a2 a1 a0

Step-3
a3 a2 a1 a0

b3 b2 b1 b0

b3 b2 b1 b0

b3 b2 b1 b0

(a)

(b)

(c)

Step-4
a3 a2 a1 a0

2
All Rights Reserved 2012 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR)

Volume 1, Issue 1, July 2012

Ci 1 Gi Pi Ci

b3 b2 b1 b0

(14)

(d)
Step-5

Step-6

Step-7

a3 a2 a1 a0

a3 a2 a1 a0

a3 a2 a1 a0

b3 b2 b1 b0

b3 b2 b1 b0

b3 b2 b1 b0

(e)

(f)

III. PROPOSED MULTIPRECISION MULTIPLIER

(g)

Figure 4 Line Diagram for Urdhva - Tiryakbhyam Sutra

Figure 4 illustrates the multiplication method used in UT

technique. In above line diagram first calculate vertically
and then crosswise computation can be done.
If any carry is produced in the previous step will be
passed to the next step of calculation.

The proposed multi-precision multiplier comprises 8x8

multiplier as the processing element. These processing
elements are programmed by Vedic multiplication. The same
multiplier can be programmed by using Array multiplication
technique to compare the performance. In existing method
only fixed-width multiplication can be done. Variable
precision multiplication can be done by using this proposed
multiplier.

For inputs a3 a2 a1 a0 and b3 b2 b1 b0:

P0 a 0.b0

(4)
(5)
C1P2 C0 a0.b 2 a1.b 1
(6)
C2P3 C1 a3.b 0 a0.b 3 a1.b2 a2.b 1 C00
(7)
C3P4 C2 a3.b 1 a1.b3 a2.b2 C01 C10
(8)
C4P5 C3 a3.b 2 a2b3 C11 C20
(9)
C5P6 C4 a3.b 3 C21
(10)
For 4x4 multiplication the above expression will be used.
The 8x8 multiplier is implemented by using 4x4 multiplier.
Addition can be done by using different adders.
In proposed system carry look-ahead adder(CLA) is used
for addition.
C0P1 a 0.b1 a1.b0

B.

Figure 6 Block diagram for multi-precision multiplier

In proposed multiplier inputs are given to the processing

element. Each processing element consists of four 8x8
multiplier, so it will provide 16 8x8 multiplication output.
For 16x16 multiplication we need 4 8x8 multiplier. Each
processing element will produce one 16 bit result as shown
in figure 7.

CLA
Carry look-ahead adder reduces the carry propagation time
by propagating the carry signals in advance.

Figure 7 Processing element(PE)

Figu
re 5 Carry look-ahead adder
In figure 5 G and P are Generate and Propagate term
respectively. S and C are Sum and Carry term
respectively. Sum and Carry are produced by using
generate and propagate term. The propagate P and
Generate G is given as followss
Pi Ai Bi carry propagate
Gi Ai Bi carry generate
(12)

(11)

The expression for output sum and carry out is given by

Si P i C i 1
(13)

We can select the product value,whichever we want to

calculate by using multiplexer. Based on the control input
given to the multiplexer, output will be selected. In this
multiplier, four 16x16 result will be produced. In 8x8
multiplication, LSB of the both multiplier and multiplicand
is multiplied in first 8x8 multiplier,LSB of the multiplier and
MSB of the multiplicand is multiplied in 2 nd 8x8 multiplier,
MSB of the multiplier and LSB of the multiplicand is
multiplied in 3rd 8x8 multiplier, MSB of the both
multiplicand and multiplier is multiplied in 4 th 8x8
multiplier which is present in the processing element.
Likewise 16x16 bit multiplication is performed.
The result, which is produced by th processing element is
given to the CLA adder for addition(for partial product
addition).
3

All Rights Reserved 2012 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR)

Volume 1, Issue 1, July 2012

IV.

EXPERIMENTAL RESULTS

The proposed multiplier is implemented by using Verilog

HDL language in Quartus II 9.1 software. Multi-precision
multiplier is implemented by using both array and vedic
multiplication. These two methods are implemented and
provides the output.

Timing analysis report provides the propogation delay

time used for calculation is 43.369ns without any failed
paths which is shown in table I.

Figure 8 Simulation output for multiprecision multiplier using array

multiplication technique

The output shows that in first interval all input a and b (32
bits) are having assigned as high. If we convert these value
in to unsigned decimal, we will get the input value which is
given at 1st interval. Likewise, if we need various input,we
can change the input value by assigning the input value at
LSB and MSB of the input.
Major factor like area and delay is compared for both
array and vedic technique by using quartus II software.

Figure 10 Simulation output for multiprecision multiplier using vedic

multiplication technique

Figure 10 shows that the simulation report for MP multiplier

based on vedic mathematics. Based on the LSB and MSB
value of the input operands the output is produced. In first
column MSB of a, LSB of input b is assigned as high. So we
can get the output only in the particular multiplication
output which uses those bit value for multiplication.

Figure 9 Compilation Report for MP multiplier based on array technique

Figure 9 illustrates that the total logic elements which is

used for MP multiplier based on array multiplication
technique is 3460 out of 68416 logic elements.
Table I Timing analysis report for MP multiplier based on array
technique

Figure 11 Compilation report for MP multiplier based on vedic technique

Figure 11 illustrates that the total logic elements which is

used for MP multiplier based on vedic multiplication
technique is 2784 out of 68416 logic elements.
Table II Timing analysis report for MP multiplier based on vedic
technique

4
All Rights Reserved 2012 IJSETR

International Journal of Science, Engineering and Technology Research (IJSETR)

Volume 1, Issue 1, July 2012

Timing analysis report provides the propogation delay

time used for calculation is 36.083ns without any failed
paths which is shown in Table II.
Table III Performance comparison of array and vedic based MP
multiplier

LOGIC
ELEMENTS
USED
(AREA)

PROPAGATION
DELAY

ARRAY 8x8
AND 16x16

3460

43.369ns

VEDIC 8x8
AND 16x16

2784

36.083ns

MULTIPLIER

Table III compares the result of area and delay of array

and vedic based MP multiplier. The result shows that vedic
muliplication based MP multiplier is the best multiplier
compare to array based MP multiplier in terms of area and
delay.

Implementation, IOSR Journal of VLSI and Signal Processing

(IOSR-JVSP) Volume 4, Issue 2, PP 29-35 , Mar-Apr. 2014.
[4] Subhash Kulkarni,Linganagouda Kulkarni,Vaijyanath kunchigi, Low
power Square and Cube Architectures Using Vedic Sutras, Fifth
International Conference on Signals and Image Processing, 2014.
[5] Sahana S Bhandari, Shreyas Srinath, Time Efficient Equations to
Solve Calculations of Five Using Recursion Method, International
Journal of Engineering Research and General Science , ISSN 20912730,Volume 2, Issue 4, June-July, 2014.
[6] Kripa Mathew, S.Asha Latha, T.Ravi, E.Logashanmugam, Design
and Analysis of an Array Multiplier Using an Area Efficient Full
Adder Cell in 32nm CMOS Technology, The International Journal
Of Engineering And Science (Ijes) Volume 2 ,Issue 3 ,Pages 816,2013.
[7] Dinesh Kumar and Girish Chander Lall, Simulation And Synthesis
Of 32-Bit Multiplier Using Configurable Devices,International
Journal of Advances in Engineering & Technology, Vol. 5, Issue 2,
ISSN: 2231-1963, pp. 216-223, Jan. 2013.
[8] Deepali Chandel1, Gagan Kumawat2, Pranay Lahoty3, Vidhi Vart
Chandrodaya, Shailendra Sharma5, Booth Multiplier: Ease of
multiplication, International Journal of Emerging Technology and
Advanced Engineering, ISSN 2250-2459, ISO 9001:2008 Certified
Journal, Volume 3, Issue 3, March 2013.
[9] Akhalesh K. Itawadiya, Rajesh Mahle, Vivek Patel, Dadan Kumar,
Design a DSP Operations using Vedic Mathematics, International
conference on Communication and Signal Processing, April 3-5,
2013.
[10] Reza Azarderakhsh and Arash Reyhani-Masoleh, Low-Complexity
Multiplier Architectures
for
Single
and
Hybrid-Double
Multiplications in Gaussian Normal Bases, IEEE Transactions On
Computers, Vol. 62, No. 4, April 2013.
[11] Anju, Performance Comparison of Vedic Multiplier and Booth
Multiplier, International Journal of Engineering and Advanced
Technology (IJEAT) ISSN: 2249 8958, Volume-2, Issue-5, June
2013.
BIOGRAPHY

V. CONCLUSION
The design of 16x16 MP multiplier based on both array
and vedic multiplication technique have been implemented
on QUARTUS II 9.1. The prorpagation delay in the vedic
based MP multiplier is 36.083ns. It is therefore seen that the
vedic based MP multiplier is superior in all respect like
delay and area while compared to MP multiplier based on
array multiplication technique. Array multiplier requires
more area,power and delay.UT, Nikhilam and Anurupye are
such algorihms which can reduce the delay, area, power and
hardware requirements.
Future scope of this project will be extension of bit range
like 32 bit, 64 bit etc., It will be used to implent in
controllers, DSP processors, Multimedia processors etc.,
REFERENCES
[1]

[2]

[3]

P.Santhini was born in Tamilnadu on 1991. She is a M.E. student of

Applied Electronics department in IFET College of Engineering,
Villupuram, India. She completed her Bachelor of degree in
Electronics and Instrumentation Engineering in Anand Institute of
Higher Technology, Chennai, India in the year 2013.
B.Sahaya Jenila was born in Tamilnadu on 1992. She is a M.E.
student of Applied Electronics department in IFET College of
Engineering, Villupuram, India. She completed her Bachelor of
degree in Elecronics and Communication Engineering in Sri
Manakula Vinayagar Engineering College, Puducherry, India in the
year 2013.

Dr.B.Elizabeth Caroline, M. E., Ph.D., is a Electronics and

Communication Engineering graduate of 1992 Batch from Karunya
Institute of Technology, Coimbatore .She obtained her Master degree
in Communication systems in the year 1999 from Regional
Engineering College (NIT) ,Trichy. She was awarded Ph.D. (Optical
signal processing) by Anna University, Chennai,Tamil Nadu, India in
2010.

Paladugu Srinivas Teja, Design Of Radix-8 Booth Multiplier Using

Koggestone
Adder
For
High
Speed
Arithmetic
Applications,Emerging Trends in Electrical, Electronics &
Instrumentation Engineering: An international Journal(EEIEJ), Vol. 1,
No. 1, February 2014.
Prof. Arun Katara, Prof. Rajkumar Chalse, Prof. Priyanka Ambatkar,
Prof.A.V.Bapat, A New Technique of High Speed Vedic Multiplier
Using Vedic Mathematics, International Journal of Research in
Advent Technology, E-ISSN: 2321-9637, Vol.2, No.2, February 2014.
K.Harika, B.V.Swetha, B.Renuka, D.Lakshman Rao, S.Sridhar,
Analysis of Different Multiplication Algorithms & FPGA

5
All Rights Reserved 2012 IJSETR