Digital Logic & Processor

Experiment 5

Monsoon, 2008
Latches and Flip-flops

In this experiment, the two basic modules required for the design of sequential circuits LATCH
for asynchronous circuits, and FLIP-FLOP for synchronous circuits will be studied. Latches
using NAND and NOR gates will be separately assembled and tested. The basic operation of
master-slave R-S and J-K flip-flops will then be studied by combining two latches to make a flipflop. All ICs used in this experiment belong to the CMOS CD40xx family.

A. NAND and NOR Latches

1. Assemble a NOR latch using two gates from the CD4001 chip, with the R and S inputs
connected to two Input Switches and the Q and Q outputs displayed on two LED Displays.
Observe and tabulate the sequence of Q and Q in response to the following input sequence:
S R = 01, 00, 10, 00, 01, 10, 01, 00, 11, 00, 10, 11, 00, 01, 11, 00.
Interpret the observed result and verify the latch operation.
14

13

12

11

10

8
R

VDD

CD4001
Q

Gnd
S
1

Fig. 5.1 NOR Latch using CD4001 Quad 2- input NOR Gate
2. Repeat the experiment with a NAND latch assembled using two gates in the CD4011 chip,
applying the following sequence of inputs through two Input switches:
S R = 10, 11, 01, 11, 10, 01, 10, 11, 00, 11, 01, 00, 11, 10, 00, 11.
14

13

12

11

10

8
S

VDD

CD4011
Gnd

Q
R

Fig. 5.2 NAND Latch using CD4011 Quad 2- input NAND Gate

B. Master-Slave Flip-flop
1. The two latches tested in part A have now to be combined to make a master-slave flip-flop,
which consists of two interconnected latches the Master latch and the Slave latch. The R-S
inputs and the Q-Q outputs of the two latches are indicated by the subscripts M and S. The
interconnection logic of the latches has to ensure the following actions:
(i) Master latch stores the finally required output when the Clock input CK = 1.
(ii) Slave latch output Q QM when the Clock input CK = 0.

RS

SM

QM
CK

CK
Q
R
SS

QM

RM

Fig. 5.3 R-S Master-Slave Flip-flop Circuit

2. Assemble the circuit given in Fig. 5.3 by using the remaining gates in the CD4001 and
CD4011 chips. Verify theoretically that the circuit implements the required logic for the R-S
inputs of the Master and Slave latches:
RM = R CK, SM = S CK, SS = QM CK and RS = QM CK.
3. Connect the R and S inputs to two Input Switches, and display SM, RM, QM, SS, RS and Q on
LED Displays. Apply the same sequence of R-S inputs as used in step 1 through the Input
Switches, applying a clock pulse through the MANUAL CLOCK at each step. Tabulate the
values of the R-S inputs and all the displayed variables, both after the 0 1 transition and
after the 1 0 transition of the CLOCK pulse for each step. Interpret the results properly and
verify the truth table of the R-S flip-flop.
RS

SM

QM
CK

CK

K
SS

QM

RM

Fig. 5.4 J-K Master-Slave Flip-flop Circuit

4. Modify the circuit of Fig. 5.3 into that of Fig. 5.4 by using two 4-input NAND gates from a
CD4012 chip (Pin connection given in Fig. 5.5) as 3-input gates. Connect the unused inputs
of the 4-input NAND gates to the HIGH (VCC) level. Repeat step 3, with S-R replaced by J-K,
for the J-K flip-flop. Verify theoretically that the circuit does realise the required logic for the
R-S inputs of the Master and Slave latches constituting a J-K Master-Slave flip-flop:
RM = K Q CK, SM = J Q CK, SS = QM CK and RS = QM CK.
14

13

12

11

10

8
J-K FLIP-FLOP TRUTH TABLE

VDD
CD4012
Gnd

Fig. 5.5 Pin Connection of CD4012

Dual 4-input NAND gate

ACTION

Qn+1

HOLD

CLEAR

SET

TOGGLE