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Q1:WhatisUVM?WhatistheadvantageofUVM?

VLSIEncyclopedia
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Ans:UVM(UniversalVeriicationMethodology)isastandardizedmethodologyforverifyingthe
bothcomplex&simpledigitaldesigninsimpleway.
UVMFeatures:
Firstmethodology&secondcollectionofclasslibrariesforAutomation

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UVMstandardizedundertheAccelleraSystemInitiative

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Registermodeling
Q2:UVMderivedfromwhichlanguage?
Ans:HereisthedetailedconnectionbetweenSV,UVM,OVMandothermethodologies.

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Q3.Whatisthedifferencebetweenuvm_componentanduvm_object?
OR
Wealreadyhaveuvm_object,whydoweneeduvm_componentwhichisactuallyderived
classofuvm_object?

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Ans:
uvm_component:

2016(8)
LABELS

QuasiStaticEntity(afterbuildphaseitisavailablethroughoutthesimulation)
Alwaystiedtoagivenhardware(DUTInterface)OraTLMport
Havingphasingmechanismforcontrolthebehaviorofsimulation
ConigurationComponentTopology

DDR3
DDR4
DigitalDesign
LogicGates
PCIExpress

uvm_object:

StateMachine

DynamicEntity(createwhenneeded,transferfromonecomponenttoother&then
dereference)

SystemVerilog

NottiedtoagivenhardwareoranyTLMport

TipsandTricks

Notphasingmechanism

Verilog

Timinganalysis

VHDL

Q4:Whyphasingisused?Whatarethedifferentphasesinuvm?
Ans:UVMPhasesisusedtocontrolthebehaviorofsimulationinasystematicway&executein
a sequential ordered to avoid race condition. This could also be done in system verilog but
manually.
1.ListofUVMPhases:
2.buid_phase
3.connect_phase
4.end_of_elaboration_phase
5.start_of_simulation_phase
6.run_phase(task)
SubPhasesofResetPhase:
pre_reset_phase
reset_phase
post_reset_phase
pre_conigure_phase
conigure_phase
post_conigure_phase
pre_main_phase
main_phase
post_main_phase
pre_shutdown_phase
shutdown_phase
post_shutdown_phase
7.extract_phase
8.check_phase
9.report_phase
Belowiguremakesitmoreclear

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Q5:Whichuvmphaseistopdown,bottomup&parallel?
Ans:Onlybuildphaseisatopdown&otherphasesarebottomupexceptrunphasewhichis
parallel.Thebuildphaseworkstopdownsincethetestbenchhierarchymaybeconiguresowe
needtobuildthebranchesbeforeleafs
Q6:Whybuildphaseistopdown&connectphaseisbottomup?
Ans: The connect phase is intended to be used for making TLM connections between
components, which is why it occur after build phase. It work bottomup so that its got the
correctimplementationallthewayupthedesignhierarchy,ifworkedtopdownthiswouldbe
notpossible
Q7:Whichphaseisfunction&whichphaseistask?
Ans: Only run phase is a task (time consuming phase) & other phases are functions (non
blocking)
Q8:Whichphasetakesmoretimeandwhy?
Ans: As previously said the run phase is implemented as task and remaining all are
function.runphasewillgetexecutedfromstartofsimulationtotilltheendofsimulation.run
phaseistimeconsuming,wherethetestcaseisrunning.
Q9:Howuvmphasesinitiate?
Ans: UVM phases initiate by calling run_test(test1) in top module. When run_test() method
call,itirstcreatetheobjectoftesttop&thencallallphases.
Q10:Howtestcasesrunfromsimulationcommandline?
Ans:Intopmodulewriterun_test();i.e.Don'tgiveanythinginargument.
Thenincommandline:+UVM_TESTNAME=testname

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Labels:InterviewQuestions,UVMInterviewQuestions,UVMMethodology,UVM/OVM
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12comments:
shubham_dce 23January2016at09:04
agoodcollectionofquestions
Reply
Replies
VLSIEncyclopedia

7May2016at23:07

ThanksShuham..!!
Reply

Rikkirevs 29February2016at20:04
Q&Aareveryusefulandinformative,
lastlineoftheanswerin9thquestionitmightbe"ischildclassofuvm_resource_db"Ithink,check
once.
Reply
Replies
VLSIEncyclopedia

4March2016at20:49

ThanksRikki,
Thatwasatypoinanswer.Corrected..!!
Thanksonceagain.
Reply

sarangsamangadkar 20March2016at05:45
Verynice..Helpfulforinterviews...
But,Expectingmorequestions!Pleasepostasmuchaspossible...
Reply
Replies
VLSIEncyclopedia

7May2016at23:05

ThanksSarang,
Surewewillkeepupdatingthissection.Pleaseletusknowifyouhaveanysuggestions.
Regards,
TeamVLSIEncyclopedia
Reply

Digvijay 5April2016at06:47
Nicepieceofinformation.
Thankyou!!
Reply

Replies
VLSIEncyclopedia

7May2016at23:06

ThanksDigvijay..!!
Reply

vansh 27July2016at23:46
Greatexplanations.Pleaseaddmorequestions.
Reply
Replies
VLSIEncyclopedia

8October2016at05:13

ThanksVansh,
Weareinprocesstoaddmorequestions.Ifyouhaveanyquestionthatcanbeaddedto
this section then please write to us with Question and detailed answer at
info@vlsiencyclopedia.comwewouldbegladtomentionyouascontributor.
Thanks,
TeamVLSIEncyclopedia
Reply

Unknown 6October2016at04:48
Hinicecollection..
Iwantyoutoaddmorequestionson
1.virtualsequencer
2.sequencerdriverhandshake
3.get()andset()methodsusedinconigdb
Thankyou
Reply
Replies
VLSIEncyclopedia

8October2016at05:14

ThanksUser,
Weareinprocesstoaddmorequestions.Ifyouhaveanyquestionthatcanbeaddedto
this section then please write to us with Question and detailed answer at
info@vlsiencyclopedia.comwewouldbegladtomentionyouascontributor.
Thanks,
TeamVLSIEncyclopedia
Reply

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