AMS Design and Verification Strategies

Lewis Sternberg
lewis@qualis.com
Qualis Design Corporation
Three Centerpointe Drive
Suite 250
Lake Oswego, OR 97035 USA
www.qualis.com

ABSTRACT
Cost and time-to-market are the overwhelming predictors of success -- both for your designs
and your career. By learning and using AMS verification techniques you can avoid being a highly
visible project bottleneck and incurring expensive design iterations.
This paper presents a design flow and methodology suited for challenging AMS projects.
Not only is a more successful project (and career) the result, but also you can spend your nights
and weekends away from the office.

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INTRODUCTION
In the past, the focus on producing AMS ICs has been on the technical challenges of
fabricating wafers with differing technologies economically, while maintaining noise immunity
between the digital and analog circuitry. While these issues are perennial, another issue has come
to the forefront: design and verification methodology.
AMS horror stories are common place:
Missed deadlines
DOA chips
Excessive chip turns
Cancelled projects
How can this be? Analog design and verification methodologies have lagged far behind
advances in digital and AMS technologies what once worked for small analog ICs now destroys
large AMS chip projects.
The methodology presented in this paper is based on behavioral models using an AMS
hardware description language (HDL), such as VHDL-AMS and Verilog-AMS.
From the digital side, the methodology looks like structured verification techniques
using behavioral models such as bus functional models (BFMs) to produce test
harnesses.
From the analog side, the methodology looks like top-down design with bottom-up
verification with behavioral modeling.
From the systems side, the methodology is a combination of 1) basic systems design
and simulation resulting in a specification written in an HDL; and 2) systems-level
testing using proven and tested behavioral models.
From the test engineers side, the methodology looks like a virtual test where the
tester program can be developed using behavioral models before first silicon.
From the customers point of view, the process results in known good simulatable
models usable for design many weeks earlier -- without the IC manufacturer having
to worry about losing IP trade secrets.
Finally, from everyones point of view, the methodology results in a 1000x+-simulation
speed-up and more dependable schedules.

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HISTORIC PERSPECTIVE
Over the past two decades, digital methodologies have advanced from gate-level schematic
capture and manual tape-out to widespread use of HDLs, synthesis tools, formal verification, and
more. Meanwhile, even though analog tools have tended to lag behind, analog and AMS HDLs
have existed for over a decade1 and AMS extensions have been added to digital HDLs2. Despite
these advances in analog computer-aided engineering (CAE) tools, analog methodologies have
largely remained unchanged for decades. Typical methodologies go something like this:
1.

Create a Design Specification from marketing requirements and control-system level

simulations.

2.

Design the circuitry at the transistor level using schematic capture tools.

3.

Verify the design using a transistor-level simulator (e.g. SPICE) until the design is
fully verified or the simulations take so long that it would be faster to just:

4.

Tape-out, prototype, and bench test the IC.

5.

Repeat steps 2-4 as necessary.

This process has proven itself to work well with designs of several dozen transistors
implemented on a small wafer with limited mask costs and quick fab turn-around. This scenario
is common among analog IC manufacturers and in-house (captive) IC units. However, this
process breaks down with larger analog ICs, and it can be disastrous in large AMS ICs. For
example,
If blocks in one domain (digital/analog) are in the feedback loop of another domain,
the circuit can be unverifiable in simulation. The result is excessive chip turns.
Mask charges can be on the order of $100k, while fab turn-around can be many
weeks. Repeated chip turns can destroy any potential profitability of the design.

MAST HDL introduced by Analogy Inc. in 1987.

IEEE 1076_1-1999 (VHDL-AMS standard). AMS extensions to Verilog (IEEE 1364) are being added at this time.

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THE PREVALENT METHODOLOGY

The methodology largely in use at this time begins with the Design Specification. From the
spec, three efforts unfold:
Digital design (RTL coding)
Digital verification
Analog design
Figure 1 illustrates the key points of the prevalent methodology. However, note that the
figure below misrepresents the prevalent methodology technique in that it does not show any
feedback loops. In reality there are small feedback loops between synthesis, layout, and
RTL for timing and power adjustments. Also, there are larger loops as bugs are found in the
physical chip requiring the design effort to be reiterated

Prevalent Methodology
Debug
Debugschedule
schedule
cant
cantbe
bepredicted
predicted
reliably.
reliably.
RTL Coding

Spec

VP

TB
Coding

Ship

Synthesis
Top Tests
RTL+TB Debug

Prod Test Dev

Layout
& Fab

Analog Design and Simulation

Feedback loops
Feedback loops
exist, but are
exist, but are
left off here.
left off here.

Often
Oftenonly
onlyminimal
minimal
verification
verificationpossible.
possible.

System Tests

Impossible
Impossibledue
dueto
to
simulation
times.
simulation times.

VP : Verification Plan
TB : Testbench
Prod Test Dev : Production Test Development

Figure 1 Prevalent methodology makes it hard predict the RTL and TB debug schedule, limits verification of analog
partitions on large systems to minimal levels only, and postpones production test development until after fabrication.

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Digital Verification Schedule Is Unpredictable

It is important to realize that the digital verification effort is significant, and
can create over twice as much code as the RTL coding. Once the RTL is
designed, both the RTL code and the testbench (TB) code are debugged in
unison. The result of this flow is that bugs in the RTL and the TB are difficult to
find because:
There is more code for any one bug to hide in
There is a significant simulation turn-around delay because of the size of
the system being simulated
One key impact of this is that the RTL and TB debug schedule cannot be
predicted reliably.
Analog Verification Is Limited
The analog design effort also begins with the Design Specification. The
analog partition is designed and simulated at the transistor level without an
independent verification effort. If the analog partition is sufficiently large,
simulation turn-around delay significantly reduces the designers ability to verify
the circuit beyond minimal levels.
System Tests Are Euphemism
Once the design is completed and the digital partition synthesized, the design
is ready for layout and system tests. Note here, that system test is a
euphemism, as the RTL representation of the entire digital partition alone can
take up to a week to simulate (longer than the MTBF of the computer operating
system and network). In reality, with this methodology, system tests are done on
the hardware at the very end of the process not in simulation.
Not until the chip itself is fabricated can the development of production tests
begin. This effort takes several weeks, which cannot (in this paradigm) begin
before first silicon.
Needless to say, the customers efforts cannot begin in earnest until shipment
begins, further delaying time-to-profit.

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A LOW-INVESTMENT MEDIUM-PAYOFF SOLUTION

The typical perception of the problem of producing an AMS design focuses on the
importance of verifying designs before tape-out. While this paper describes a thorough, highpayoff solution to this problem, it should be noted that a simpler solution exists that is
appropriate for circuitry with loose digital/analog feedback loops. This time-honored
engineering technique can be described with the mundane term: cheat.
A less provocative term, pretend is perhaps more appropriate:
From the digital domains perspective, pretend that the analog circuitry is digital by
modeling it in the digital HDL from a high-level perspective or, if necessary in the Zdomain.
From the analog domains perspective, pretend that the digital circuitry is analog
not by modeling gates on the transistor level, but by modeling digital blocks
behaviorally.3

If behavioral modeling is not available with your analog simulator, the digital portion may be modeled as macromodels or
as a time-averaged analog transfer function.

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Figure 2 illustrates this solution.

Low-Investment Medium-Payoff Solution

Digital

Analog

Analog

Digital

Analog

Analog Simulation

Digital

Digital Simulation
Modeled
Modeled
in
inanalog
analog

Modeled
Modeled
in
indigital
digital

Figure 2 In the Low-Investment Medium-Payoff solution the analog domain models the digital circuitry behaviorally and
the digital domain models the analog circuitry in the digital HDL. This solution is appropriate for circuitry with loose
digital/analog feedback loops.

An advantage of this technique is that the designers can implement it using the tools currently
in use. It requires neither additional CAE license fees nor new tools to learn. A disadvantage of
this technique is that, while it optimizes making the most of available CAE tools, it tends to
minimize the productivity of the engineer.

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A HIGH-INVESTMENT LOW-PAYOFF SOLUTION

The most apparent problem with AMS design techniques is that the digital and analog
partitions are simulated separately. The most obvious solution is to simulate them together in a
mixed-signal simulator that supports the HDL used by the digital engineers (e.g. VHDL and/or
Verilog) and SPICE-like transistor-level simulations used by analog engineers.
Low-Level Simulation Creates Untenable Simulation Times
The problem with this technique is that maximum license fees are paid, and
more importantly, that the least benefit is received from the CAE tools. In fact,
using this technique, simulation times may become untenable.

High-Investment Low-Payoff Solution

Low-level
Low-levelsimulation
simulation
creates
untenable
creates untenable
simulation
simulationtimes.
times.

Analog

Digital

Very
Veryslow
slow
Extremely
Extremely
slow
slow

Hours-long
Hours-longsimulations
simulationsturn
turn
to
days-long
simulations
to days-long simulations

June

Figure 3 In the High-Investment Low-Payoff solution the digital and analog partitions are simulated together.This
solution often creates untenable simulation times.

Particularly vexing is the situation where the design is not appropriately

partitioned and high-frequency digital clocks enter the analog simulation, causing
simulations times to increase by orders of magnitude, while simultaneously
reducing the accuracy of the analog simulator.
The critical problem with this technique is that the analog partition is being
simulated at the lowest (transistor) level. While it is ultimately necessary to verify
each analog block at this level, it is wasteful to drag this detail into higher-level
design and verification simulations.

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Long Simulation Times Render Systems Unverifiable

The importance of simulation time cannot be overstated. Long simulation
times render systems unsimulatable and unverifiable:
One-to-five-minute simulations: maximum engineer productivity
Hour-long simulations: too long for rapid design or test development
Day-long simulations: too long for design or debugging
Week-long simulations:
windows

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A HIGH-INVESTMENT HIGH-PAYOFF SOLUTION

As with quantum shifts in physics, this methodologys high-payoff (more reliable design
process) simply cannot be reached by making many incremental low-investment low-payoff
changes. While small changes would seem to represent lower risks, the best payoff these changes
can offer is offsetting the problems of the prevalent methodology (presented on page 4).
The prevalent methodology is well suited to smaller designs and incremental changes.
However it has proven itself inadequate to the task of large analog and AMS designs. To make
this shift while continuously reducing time-to-profit requires a rethinking of the methodology
itself.
By using an AMS HDL such as VHDL-AMS, Verilog-AMS or MAST, you can reap the
benefits of AMS simulation and the advantages of behavioral modeling:
Top-down design
Bottom-up verification
Much faster simulations
In this methodology, the design is simulated at the highest level using behavioral models of
the blocks at this level.

High-Investment High-Payoff Solution

High-level
High-levelsimulations
simulations
optimize
simulation
optimize simulation
times.
times.
Behavioral
block

Behavioral
block

Behavioral
block

Beh
block

Behavioral
block

Figure 4 In the High-Investment High-Payoff solution the design is simulated at the highest level using behavioral
blocks

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Top-Down Design Keeps Simulations Short

Once the design is known to work at this level, the blocks are then broken
down to lower levels of abstraction until the implementation level is reached
transistor level in the analog partition or gate level in the digital partition. This
activity is illustrated in Figure 5.

High-Investment High-Payoff Solution

Once
Oncetop-level
top-levelworks,
works,
move
to
lower
levels
move to lower levels
of
ofabstraction.
abstraction.
Top-down
Top-down
design
design

Bottom-up
Bottom-up
characterization
characterization

Once
Oncebottom-level
bottom-level
works,
works,back-annotate
back-annotate
characteristics.
characteristics.

Figure 5 Once the design is known to work, move to lower levels of abstraction

Multiple design groups can work on individual blocks. Each group designing
their own block to the implementation level, while simulating their portion with
behavioral models of the rest of the design.

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Bottom-Up Characterization Increases Accuracy

When the implementation level is reached, bottom-up characterization can be
applied. That is, design-critical characteristics of the individual blocks (such as
delay, impedance and phase shift) can be measured and applied to the higherlevel models. In this way, the higher level models have the same accuracy as the
lowest level models without the CPU-intensive low-level resolution.
An additional advantage is any block can be simulated at the implementation
level within a system with the other blocks represented behaviorally. In this way,
any portion of the design can be seen to work in the whole, without having to
simulate the entire system at the transistor or gate level.
With this methodology, simulations that would normally take days for a large
design can be run in minutes, without any loss of accuracy.

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THE HIGH-INVESTMENT MAXIMUM-PAYOFF SOLUTION

While the High-Investment High-Payoff solution results in significant benefits, it does not
take full advantage of the power of AMS behavioral modeling and the resultant IP. If highly
accurate behavioral models are being created, they might as well have maximum use throughout
the development cycle. As well, if engineers on the staff are trained to create behavioral models,
then modeling should be used in the entire development cycle when appropriate.

High-Investment Maximum-Payoff Solution

Highly
Highlyparallel
parallelwork
workflow
flow

Ship Beh Models

System Tests / Regression Testing

System Design
Executable
Spec

RTL Coding

Synthesis
Top Tests

VP

Ship

Layout
& Fab

RTL Dbg

Prod Test Dev

TB Cdg + Db

Beh
Analog Design and Simulation
Feedback loops
Feedback loops
exist, but are
exist, but are
left off here.
left off here.

VP : Verification Plan
Beh : Behavioral modeling
TB Cdg + Db : Testbench coding and debug
RTL Dbg : RTL debug

Fastest
Fastesttime
timeto
tomaximum
maximumprofit
profit
Prod Test Dev : Production Test Development
Ship : Make money

Figure 6 The High-Investment Maximum-Payoff solution takes full advantage of the power of AMS behavioral
modeling and the resultant IP

Parallel Work Flow Maximizes Payoff

As with Figure 1, The Prevalent Methodology, note that this solution also has
feedback loops that are not shown in the figure above. Figure 6 highlights the
benefit that as efforts are paralleled, information about design problems is
available sooner and verification is more rigorous. Bugs can be fixed more
quickly, iterations are faster and there are fewer of them. As well, the
thoroughness of the verification effort and the speed of the iterations are greatly
increased by the incredibly faster simulation turn-around made possible with the
use of behavioral models.

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Executable Specification Is Verifiable

In the figure, the term Executable Spec signals the turning point in this
paradigm shift. In this solution, there are no ambiguities in the interpretation of a
loosely worded spec. The spec itself is written, not in the vague vernacular, but
behaviorally in an AMS HDL and is directly verifiable through simulation. In a
larger system, the executable spec is actually a midpoint in the top-down design
of the system itself. This spec includes the pin-level characteristics and
functionality. Although the written specification is significant in developing the
verification plan (VP) and in interpreting the results of simulations, it is
subservient to the executable spec.
Design and Verification Run in Parallel
Once the specs are approved, then, in parallel with the design effort, an
independent verification effort begins on three fronts:
System engineers begin work on the system-level testing and regression
test suite
A verification plan is written including prioritization of tests:
Mission-critical features are to be tested before non-critical features
Must-pass tests are clearly identified
Other tests are ranked because typically there is insufficient time to
test all feature permutations
Behavioral models such as BFMs are written for the test harness and
digital partition so that the testbench can be debugged before the RTL is
ready. The digital behavioral models are then available as appropriate for
AMS and system testing.
In addition,
Behavioral models of the analog partition are written as part of the topdown, bottom-up design technique delineated in the previous section.
The analog behavioral models are then available as appropriate for AMS
and system testing.

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RTL Verification Goes Faster

When the RTL is ready for verification, bug-free testbenches are available.
RTL verification runs much faster because the effort is not delayed by debugging
the testbenches. Only those portions of the digital partition being tested at any
one time need be represented in RTL. The remainder of the system can be
represented using verified behavioral models, which results in much faster
simulations and in the ability to focus on the portions of the code under test.
More timesavings are possible by using virtual testing. By combining
verified behavioral models with behavioral models of the production tester4, test
engineers can begin working on their test programs before first silicon.
Time-to-Profit Is Maximized
The ultimate time saving is time-to-profit. Customers can begin to design-in
the chip, even while chip design is proceeding because the development effort shown
here begins with verified behavioral models. Because theyre behavioral, these
models can be shared with customers without divulging trade secrets. Not only is
tested, production silicon available much sooner, but also the customers are fully
committed to your chip and theyre ready to put it into production almost
immediately!

The Virtual Test division of IMS, Inc. supports digital and AMS testers from a number of tester vendors. Teradyne, Inc.
similarly provides virtual test tools for its own AMS testers.

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CONCLUSIONS
One of lifes paradoxes is that it takes more time and money to get things wrong than to get
them right. As with any job, having the right tools is just part of the story. How theyre used
methodology is the determining factor in getting things right. In the case of AMS chip
designs, its also the difference between a functional chip passing spec on time and in budget, and
interminable ulcer-inducing chip turns and lost sleep.

REFERENCES
www.analogy.com Home page of Analogy (Avant!)
www.eda.org/verilog-ams Open Verilog International Verilog Analog Mixed-Signal Group
www.janick.bergeron.com Web page for: Bergeron, Janick, Writing Testbenches: Functional
Verification of HDL Models, Kluwer Academic Publishers
www.janick.bergeron.com/guild Moderated electronic mail forum dedicated to the
verification of electronic designs and the software that runs them
www.mentorg.com/ams Mentor Graphics web page for Analog Mixed Signal news and
events
www.teradyne.com/prods/icd/vx/ Home page of Teradyne VX Software
www.virtualtest.com Home page of IMS Virtual Test Division
http://www.wkap.nl/book.htm/0-7923-9516-6 Web page for: Mantooth, Alan H,
Fiegenbaum, Mike F. Modeling with an Analog Hardware Description Language, Kluwer Academic
Publishers

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