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AVR Internal Test

1. If watchdog timer is enabled, it will operate in


A. All the sleep modes
B. Only in power down mode
C. Only in the standby mode
D. Only in the Idle mode
2. Which of the following is NOT true regarding I2C bus?
A. It supports multiple masters
B. It is a two-wire Interface
C. It is slower than SPI interface
D. It is a single master Protocol
3. What is the correct sequence of events that occur when an interrupt occur in
AVR?
1.
The processor executes the ISR
2.
Current instruction execution is completed
3.
Address of the ISR is loaded in the PC.
4.
The address of the next Instruction is stored onto the Stack.
5.
The end of the ISR is indicated by the RETI instruction.
6.
The processor loads the PC with the value stored onto the Stack.
A.
B.
C.
D.

6-1-4-5-3-2
4-3-1-2-5-6
2-4-3-1-5-6
4-3-1-5-2-6

4. What is the default clock source setting in an AVR?


A. External RC Oscillator
B. Calibrated Internal RC Oscillator
C. External Ceramic Resonator
D. External Crystal
5. Which of the following instruction will branch to label if C=1?
A. BRLO label
B. BRSH label
C. BREQ label
D. BRGE label

6. In AVR, X,Y and Z registers are:


A. 16-bit indirect address register pointers for Data Space addressing
B. 8-bit direct address register pointers for Data Space addressing
C. 16-bit indirect address register pointers for EEPROM addressing
D. 8-bit indirect address register pointers for Data Space addressing
7. What is the output of the following instructions:
LDI R16, 0x74
LDI R17, 0x98
ADD R17, R16
NEG R1
A.
B.
C.
D.

0x172
0x0B
0x8E
0xF5

8. What is the value in R20 after the execution of following instructions?


CLC
LDI R20, 0x4D
SWAP R20
ROL R20
ASR R20
A. 0x4D
B. 0xD4
C. 0x54
D. 0xB5

9. AVR instructions which operate only on registers R16 to R31.


A. CLI
B. ROL
C. SBR
D. None of the Above
10. Which of the following USART registers in AVR 8515 share the common I/O
address?
A. UCSRA and UBRRH
B. USCRC and UBRRH
C. UCSRC and UBRRL
D. UCSRA and UBRRL

11. The AVR Microcontroller is a


A. CISC with Harvard Architecture and Big Endian format
B. RISC with Von-Neumann Architecture and Big Endian format
C. RISC with Harvard Architecture and Little Endian format
D. RISC Von-Neumann Architecture and Little Endian format
12. Which of the following does not generate an Opcode?
A. SEZ
B. SLEEP
C. LDI R16, 0
D. .ORG 0
13. After the MULS R16, R17 instruction, the result is stored in which register(s)?
A. R16 and R17
B. R16
C. R1 and R0
D. R31 and R30
14. What value will be sent to PORTC after the execution of following C instructions?
unsigned char num=0x35;
num= num^0xFF;
num=num>>4;
PORTC=num;
A. 0xCA
B. 0x0C
C. 0xAC
D. 0xC0
15. For an 8-bit ADC with Vref=2.56V, the output D0-D7 for analog input 1.7V will be
A. 10101010
B. 11001100
C. 10101110
D. 10110111
16. What is the value on the Stack Pointer after the following instructions
LDI R16, 0x45
OUT SPL, R16
LDI R17, 0x01
OUT SPH, R17
A. 0x4501
B. 0x5410
C. 0x0145
D. 0x1054

17. How many locations of the stack are used when the CALL Instruction is
executed?
A. 1
B. 2
C. 3
D. 4
18. What does the following line of code do?
PORTD &=~(1<<7)
A. It will reset the 7th bit of PORTD without affecting the other bits
B. It will set the 7th bit of PORTD without affecting the other bits
C. It will reset the PORTD
D. It will set PORTD
19. An AVR has128K of memory locations, how many address lines does it have?
A. 16
B. 20
C. 15
D. 17
20. In AVR 8515 data memory bus is of _____bits and program memory bus is of
_____ bits.
A.
B.
C.
D.

8,8
16,16
8,16
16,8