Simple FET DC Bias Circuits

Bob York
 Load-Line and Q-point

Consider the effect of a drain resistor in

the comnon-source configuration: Id
Smaller Rd
+Vdd Vdd / Rd
KVL: Vdd I d Rd Vds Vgs= Vtn + 2.0
RD
Q point

Increasing Vgs
Vdd 1 Larger
Id Vout Id Vds
Rd Rd Rd Vgs= Vtn + 1.5

Vds This is the equation of a line that Vgs= Vtn + 1.0

can be superimposed on the FET
Vgs I-V characteristics as shown at
right. This is the load-line.
Vknee Vdd Vds

The points of intersection represent the allowed device voltages and drain current for the
resistor-FET combination. These are the quiescent operating conditions or Q points, i.e.
the DC bias conditions.
There are a number of possible Q-points along the load-line, depending on the gate voltage. It
is the job of the circuit designer to choose this Q-point.
The choice of Q-point will vary with the circuit application. For simple amplifier circuits a Q-
point in the middle of the saturation region is often desirable.

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 FET DC Biasing

Consider the design of the circuit to set a certain Q-point:

Id Vgs= 4
FET Parameters: Vt 1V 45mA
+10 V
K n 5mA/V 2
RD Vgs= 3
20mA
Design goal: Vout 6 V
Id Vout Vgs= 2
I d 20 mA 5mA

Vds To get a 4V drop across the drain resistor

@ 20mA current requires a resistor value
Vgs 6 10 Vds
10 V 6 V
Rd 200
20mA
The design goal puts the Q-point
right in the middle of the saturation Id 20 mA
region in the I-V curves where
I d K n (Vgs Vt ) 2 Vgs Vt 1V 3V
Kn 5mA/V 2

With a plot of the FET I-V curves we can quickly tell at a glance whether the Q-point is in the
saturation or ohmic region. Without the visual plot we could make an initial guess and then
check to see whether the answer is consistent with this assumption:

Saturation requires: Vds Vgs Vt 10 3 1

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 Simple NMOS Gate Bias Network

The previous design example required two DC sources: a drain supply (+10V)
and a gate supply (+3V)
A simpler solution for enhancement-mode devices is to use just a single supply
at the drain and generate the required gate voltage using a resistor divider:

+10 V

200
+10 V
Voltage divider
to set the gate +6 V Remember: no current flows
voltage required 700 k into the gate. This simplifies
for a certain Id the design and analysis of
20 mA
+3 V the gate bias circuit

300 k

In discrete circuits the gate bias resistors usually have large values. You will
learn why in ECE 2C when we discuss AC amplifiers.
In Integrated Circuit (IC) designs, large resistors take up too much space and
a different approach is taken. We will explore this later.

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 Simple PMOS Biasing Example

+9 V Problem: Find the drain voltage and current Vtp 1V

assuming the following FET parameters:
K p 1mA/V 2
1 M Vsg
2M
Vg The voltage at the gate node is: Vg 9 V 6V
Vsd
2 M 1M
2 M Vout
Id The source-gate voltage is then: Vsg 9 V 6 V 3V
1 k
Assuming the device is in
saturation, the drain current is:
I d 1mA/V 2 3V 1V 4 mA
2

and the output voltage is: Vout I d Rd 4 mA 1k 4 V

Double-check that the device is in saturation: Vsd 9 V Vout 5V

?
Vsd Vsg Vtp 5 3 1
Note: if the drain resistor was increased to 2k the device would no longer be in saturation and
we would need to re-analyze the circuit using the equations appropriate to the ohmic region.

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 Stabilizing the Bias Point: Source Resistance

All examples so far have used a constant Vgs Device #1

bias scheme. ID
Id Device #2
The problem with this approach is evident
when we consider things like temperature Vg
variations or manufacturing tolerances on I d
device parameters. Vds
As shown at right, two different devices can Vgs
yield a large difference in drain current when
biased at the same voltage Vg
Vt1 Vt2 Vg Vgs

A simple solution is to add a source ID

resistance. This provides negative feedback Id
to stabilize the drain current with respect to Vg Vg slope
1
device parameter variations Rs
Rs
Vg Vgs I d Rs I d
Vgs Vs
Vg 1 Another RS
Id Vgs load-line
Rs Rs
If drain current increases due to Vt1 Vt2 Vg Vgs
parameter change, Vs will rise and this
lowers Vgs which in turn reduces Id
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 The Four-Resistor Bias Network

The standard bias network for discrete designs

Id Load-line now a function
+Vdd Vdd of both Rd and Rs
Design Procedure for a given FET
Rd Rs
Specify Q-point (Id and Vds)
RD slope 1
Rg1 Id Net resistance can be
Rd Rs

Increasing
determined from load-line:
Vd
Vdd I d ( Rd Rs ) Vds

Vgs
Ig = 0
Vg Vds
Vdd Vds
Rd Rs
Vgs Vs
Id Vdd Vds
Rg2
RS Often there will be constraints on Rd or Rs imposed by
the application. If Vd or Vs is specified, then
Vdd Vd Vs
Rd or Rs
Id Id
Once Rs and Rd are known we can design the gate bias Id
network. Required Vgs determined from I-V curves. In saturation: Vgs Vt
Kn
Then gate voltage and voltage-divider can be designed according to:
Rg 2 Always double-check that
Vg Vgs I d Rs Vdd Vgs I d Rs the design is consistent
Rg1 Rg 2 with assumptions!

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 FET Bias Building Blocks

Vdd
A FET with drain and gate connected is a common building
block in IC bias networks
Rd
This connection forces the device into saturation such that
Vdd Vout Vout Vgs Vds
I d K n Vout Vt Id
2

Rd
W /L
Common design problems:
Find the Rd that gives a specified Vout or Id

Remember: the device W/L

Vout specified Id specified
ratio can also be

Rd
1
or Rd
Vdd Vt 1 manipulated to vary Kn:

K n Vout Vt Id Kn Id 1 W
K n kn
2 L
Find the Vout or Id for a given Rd

1
Vout Vt 1 4 K n Rd (Vdd Vt ) 1
2 K n Rd

Vdd Vt 1
Id 2
1 1 4 K n Rd (Vdd Vt )
Rd 2 K n Rd
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 Some Examples with Drain-Gate Connection

Can you find Id and Vout in each case?

+5 V +5 V +5 V

4 mA 3 k

Vout Vout
Vout Vout
4 mA 3 k
Assume:

Vt 1V
+5 V +5 V K 1mA/V 2 +5 V

4 mA 3 k
Vout Vout
Vout Vout

4 mA 3 k

-5 V -5 V -5 V
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