Generating FPGA Accelerators
for Chemical Similarity Assessment
Nikolaos Alachiotis
Dept. of Electrical and Computer Engineering
Carnegie Mellon University
Pittsburgh, PA 15217
Email: nalachio@ece.cmu.edu
AbstractNumerical measures of similarity/distance between
objects represented by binary vectors are common in a wide
range of disciplines. Searching in large-scale chemical databases
requires billions of comparisons between molecules that are rep-
resented by binary fingerprints to capture the atomic structure.
The performance bottleneck here is the enumeration of set bits
in vectors (population count). Due to the discrete representation,
similarity measures between binary fingerprints should fit well
to FPGAs. We present an architecture to accelerate binary sim-
ilarity assessment, evaluate various design points, and compare
performance to highly optimized CPU and GPU implementations.
We implement an RTL generation software, SimGenRTL, to
generate accelerators of various sizes based on the proposed
architecture. We find that accelerators with fewer and wider
population counters allow better distribution of the hardware
resources, outperforming significantly accelerators with more and
narrower bit-enumeration components. SimGenRTL is available
for download to allow rapid design space exploration of the
computational core ahead of a full custom system implementation.
I. I NTRODUCTION
A wide range of applications in chemical informatics
rely on similarity calculations as a critical subroutine. Virtual
screening, which relies on compound database searching, has
emerged as a cost-effective in silico method for early-stage
drug design and discovery. Database clustering is also widely
used in pharmaceutical chemistry to create ensembles of
molecules that share similar biological activity. Thus, finding
similarity in multimillion compound databases currently avail-
able (e.g. PubChem [1], 63, 160, 076 compounds, last accessed
March 4, 2015) has a key role in chemical informatics, but also
requires immense computational power.
A common approach to assess chemical similarity between
compounds involves the calculation of similarity measures on
2D fingerprints, i.e., binary vectors of fixed length where each
bit represents the existence or absence of a substructural frag-
ment in a molecule. Albeit conceptually simple, fingerprint-
based similarity assessment has been proven very effective,
and several measures have been proposed [2], with the most
widely used being the Jaccard index/Tanimoto coefficient.
Similarity assessment between objects represented by binary
vectors is employed in other disciplines as well. In population
genetics, genetic polymorphisms (SNPs) are represented by
binary vectors to facilitate association studies.
Assessing similarity between two objects A and B repre-
sented by binary vectors consists of two distinct stages. During
the first stage, a number of population count and accumulate
operations are required to calculate the total number of set
bits in A, B, and their intersection A B. In the second
stage, a similarity coefficient is calculated. Typically, the first
stage is common not only among different chemical similarity
measures (e.g., Jaccard/Tanimoto, Dice, and Cosine) but also
among different applications (e.g, SNP association). However,
it has been reported that 2D similarity calculations can achieve
only up to 65% of the theoretical peak performance on modern
CPU architectures [3]. Based on a performance evaluation of
the SNP association subroutine in the software OmegaPlus [4],
we conclude that such a peak performance deviation might
be associated, to a certain extent, with possible architectural
restrictions of modern x86 CPUs that not allow the efficient
combination, at the microkernel level, of SSE or AVX vector
instructions with the population count instruction supported in
hardware, which operates on regular registers with single-cycle
throughput (available since Intel Nehalem and AMD K10).
Here, we present a versatile reconfigurable architecture
to accelerate fingerprint-based similarity calculations. Further,
we implement SimGenRTL (available at https:// github.com/
alachins/ simgenrtl), an RTL generation software that generates
fully synthesizable Verilog for the proposed architecture for
a variety of parameters such as the number and topology of
the processing units, the width and latency of the population
counters, as well as the required multi-bank memory subsys-
tem. Therefore, it allows rapid design space exploration for
the similarity kernel, and reduces significantly the engineering
effort to adapt the architecture for a device of different size
and/or an FPGA board with different DRAM bandwidth.
II. 2D F INGERPRINT S IMILARITY
According to the similar property principle [2], structurally
similar molecules tend to exhibit similar biological properties
and activity. Given a similarity measure S and a cut-off
threshold value D, compounds A and B are considered similar
if SAB D. Most frequently, chemical similarity is evaluated
in silico using fixed length binary fingerprints, i.e., series
of binary digits. A binary fingerprint is generated using a
subgraph isomorphism algorithm. The atoms and the bonds
between neighboring atoms are examined and organized into
patterns. Thereafter, a bit is set for each different pattern.
Binary fingerprints are usually called 2D fingerprints to dis-
tinguish them from 3D fingerprint schemes that depend on the
compound shape.
When fingerprints have been generated to numerically
represent the compounds under investigation, a measure is

employed to evaluate the similarity between two compounds
from their fingerprints. Given two compounds A and B, with
p, q, and x being the numbers of set bits in A, B, and A B,
respectively, the similarity between A and B can be calculated
by several measures. The most widely used measure is the
Tanimoto coefficient, which relies on the common set bits:
x x
T animotoAB = . (1)
p+qx
Other rarely used measures are Manhattan, Dice, Cosine, and
Euclidean. Typical fingerprint schemes comprise between 164
(MDS fingerprints) and 2,048 bits (Daylight fingerprints).
III. R ELATED W ORK
Haque et al. [3] described a series of fast methods for
population count on modern x86 architectures and a GPU im-
plementation to compute the Tanimoto coefficient. Employing
OpenMP and SSE4.2 intrinsics, a throughput of 217.0 106
coefficients/second (1,024-bit fingerprints) was achieved on
a 4-core Intel Core i7-920 CPU running at 2.93 GHz. Fur-
thermore, an Nvidia GTX 480 GPU implementation achieved
throughput of 1, 157 106 coefficients/second. Maggioni et
al. [5] presented a GPU algorithm and a series of opti-
mizations to compute all-to-all chemical similarity matrices
implementing the Tanimoto, Dice, Cosine, Euclidean, and
Manhattan coefficients. The optimized GPU implementation,
on an Nvidia GTX 460 GPU, can achieve throughput of up to
214.0 106 coefficients/second for computing the Tanimoto
coefficient on 256-bit fingerprints. Ma et al. [6] evaluated
Tanimoto calculations on GPUs when processing low-sparsity
fingerprints. They implemented an integer-based as well as a
sparse vector algorithm. The highest reported throughput was
288.9106 coefficients/second, processing 992-bit fingerprints,
and it was achieved on an Nvidia GTS 250 GPU.
Szanto et al. [7] presented an FPGA accelerator archi-
tecture for reducing virtual screening processing times by
accelerating Tanimoto calculations. The proposed architecture
was mapped to a Virtex-4 LX200 FPGA, and a maximum
operating frequency of 100 MHz was reported. The authors
employ a lookup table-based approach associated with the
similarity cut-off threshold in order to avoid the floating-
point division, a design choice that restricts significantly the
capability of the architecture to accelerate similar or even
identical similarity calculations in other domains. Reported
speedups range between 100X and 200X, from the comparison
of a single FPGA device against industrial software, however
no benchmarking methodology is provided.
IV. R ECONFIGURABLE A RCHITECTURE
The proposed computational core is generated
by SimGenRTL based on the parameters summarized
in Table I. These parameters specify a single design point.
a) Population counter: The population count pipeline
(POPCNT) is outlined in Figure 1. At the lowest level, it
consists of an array of lookup tables (ROM blocks) that are,
by default, mapped to dual-port block RAMs in order to
reduce logic slice utilization by exploiting the large number
of available block RAMs in state-of-the-art FPGAs. The num-
ber of block RAMs per ROM table is controlled by the k
parameter since each table comprises 2k entries. The number
TABLE I. A RCHITECTURE PARAMETERS
Parameter Description
m population counter input bus width (bits)
k population counter LUT port width (bits)
t population counter latency (cycles)
n population counter output width (bits)
number of processing units horizontally
y number of processing units vertically
z number of words in query memory bank
r number of words in result memory bank
o number of result memory banks grouped together
n-bit output
A B
+
m bits
vldin
CLB
delay t-1
latency
t latency
POPCNT
delay
+ +
n bits
rst ACCUM
ROM ... ROM
1c
SMC
vldin
vldout
k bits ... result
m-bit input IEEE-754 fp
Fig. 1. Parameterized population counter (left) and processing pipeline unit
(PPU, right) generated by SimGenRTL.
of ROM blocks in the array depends on the m parameter. The
output of the ROM block is the number of set bits for each
corresponding k-bit input segment, and the final population
count value is computed via an adder-tree reduction structure
with increasing adder width. To achieve high operating clock
frequency, register stages are inserted in between the adders
in the reduction structure.
b) Processing Pipelined Unit: The main processing
pipelined unit (PPU) is illustrated in Figure 1. Initially, a Com-
bining Logic Block (CLB) implements the required operations
to construct a single binary vector to capture the common
set bits between the objects under comparison. The CLB
output vector is validated via the vldin input port to ensure
correctness of the accumulation of the POPCNTs outputs via
the accumulator unit (ACCUM) in the case of input flow
disruptions. In addition to the population counter output width,
the n parameter also specifies the width of the accumulator.
The rst ACCUM input port resets the accumulator when the
two objects A and B are streamed in. The final PPU stage is
the similarity measure calculation (SMC), which implements
the Tanimoto coefficient. The objects A and B are streamed in
cycle by cycle in m-bit segments via the separate input ports,
and a similarity coefficient is computed every l/m cycles,
where l is the smallest multiple of m that is larger than the
length of the objects under comparison.
c) Similarity Core: The similarity core architecture
generated by SimGenRTL is illustrated in Figure 2. The Query
Mem exhibits x dual-port memory banks (QBanks), and each
bank can store up to z number of m-bit segments. Each object
is stored contiguously in a QBank, occupying l/m words,
where l is the smallest multiple of m that is larger than the
length of the object. All QBank ports are connected to the
same read/write address and write enable wires. However,
 Dport 0 RBank RBank
PPU . . . PPU
management logic (FETCH, IMEM, and DECODE units in
CNT
Fig. 3) to set the number of query/database objects and the

. . .
. . .
Dport PPU Block A
y-1 RBank RBank
object length. The FETCH unit retrieves the descriptor from
CNT PPU . . . PPU DRAM, stores it in the IMEM instruction memory, and notifies
CNT . . . CNT
the DECODE unit. The DECODE unit extracts the required
parameters from 8-byte long instructions and configures the
A A
QBank . . . QBank control FSMs, i.e., IControl, CControl, and OControl. All
0 Query Mem x-1 objects are stored in memory in chunks of size that does not
B B
exceed the DRAM row buffer size to achieve high bandwidth.
CNT . . . CNT
When all control units are configured, the DECODE unit
PPU . . .
PPU row PPU
initiates the similarity calculations by enabling the CControl,

y PPUs
which coordinates the operation of the similarity core with the

. . .
. . .

PPU Block B
incoming and outgoing data chunks via synchronization with
PPU . . . PPU the IControl and OContol units, respectively. For each iteration,
PPU column
a number of query chunks is initially loaded into Query Mem.
x PPUs
Therafter, the database objects are streamed in chunks. We
Fig. 2. The similarity core architecture generated by SimGenRTL. employ double buffering for streaming in the database. Each
of the two DMem memory blocks stores a database chunk,
start
Fetch descriptor IMem pass Decode and its objects are reused multiple times depending on z, i.e.,
rdaddr/
configuration parameters the size of the QBanks. To provide fingerprints to the y PPU
descriptor
rdaddr/sync sync CControl sync rows, each DMem memory is organized into y banks of width
IControl OControl m. When results start being stored in the RBanks using one
q_rdaddr/o_rst
q_wraddr/q_wren r_rdaddr wraddr
query data wren of the two available ports, the CControl notifies the OControl
Similarity to start transferring data to DRAM via the second port. Data
Interface

Interface
External

External

DMem Core
coefficient
from multiple RBanks are read per cycle, depending on the o
DMem database results
data parameter, to saturate the available DRAM bandwidth.
Fig. 3. The top-level similarity evaluation architecture.
V. C ODE GENERATION AND E VALUATION

each QBank is assigned a bank ID to allow distributing the a) Code Generation: The RTL generation software
query objects to the available banks during the Query Mem SimGenRTL is implemented in the C language and generates
initialization phase. During processing, the two available ports Verilog for the similarity core and the underlying hierarchy
in the QBanks provide query objects to the CNT blocks which of module instances. The command line below represents an
accumulate the number of set bits and pass the count number invocation example that was used to generate a small similarity
and the query objects to the PPU blocks. The CNT block core (8 PPUs, henceforth denoted by test8 core) for testing.
pipeline is identical to the PPU pipeline without the SMC SimGenRTL -name test8 -m 16 -k 8 -t 4
stage. Each of the two PPU blocks comprises y rows of x PPUs -n 32 -x 4 -y 1 -z 256 -r 256 -o 2
each. A PPU column computes similarity coefficients between
the same query object and a subset of y database objects, while In addition to the required parameters that specify the RTL
each PPU row computes similarity coefficients between the design (Table I), optional parameters allow to select between
same database object and x query objects that are loaded in block RAMs and distributed memory individually for each of
parallel from the x QBanks. The two PPU blocks comprise the modules that instantiate memory blocks, or between using
in total 2xy processing units. An equal number of output FPGA LUTs and DSP48 slices in the adder-tree reduction
memory banks (RBanks) are used to store the results. The structures. The test8 similarity core was mapped on a Virtex5
output memory that comprises the 2xy RBanks is organized SX95T-2 FPGA. To verify correctness, we conducted extensive
into two memory blocks, one for every PPU block, of xy dual- post-place and route simulations using ModelSim 6.3f, as well
port banks each. All RBank ports are assigned a group ID and as by employing the test environment provided by an open-
are driven by the same read/write addresses and write enable source PC-FPGA communication platform [9].
wires. For clarity reasons, the write address and write enable
b) Evaluation: A series of design points were gener-
generation logic for the RBanks is ommitted in Figure 2. Each
ated and mapped on a Virtex7 VX980T-2 FPGA. We assess
RBank group consists of o memory banks.
throughput performance in terms of billion Tanimotos per
d) Top-level Architecture: The similarity core operates second (bTan/sec) for varying number of PPUs and popu-
on a subset of query and database objects. To address the lation count sizes when 1,024-bit fingerprints are processed.
generic problem of all-to-all similarity calculations, compu- Figures 4 and 5 illustrate post-place and route (PAR) resource
tations are conducted on chunks of data iteratively. Each utilization, maximum operating clock frequency (post-PAR
iteration computes the similarity coefficients between a limited static timing report), and estimated throughput performance.
number of query objects and the entire database. The top-level Table II shows the resources for the entire control logic
architecture is depicted in Figure 3. To facilitate the analysis (Control), the similarity measure calculation stage (SMC), and
of arbitrary problem sizes and object lengths, we adopt the the population count module with m = 16 and t = 4. Note
concept of an accelerator descriptor as introduced by Quo et the disproportionately large amount of slice resources occupied
al. [8]. We implement a light-weight version of the descriptor by the SMC floating-point operators in comparison to the
 Similarity Core Evaluation for m=16 and t=4 Similarity Core Evaluation for x=16 and y=1

100 200 100 200

T=0.1 Occupied slices BRAMs Occupied slices BRAMs
Slice registers DSP48 Slice registers DSP48
Slice LUTs Frequency T=0.76 Slice LUTs Frequency

T=0.18
80 180 80 180

T=0.34
Resource Utilization (%)

Resource Utilization (%)

T=1.29
T=0.32

Frequency (MHz)

Frequency (MHz)
60 160 60 160

T=2.42

40 140 40 140

T=0.53

20 120 20 120

0 100 0 100
32 64 128 256 64 128 256 512

Number of Processing Units (PPUs=2xy) Population counter size (width m, latency t=log2(m))

Fig. 4. Resource utilization, maximum frequency, and throughput (bTan/sec, Fig. 5. Resource utilization, maximum frequency, and throughput (bTan/sec,
1,024-bit fingerprints, denoted by T ) for constant population counter size. 1,024-bit fingerprints, denoted by T ) for constant number of PPUs.

TABLE II. O CCUPIED R ESOURCES TABLE III. P ERFORMANCE COMPARISON WITH PREVIOUS WORKS
Resources Control SMC POPCNT 16 4
Occupied Slices 868 448 1 Platform Length bTan/sec FPGA Throughput & Speedup
Slice Registers 1,218 1,888 4 Haque et al. [3], CPU 1,024 0.217 13.7x
Slice LUTs 1,877 1,316 0 Haque et al. [3], GPU 1,024 1.157 Instance A: 2.97 2.6x
BRAM (18Kb)/DSP48 4/0 0/0 1/1 Ma et al. [6], GPU 992 0.288 10.3x
Maggioni et al. [5], GPU 256 0.214 Instance B: 3.19 14.9x

population count module. The latency of the bit enumeration

stage is proportional to the length of the fingerprints, and
rapidly becomes the bottleneck as the fingerprint length in-
creases. Consequently, similarity cores with large number of
PPUs and narrow population counters exhibit poor throughput
performance, as can be observed in Figure 4, since the largest
fraction of resources is allocated for floating-point operations,
which are not performance critical. On the other hand, a mod-
erate number of PPUs allows for significantly wider population
count modules, leading to dramatic latency reduction for the
bit enumeration stage and a significant throughput performance
boost, as can be observed in Figure 5. Table III provides
a performance comparison between two accelerator instances
(A: 44 PPUs, m=512, t=9, 135 MHz, and B: 80 PPUs, m=256,
t=8, 155 MHz, based on 12 GB/s memory bandwidth) and
previous works on microprocessors and GPUs.
VI.
Similarity calculations between binary objects are widely
employed in various domains. While current microprocessor
architectures provide hardware support for population count
operations, deployment with vector intrinsics at the micro-
kernel level leads to suboptimal kernel performance. To this
end, a high-performance accelerator architecture for FPGAs
was presented and compared to third-party highly optimized
software and GPUs codes. Additionally, an RTL generation
software was developed, which allowed extensive design space
exploration. We found that custom FPGA designs are up to
2.6 and 13.7 times faster than GPU and software imple-
mentations, respectively, while performance benefits become
more prevalent when FPGA resources are allocated for wider
pipelined population count modules instead of a high number
of independent pairwise comparison units.
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