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VLSI (B.Tech.)
S.NO Projects Titles Type
Front End(Verilog HDL/VHDL)
1 An Optimized Design of Area efficient FAM for Real time Arithmetic operations IEEE

Video Objects Motion Estimation Architecture using Adaptive Rood Pattern Search(ARPS)
2 IEEE
Algorithm
3 A Nano-Transmitter design for Ultra-Wide Band Communications IEEE

4 A Low-power Variable-length FFT Processor Base on Radix-24 Algorithm IEEE

5 Smart Games applicable Parallel Radix-Sort-based VLSI architecture IEEE

6 Design and implementation of efficient Quaternary Signed Digit Multiplier IEEE

7 3D Pilot Pattern based MIMO-OFDM System for Telecommunications IEEE

8 Area-Delay Efficient Binary Adders in QCA IEEE

9 Low power VLSI architecture for adaptive filter and its application to noise cancellation IEEE

10 Differential Scan-Path: A Novel Solution for Secure Design-for Testability IEEE

11 FIR Filter Design Based on Faithfully Rounded Truncated MCM IEEE

12 Implementation of JPEG2000 using DWT IEEE

13 FPGA implementation of multi operand redundant adders IEEE

14 Multi bit Flip-Flop design for Area efficiency IEEE

15 MDC FFT/IFFT Processor With Variable Length IEEE

16 Built in generation of functional broadside tests using a fixed hardware structure IEEE

17 Constant and high speed adder design using QSD number system IEEE

18 Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool IEEE

19 A Common Boolean Logic(CBL) implementation for modified CSLA IEEE

20 High speed Vedic multiplier using barrel shifter IEEE

21 Bar Code Reader(RFID Gun) with Reliable and Higher Throughput Anti-Collision Technique IEEE

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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A new approach to design fault coverage circuit with efficient hardware utilization for testing
22 IEEE
applications
23 Design of Parallel Carry-Save Pipelined RSFQ Multiplier IEEE

24 Single phase clock distribution using VLSI technology for low power IEEE

25 A VLSI architecture for video object motion estimation using a 2D hierarchical mesh model IEEE

26 High Speed FPGA implementation of FIR Filters for DSP Applications IEEE

27 Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique IEEE

28 A Novel Approach for parallel CRC generation FOR High Speed Application. IEEE

29 High speed Modified Booth Encoder multiplier for signed and unsigned numbers. IEEE

30 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation. IEEE

Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining
31 IEEE
concept using Verilog and FPGA
32 Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra IEEE

33 A Floating point Fused Dot Product Unit IEEE

34 Implementation of Power Efficient Vedic Multiplier using DBNS IEEE

35 LUT Optimization for Memory-Based Computation IEEE

Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR
36 IEEE
Algorithm
37 Measurement and evaluation of power analysis attacks on Asynchronous S-Box. IEEE

38 High Speed Booth Encoded Multiplier to Minimize the Computation time IEEE

39 Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation. IEEE

40 VLSI design Of a Digital Clock Using GALS Technique IEEE

41 Efficient Weighted Pattern Generation Technique with Low Hardware Overhead IEEE

42 SCA-FF and SCAh-FF design for single cycle access test IEEE

43 Design and implementation of a high performance multiplier using HDL IEEE

44 A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth Algorithm IEEE

45 Platform-Independent Customizable UART Soft-Core IEEE

A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by Using Spurious
46 IEEE
Power Suppression Technique
47 Using Self-Immunity Technique 64-bit Register File Immunity Improvement IEEE

48 A Novel Nanometric Parity Preserving Reversible Vedic Multiplier IEEE

High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based wavelet
49 IEEE
Transform

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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50 Pulse Triggered Flip-Flop Design for low power IEEE

Back End(Schematics & Layouts)

51 Design of Secure Differential Logic Gates for DPA Resistant Circuits for High-Secure Applications IEEE

52 Pulse Triggered Flip-Flop Design for low power IEEE

Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm
53 IEEE
technology
54 Statistical Analysis of MUX-Based Physical Unclonable Functions IEEE

55 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator IEEE

56 Realization of Basic Gates Using MUX in CMOS Design IEEE

57 Digitally Controlled Pulse Width Modulator for On-Chip Power Management IEEE
A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and
58 IEEE
Low Phase Noise Current Starved VCO
59 Area Efficient ROM-Embedded SRAM Cache IEEE

60 A Low Power MICS Band Phase - Locked Loop for High Resolution Retinal Prosthesis IEEE

VLSI (B.Tech.) 2014-2015

S.NO Projects Titles
1 High Speed FPGA implementation of FIR Filters for DSP Applications

2 Design and implementation of Floating Point Multiplier based on Vedic Multiplication

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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Technique

3 A Noval Approach for parallel CRC generation FOR High Speed Application.

4 High speed Modified Booth Encoder multiplier for signed and unsigned numbers.

Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
5
Implementation.

Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block
6
Chaining concept using Verilog and FPGA

7 Implementation of an Efficient Multiplier based on Vedic Mathematics

8 A Floating point Fused Dot Product Unit

9 Implementation of Power Efficient Vedic Multiplier

10 LUT Optimization for Memory-Based Computation

Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on
11
Fast FIR Algorithm

12 Measurement and evaluation of power analysis attacks on Asynchronous S-Box.

13 High Speed Booth Encoded Multiplier By Minimizing The Computation Time

14 Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation.

15 A Secure, Low Power and Low Hardware Digital Watermarking System.

16 Efficient Weighted Pattern Generation Technique with Low Hardware Overhead

Low Power Design Techniques Applied to Pipelined Parallel and Iterative CORDIC
17
Design

18 Design and implementation of a high performance multiplier using HDL

A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth

19
Algorithm

20 Platform-Independent Customizable UART Soft-Core

A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by Using

21
Spurious Power Suppression Technique

22 Using Self-Immunity Technique 64-bit Register File Immunity Improvement

23 FPGA Implementation of Low power Digital QPSK Modulator

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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High Speed 3D DWT VlSI Architecture for Image Processing Using Lifting Based wavelet
24
Transform

25 Implementation of AMBA compliant Memory Controller on a FPGA

26 Faster and Low Power Twin Precision Multiplier

27 Design and Analysis of Low Power Parallel Prefix VLSI Adder

28 FPGA Implementation of Booths and Baugh- Wooley Multiplier

29 Implementation of Area Efficient 16bit Adder in SPARTAN-3 FPGA

30 Reliable and Higher Throughput Anti-Collision Technique for RFID UHF Tag

31 Implementation of Bus Bridge between AHB and OCP

32 An Implementation of Open Core Protocol for the On-Chip Bus

33 Implementation of OFDM System using IFFT and FFT

34 An Efficient FPGA implementation of Double Precision floating Point Multiplier

35 FPGA Based High Speed Parallel Cyclic Redundancy Check

36 High speed carry save multiplier based linear convolution using Vedic mathematics

37 FPGA Implementation of 2-D DCT Architecture for JPEG Image Compression

38 Performance Evaluation of Complex Multiplier Using Advance Algorithm

39 Design of High Speed Vedic Square by using Vedic Multiplication Techniques

40 An FSM Based VGA Controller with 640480 Resolution.

41 A Verilog Model of Universal Scalable Binary Sequence Detector

42 Hardware modeling of binary coded decimal adder in field programmable gate array

43 Low powers add and shift multiplier design BZFAD architecture

44 A High Throughput Fixed point Complex divider for FPGAs

Design and Implementation of Two Variable Multiplier Using KCM and Vedic
45
Mathematics.

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com