At-Speed Test:

Improving Defect Detection for Nanometer

Designs

Jayant DSouza
Technical Marketing Engineer
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

2
At-Speed Test , SW DFT Symposium, May 2006
 Why At-Speed Test?
At-speed test detects the delays introduced by
resistive defects
This is necessary to
maintain DPM rates
in nanometer designs
At-speed test
is a must!
Fabless Forum March 2003

Nvidia saw a 20X increase in speed-related defects

moving from 180nm to 130nm.
G. Aldrich, B. Cory, Improving Test Quality and Reducing Escapes,
Proc. Fabless Forum, Fabless Semiconduct Assoc., 2003, pp.34-35.

3
At-Speed Test , SW DFT Symposium, May 2006
 Industrys Thoughts on At-Speed Test
Delay
Delaydefects
defectsare
areaacritical
criticalconsideration
considerationin
indesigning
designingtest
teststrategies
strategiesto
to
achieve
achieveoutgoing
outgoingquality
qualitygoals
goalsdelay
delaydefects
defectshave
havetypically
typicallyrepresented
represented
1%
1%toto5%
5%ofofthe
thetotal
totaldefect
defectpopulation
populationobserved.
observed.
Excerpts
Excerptstaken
takenfrom
fromIEEE
IEEEDesign
Design&&Test
TestofofComputers,
Computers,Sept-Oct
Sept-Oct2003
2003
Delay Defect Characteristics and Testing Strategies
Delay Defect Characteristics and Testing Strategies
A
Astudy
studywas
wasperformed
performedononmultiple
multipleASICs
ASICsto toquantify
quantifythe
theoccurrence
occurrenceof
of
frequency
frequencydependent
dependentdefects
defectswith
withthe
theyield
yieldloss
lossand
andcustomer
customerquality
quality
(DPM)
(DPM) reduction obtained by screening them. In each case,the
reduction obtained by screening them. In each case, the
reduction
reductionin
inDPM
DPMisissignificant
significant[33%-60%]
[33%-60%]
Excerpts
Excerptstaken
takenfrom
fromVTS
VTS2003
2003paper
paperentitled
entitled
Effectiveness
Effectiveness Comparisons of Outlier ScreeningMethods
Comparisons of Outlier Screening Methodsfor
forFrequency
Frequency
Dependent Defects on Complex ASICs
Dependent Defects on Complex ASICs
Each
Eachtest
testin
inthe
theMPC7410
MPC7410test testprogram
programuniquely
uniquelydetects
detectsaaset
setof
ofdefects
defects
that cannot be detected by any other tests in the test program
that cannot be detected by any other tests in the test program both both
DC
DCand
andACACscan
scantests,
tests,all
alldetect
detectunique
uniquesets
setsof
ofdefects.
defects.
Excerpts
Excerptstaken
takenfrom
fromITC
ITC2002
2002 conference
conferencepaper
paperentitled
entitled
Evaluating
Evaluating ATE Features in Terms of Test EscapeRates
ATE Features in Terms of Test Escape Ratesand
andOther
OtherCost
CostofofTest
TestCulprits
Culprits
4
At-Speed Test , SW DFT Symposium, May 2006
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

5
At-Speed Test , SW DFT Symposium, May 2006
 At-Speed ATPG
Scan
chains

10 10

Test Path

Goal = test path for a falling edge propagation from

1 to 0
ATPG will automagically determine appropriate values to
load scan chains and perform the test

6
At-Speed Test , SW DFT Symposium, May 2006
 At-Speed ATPG
How it Works

1
1
1 1
1 1

Define values for starting value and to sensitize path

7
At-Speed Test , SW DFT Symposium, May 2006
 At-Speed ATPG
How it Works

1
1 1
1 0
1
0
0

Define values to cause launch event

NOW - all values are known to load the scan chain

8
At-Speed Test , SW DFT Symposium, May 2006
 At-Speed ATPG
How it Works

11
1 10
1 0
0 10 1
0
0

Pulse clock in functional mode (SE=0) to launch

event
This causes the value change to start propagating through
the path

9
At-Speed Test , SW DFT Symposium, May 2006
 At-Speed ATPG
How it Works

10

10 0

Pulse clock in functional mode to capture value and

verify that transition propagated in time

10
At-Speed Test , SW DFT Symposium, May 2006
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

11
At-Speed Test , SW DFT Symposium, May 2006
 Path Delay and Transition Faults
Path Delay fault model
Tests combined delay through all gates of a path
Requires paths as input

Faulty path

Transition fault model

Tests for a gross delay potential at each gate terminal
Paths are automatically selected to test transition faults

Fault site

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At-Speed Test , SW DFT Symposium, May 2006
 Transition Fault Patterns

Transition fault patterns:

Capture
Launch
Launch-off shift
ATPG must switch scan enable at- CLK

speed (requires clock routing or

pipelining of SE) SE
SHIFT SHIFT SHIFT Capture
Applies combinational ATPG

Broadside or Launch-off capture

Capture

Launch
Scan enable timing is not critical
...
Applies clock sequential ATPG CLK

Activated when clock-sequential ...

SE
depth > = 2 SHIFT SHIFT SHIFT
Dead cycle

13
At-Speed Test , SW DFT Symposium, May 2006
 Transition Testing
Launch-off Shift vs. Broadside
Advantages Advantages
Combinational ATPG Fewer requirements on
Fewer patterns, faster
the scan control logic and
runtime
is usually easier
Shifting can be done at
any speed
Disadvantages Scan enable does not
have to be routed as a
Must disable scan enable clock or pipelined
quickly
Disadvantages
Scan enable must be
routed as a timing Sequential ATPG (2
critical clock system clock cycles)
More patterns, longer
Can create non-
runtime
functional patterns

Most customers use broadside transition patterns!

14
At-Speed Test , SW DFT Symposium, May 2006
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

15
At-Speed Test , SW DFT Symposium, May 2006
At-Speed Test Requires High Speed Clocks
Where do these clocks come from?

Automatic test equipment (ATE)

Requires high accuracy and tolerances
Usually only found on sophisticated
machines

Internal PLL or other clock

PLL
PLL generating circuitry
Control
Design Real functional clocks for testing
Core Allows use of less expensive ATE
ATPG must be able to produce desired
capture sequences from internal PLL

16
At-Speed Test , SW DFT Symposium, May 2006
 Improving At-Speed Test
Dealing with False Paths
False paths create unknown (X)
states; impacts test coverage False Path
U1 G1 G3
and compression D Q
G5 G6 U5
D Q
Effective at-speed test must Clk 1 CK
CK
consider false and multicycle U2
paths during pattern generation D Q

CK
Techniques that just mask the untested
observation point result in lower U3 G2
G4 G7 U6
D Q
coverage and compression D Q

CK CK

Auto identify false path:

Read
From U1/Q To U5/D
SDC Through G3/A
*Freescale: V. Vorisek et. Al, Improved Handling of False and Multicycle Paths in ATPG, VLSI Test
Symposium, 2006

17
At-Speed Test , SW DFT Symposium, May 2006
Improving the Quality of At-Speed Test
Test Case A B C D E
Gate Count 1.5M 3.7M 3.5M 3.8M 2.8M
#Timing Exceptions 4.1K 1.3K 1.8K 1.3K 10.1K
Test coverage
New - Old +4.02% +1.06% +2.94% +16.59% +5.13%
improvement [%]
Old 12.6 20.5 13.5 17.1 30.0
Patterns [K]
New 12.4 20.4 12.3 16.9 30.0
Old 0.34% 3.66% 1.25% 32.06% 3.02%
Xs per pattern
New 0.08% 1.68% 0.29% 0.58% 0.93%

Old method: cell constraint based masking

New method: analysis based on path sensitization

18
At-Speed Test , SW DFT Symposium, May 2006
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

19
At-Speed Test , SW DFT Symposium, May 2006
 Dont Over Test

Use broadside transition patterns instead of

launch-off-shift
Dont exercise non-functional paths
No fault test logic
Compression logic
BIST

Boundary scan

Specify false and multicycle paths

20
At-Speed Test , SW DFT Symposium, May 2006
 Multiple Clock Domains
What if design has 3+ clocks?
ATPG tools must handle this automatically
NOTE: most common practice is to test within each
clock domain and not between domains

21
At-Speed Test , SW DFT Symposium, May 2006
Multiple Clocks and Frequencies
F1

F2

F3
Capture domain
F1 F2 F3

Launch domain

F1

F2
F3
22
At-Speed Test , SW DFT Symposium, May 2006
 Per Pattern At-speed Control
PLL
CLOCK GATING
Gated Clocks
start_AC_test LOGIC
CONTROLLER
scan_in 0 0 1 1

Capture Sequence 3: Specify clock sequence

F1

F2

F3

23
At-Speed Test , SW DFT Symposium, May 2006
Combining Stuck-At and At-Speed Tests
100 98%

% Test Coverage
85%

First idea
Add TDF after SAF 50

TDF = Time Delay Fault

SAF TDF
SAF = Stuck-at Fault
0
0k 3k 6k 9k
Pattern Count
98%

% Test Coverage
100
91%
Better idea 85%

Do TDF first
50
Fault grade for SAF
coverage TDF SAF

Create top-up SAF

0
0k 3k 6k 9k
Pattern Count

24
At-Speed Test , SW DFT Symposium, May 2006
If Test Pattern Volume is Unacceptable

Dont truncate!
Remember the reason youre adding at-speed test is
to ensure quality
Use recommended flow with stuck-at generation
Run compression on test set
Important to get compression of both test data
volume and test time

25
At-Speed Test , SW DFT Symposium, May 2006
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

26
At-Speed Test , SW DFT Symposium, May 2006
 Memory Test
How do you effectively test memories at-speed

At-speed ATPG can test logic around the memories

At-speed memory testing is necessary

27
At-Speed Test , SW DFT Symposium, May 2006
 Memory Test

Testing typical memories

Industry-wide adoption of memory BIST
High quality memory BIST requires multiple
algorithms plus at-speed capabilities
Testing very small (or performance critical)
memories
Various approaches employed (not testing being one
of these)
Macro Testing offers an ideal, high-quality test
alternative to other approaches

28
At-Speed Test , SW DFT Symposium, May 2006
 Memory BIST & Macrotest
Complementary solutions for comprehensive memory testing

MBIST Macrotest
0 1
0 0
1 1
1 1
1 0
1 1
0 Logic 0 RAM 0 Logic 0
1 1 1 1
0 0 1 0
1 1

0010101
0101001
1011010
1011000
1011001
010011

Preferred choice for Use when area or

comprehensive Built-in Self- performance issues require
test of embedded SRAM or a non-intrusive approach
ROM

29
At-Speed Test , SW DFT Symposium, May 2006
 Agenda
At-Speed Test Motivation
At-Speed Logic Test
Defining At-Speed test
Path Delay & Transition Faults

At-Speed Patterns & Clocking

Issues & Solutions

At-Speed Memory Test

Memory BIST
Macro Testing

Conclusion

30
At-Speed Test , SW DFT Symposium, May 2006
 Conclusion
At-Speed test is necessary to ensure test
quality
At-Speed test must include logic and
memory test
False and multicycle paths must be handled
by ATPG

31
At-Speed Test , SW DFT Symposium, May 2006
 Mentor Supports At-Speed Test
Logic Test &
FastScan: Industry leading ATPG Compression
with advanced at-speed test
TestKompress: ATPG (including at-
speed) capabilities of FastScan, with
100X compression
Memory Test
MBISTArchitect: Memory built-in-
self-test with Full-SpeedTM operation
(up to 1Ghz)
MacroTest -- Scan-based testing for
small memories, including at-speed

32
At-Speed Test , SW DFT Symposium, May 2006
33
At-Speed Test , SW DFT Symposium, May 2006
 At-Speed ATPG Reference Information
K. Kim, S. Mitra, P. Ryan, Delay Defect Characteristics and Testing Strategies, IEEE Design
& Test of Computers, pp 8-16, Sept-Oct 2003.
G. Aldrich, B. Cory, Improving Test Quality and Reducing Escapes, Proc. Fabless Forum,
Fabless Semiconduct Assoc., 2003, pp.34-35.
J. Boyer, and R. Press, New Methods Test Small Memory Arrays, Proc. Test & Measurement
World, Reed Business Information, 2003, pp. 21-26.
R. Wilson, Delay-Fault Testing Mandatory, Author Claims, EE Design, 4 Dec 2002.
Tendolkar, N., Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage
for Motorolas Microprocessors Based on PowerPC Instruction Set Architecture, VTS, 2002.
J. Saxena et al., Scan-Based Transition Fault Testing: Implementation and Low Cost Test
Challenges, Proc. Intl Test Conf. (ITC 02), IEEE Press, 2002, pp. 1120-1129.
Tendolkar, N., At-Speed Testing of Delay Faults for Motorolas MPC7400, a PowerPC
Microprocessor, VTS, 2000.
Bailey, B. et al., Test Methodology for Motorolas High Performance e500 Core Based on
PowerPC Instruction Set Architecture, ITC, 2002.
Tendolkar, N., A Study of FastScan Transition Fault ATPG Capability for PowerPC
Microprocessors, Mentor Graphics User Group International Conf, 1998.
Butler, K. M., Estimating the Economic Benefits of DFT, IEEE Design and Test of
Computers, Jan-Mar 1999.
Motorola At-Speed Test White Paper - www.mentor.com/dft

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At-Speed Test , SW DFT Symposium, May 2006