VERY IMPORTANTNOTES

Out of various techniques to minimize the leakage and sub-threshold currents to minimize
static power dissipation one can use a variable threshold CMOS (VTCMOS) circuit, which is
easier to achieve and is further discussed here. The basic principle of a VTMOS circuit is to
keep the substrate separate from source and apply different voltage to it with respect to source
(See Figure-2).

Figure 2. A variable threshold CMOS inverter

Here the substrates of pMOS and nMOS transistors are separated out and have their own
voltage source, which is called substrate bias control circuit. The threshold voltage Vt of the
MOS device is a function of its source-to-substrate voltage Vsb. Normally the substrate of an
nMOS transistor is connected to GND and the substrate of pMOS transistor is connected to
VDD. This ensures the reverse bias condition of source and drain with respect to substrate.
There is a depletion region around source and drain which inhibits the conduction through
substrate. Only the leakage current can flow between source-substrate and drain-substrate.
However, if the depletion region between source-substrate and drain-substrate is increased,
the leakage current can be further minimized, which is the role of the VTCMOS circuit.

During active operation the voltage of nMOS substrate is kept at 0V (on GND at which the
source is also kept) and the voltage of pMOS substrate is kept at 2V (equal to source voltage).
When the circuit is in standby mode, as depicted in Figure 2, the substrate voltages are
changed through a substrate bias control circuit. It is 4V for pMOS and -2V for nMOS,
minimizing the static power dissipation by widening the depletion region and reducing the
leakage currents. A drawback of this method is that it requires an extra voltage source for
substrate biasing and substrate bias control circuitry that results in increasing the chip area.