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  • Part1 Fab Slides Ch01

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    Le Phuong Trinh
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    The document is a lecture on integrated circuit fabrication and design processes. It introduces microelectronic fabrication, covering historical trends like increasing wafer size and memory density. It describes the basic NMOS transistor and CMOS technology. Key fabrication steps like oxidation, photolithography, implantation, and diffusion are discussed. Bipolar junction transistors and the standard buried collector process are also introduced. The references and end of Chapter 1 are noted.

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    IC Fabrication & design precess

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    The document is a lecture on integrated circuit fabrication and design processes. It introduces microelectronic fabrication, covering historical trends like increasing wafer size and memory density. It describes the basic NMOS transistor and CMOS technology. Key fabrication steps like oxidation, photolithography, implantation, and diffusion are discussed. Bipolar junction transistors and the standard buried collector process are also introduced. The references and end of Chapter 1 are noted.

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    © All Rights Reserved
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    26 views8 pages

    Part1 Fab Slides Ch01

    Uploaded by

    Le Phuong Trinh
    The document is a lecture on integrated circuit fabrication and design processes. It introduces microelectronic fabrication, covering historical trends like increasing wafer size and memory density. It describes the basic NMOS transistor and CMOS technology. Key fabrication steps like oxidation, photolithography, implantation, and diffusion are discussed. Bipolar junction transistors and the standard buried collector process are also introduced. The references and end of Chapter 1 are noted.

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    of 8

    2/15/2017

    IC fabrication&design
    process (EE3113)
    Part 1: FAB
    HOANG Trang
    hoangtrang@hcmut.edu.vn
    Main reference:
    Jaeger R C Introduction to Microelectronic Fabrication (Pearson Higher
    Education, 2001) ISBN 0201444941
    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 1

    IC fabrication&design process (EE3113)


    Part 1: FAB

    Chapter 1:

    Overview

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 2

    1
    2/15/2017

    Motivation, Introduction
    Video:
    Microelectronic fabrication !!!???? WHY
    from sand to chip

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 3

    Historical Trends
    Silicon Wafer Size
    Early Wafers - 1, 1.5, 2
    Inch Diameters
    Wafer Size has
    Increased Steadily
    200 mm (8) Wafers in
    Production
    300 mm (12) (>
    3B$/Fab. Intel: 6B$)
    450 mm Planned and
    coming on line now

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 4

    2
    2/15/2017

    Larger Wafers
    Lower Die Cost

    Cost to Process a Wafer is


    Relatively Fixed for a Given
    Process
    Larger Wafer Lower
    Cost/Die
    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 5

    Historical Trends
    Memory Density (Bits/Chip)

    Moores Law - Exponential


    Increase in Chip
    Complexity

    ISSCC Research
    Benchmarks
    1967 - 64 bit Memory
    1984 - 1Mb Memory
    1995 - First 1 Gb
    Memory

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 6

    3
    2/15/2017

    Historical Trends
    Microprocessor Complexity (Trans./Chip)

    ISSCC Benchmarks
    1971 - 2000 Transistors
    1988 - 1M Transistors
    1998 - 100M Transistors

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 7

    Historical Trends
    Memory Feature Size (mm)
    Feature Size Decreases by
    2X approximately every 5
    years
    Each New Process
    Generation Doubles
    Density - Reduction of
    Feature Size by 0.707
    The Original
    Nanotechnology!
    Feature size now 22-28 nm
    Transistors Operate
    Normally to at Least 6 nm
    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 8

    4
    2/15/2017

    Semiconductor Industry
    Roadmap - ITRS

    Each new process generation doubles chip density by scaling feature size
    by 0.7.

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 9

    NMOS Transistor
    Top View and Cross-Section
    N-Channel Metal-Oxide
    Semiconductor
    Transistor
    Conducting Channel
    n- and p-type
    Region semiconductor regions
    Thick and thin oxides
    Etching Openings
    Polysilicon gate
    Metal (Al)
    Interconnections

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 10

    5
    2/15/2017

    Basic NMOS Process


    Key Steps

    Oxidation
    Photolithograph
    y
    Implantation
    Diffusion
    Etching
    Film Deposition

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 11

    CMOS Technology
    N-Well Technology Cross-Section
    Complementary Metal-
    Oxidation Oxide Semiconductor
    Technology
    Photolithography
    Dominant Technology
    Implantation in Integrated Circuits
    Today!
    Diffusion
    Requires both NMOS
    Etching and PMOS Transistors

    Film Deposition

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 12

    6
    2/15/2017

    Bipolar Transistor
    Top View and Cross-Section
    Bipolar Junction Transistor
    (BJT)
    Standard Buried Collector
    Process (SBC)
    Active n- and p-type
    Transistor semiconductor regions
    Region
    Thick and thin oxides
    Etching Openings
    Metal (Al) Interconnections

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 13

    SBC Process
    Key Steps

    Oxidation
    Photolithography
    Implantation
    Diffusion
    Etching
    Film Deposition

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 14

    7
    2/15/2017

    References

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 15

    End of Chapter 1-Part 1 (FAB)

    HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 16

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