Micro Processor design

Chapter 1

1.1MOSFET Transistors
A MOSFET is a sandwich of several layers of conducting and insulating materials. MOSFETs
are built on thin flat wafers of silicon of about 15 to 20 cm in diameter. The MOSFET sandwich
consists of a conducting layer called the gate on top of an insulting layer of silicon dioxide
(Si O 2) on the top of the silicon wafer called the substrate. The metal-oxide semiconductor

sandwich forms a capacitor in which a thin layer of insulating oxide called a dielectric separates
the metal and semiconductor plates. A MOSFET behaves as a voltage-controlled switch in which
the gate voltage creates an electric field that turns ON or OFF a connection between the source
and drain. The term field effect transistor comes from this principle of operation.

1.2Kinds Of MOSFET
There are two flavors of MOSFETS. They are the nMOS and the pMOS. The n-type transistors,
called nMOS, have regions of n-type dopants adjacent to the gate called the source and the drain
and are built on a p-type semiconductor substrate. The pMOS transistors are just the opposite,
consisting of p-type source and drain region in an n-type substrate. The figures below show an
nMOS and pMOS.

Source Gate Drain Source Gate Drain

n n p p
P substrate N substrate

Fig: nMOS and pMOS Transistors

Gate Gate

Source Drain Source Drain

Fig: Symbols for nMOs and pMOS Transistors

1.3MOSFET Transistors as Switch
MOSFET transistors work as voltage regulated switches. The voltage is given into the gate
terminal of a specific MOSFET transistor. According to the applied voltage the transistor state
remains either ON or OFF. Different states of two types of MOSFET transistor are given below:

Gate Voltage nMOS pMOS

Gate voltage, g=0 OFF ON
Gate voltage, g=1 ON OFF
Fig: Table of states of nMOS and pMOS transistors

1.4Transmission Gate:
nMOS transistors are good at passing 0 and pMOS transistors are good at passing 1, so the
parallel combination of the two passes both values well. This combination of both transistors is
known as transmission gate.

EN

EN

Fig: Transmission Gate

1.5Considered Parameters for Digital System

A digital system uses discrete valued variable. However, the variables are represented by
continuous physical quantities such as the voltage on a wire, the position of a gear, or the level of
fluid in a cylinder. Hence, the designer must choose a way to relate the continuous value to the
discrete value. To convert a physical quantity into discrete form many parameters such as supply
voltage, logic levels, noise margins, DC transfer characteristics are needed to be considered. All
these parameters help designer to design effective digital system.
1.5.1 Supply Voltage
For a digital system, the lowest voltage in the system is 0V, also called ground or GND. The
V DD
highest voltage in the system comes from the power supply and is usually called . In
V DD
1970s and 1980s technology, was generally 5V. As chips have progressed to smaller
V DD
transistors, has dropped to 3.3V, 2.5V, 1.8V, 1.5V, 1.2V or even lower to save power
and avoid overloading the transistors.

So, In digital system: The lowest supply voltage is 0V.

The highest supply voltage can be from 5V to 1.2V.

1.5.2 Logic Level

The mapping of a continuous variable onto a discrete binary variable is done by defining logic
levels. These logic levels are basically either 0 or 1. For defining logic levels a driver and a
receiver are used as shown below:

Driver Receiver

Fig: Logic levels

Here the first gate is called the driver and the second gate is called the receiver. The driver
V OL V OH V DD
produces a low output in the range of 0 to or a high output in the range of .
V IL
If the receiver gets an input in the range of 0 to , it will consider the input to be Low. If the
V OH V DD
receiver gets an input in the range of , it will consider the input to the High. If for
some reason such as faulty components, the receiver input should fall in the forbidden zone
V IL V IH V OH , V OL , V IH V IL
between the behavior of the gate is unpredictable. are called
the output and input high and low logic levels.

1.5.3 Noise Margins

If the output of the driver is to be correctly interpreted at the input of the receiver, we must chose
V OH > V IH V OH >V IH
. The noise margin is the amount of noise that could be added to a worst
case output such that the signal can still be interpreted as a valid input. Thus, the low and high
noise margins are :

NM L=V IL V OL NM H =V OH V IH

Logic high output Logic High input

Forbidden Zone NM H Forbidden Zone

NM L Logic low input

Logic low output

GND GND

Fig: Noise margin

1.5.4 DC Transfer Characteristics

The DC transfer characteristics of a gate describe the output voltage as a function of the input
voltage when the input is changed slowly enough that the output can keep up. They are called
transfer characteristics because they describe the relationship between input and output voltages.
 V DD
An ideal inverter would have an abrupt switching threshold at 2 ,V ( y )=V DD , for

V DD V
V ( A )= , V ( Y ) =0 . In such a case, V IH =V IL = DD . V OH =V DD V OL =0 . A real inverter
2 2

changes more gradually between the extremes. When the input voltage V (A) is 0, the output
voltage V ( y )=V DD and when V ( A )=V DD ,V ( y )=0 . However, the transition between these
V DD /2
endpoints is smooth and may not be centered at exactly . This raises the question of
how to define to logic levels. A reasonable place to choose the logic levels is where the slope of
dv ( y)
the transfer characteristic dv (a) is -1. These two points are called the unity gain points.

Choosing logic levels at the unity gain points usually maximizes the noise margins.

V DD
V(y) Unit gain points

V OH =V DD V OH
Slope=-1

V OL
V (A)

V DD
V OL=0 V DD /2 V DD
2 V (A)

Fig: DC transfer characteristics and unity gain

1.6Static Discipline
To avoid inputs falling into the forbidden zone, digital logic gats are designed to conform to the
static discipline. The static disciplines require that given logically valid inputs, every circuit
V DD
element will produce logically valid outputs. The choice of and logic levels is arbitrary,
but all gates that communicate must have compatible logic levels. Therefore, gates are grouped
into logic families such that all gates in a logic family obey the static discipline when used with
other gates in the family. The table below shows the value of voltages according to logic
families.

Logic Family V DD V IL V IH V OL V OH

TTL 5.0 0.80 2.00 0.40 2.40

CMOS 5.0 1.35 3.15 0.33 3.84
LVTTL 3.3 0.80 2.00 0.40 2.40
LVCMOS 3.3 0.90 1.80 0.36 2.70
Fig: Logic levels of 5V and 3.5V logic families

Receiver TTL CMOS LVTTL LVCMOS

Driver TTL OK NO: MAYBE MAYBE
V OH < V IH

CMOS OK OK MAYBE MAYBE

LVTTL OK NO: OK OK
V OH < V IH

LVCMOS OK NO: Ok OK
V OH < V IH

Fig: Compatibility of logic families

1.7Power Consumption
Power consumption is the amount of energy used per unit time. Power consumption is of great
importance in digital system. Digital systems draw both dynamic and static power. Dynamic
power is the power used to change capacitance as signals change between 0 and 1. Static power
is the power used even when signals do not change and he system is idle. The dynamic power
consumption follows the equation below:
 1
Pdynamic = C V 2DD f
2

Where C is the capacitance of the transistor or chip.

And f is the operating frequency of the system.

The power consumption follows the equation below:

Pstatic =I DD V DD

I DD is static current
Where

Thus, digital systems draw power both in active and inactive mode and it is defined by these two
equations above.