Flip flops

Prof. Jagannadha Naidu K

Outline
Sequencing
Sequencing Element Design
Latches
Flip-flops
Sequencing
Combinational logic
output depends on current inputs
Sequential logic
output depends on current and previous inputs
Requires separating previous, current, future
Called state or tokens
Ex: FSM, pipeline

clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

Sequencing Overhead
Use flip-flops to delay fast tokens so they
move through exactly one stage each cycle.
Inevitably adds some delay to the slow
tokens
Makes circuit slower than just the logic delay
Called sequencing overhead
Some people call this clocking overhead
But it applies to asynchronous circuits too
Inevitable side effect of maintaining sequence
Sequencing Elements

Latch: Level sensitive

a.k.a. transparent latch, D latch
Flip-flop: edge triggered
A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams clk
clk
clk
clk

Latch

Flop
Latch

Flop
D Q D Q
Transparent D Q D Q

Opaque clk
clk

Edge-trigger D
D

Q
Q (latch)
(latch)

Q
Q (flop)
(flop)
Latch Design
Pass Transistor Latch
Pros

+ Tiny
+ Low clock load
D Q
Cons
Vt drop Used in 1970s
nonrestoring
backdriving
output noise sensitivity
dynamic
diffusion input
Latch Design

Transmission gate
+ No Vt drop
D Q
- Requires inverted clock

Latch Design

Inverting buffer
X
+ Restoring D Q

+ No backdriving

+ Fixes either
D Q
Output noise sensitivity
Or diffusion input

Inverted output
Latch Design

Tristate feedback
+ Static D
X
Q
Backdriving risk

Static latches are now essential

because of leakage
Latch Design

Buffered input

+ Fixes diffusion input D

X
Q

+ Noninverting

Latch Design

Buffered output Q

X
+ No backdriving D

Widely used in standard cells

+ Very robust (most important)
- Rather large

- Rather slow (1.5 2 FO4 delays)

- High clock loading

Latch Design

Datapath latch Q

+ smaller D
X

+ faster

- unbuffered input

Flip-Flop Design

Flip-flop is built as pair of back-to-back

latches
X
D Q

X
D Q

Enable
Enable: ignore clock when en = 0
Mux: increase latch D-Q delay
Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
en

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

en

D 1
Flop

Q
0
Flop

Flop
D Q D Q
en
en
Reset
Force output low when reset asserted
Synchronous vs. asynchronous

Symbol

Latch

Flop
D Q D Q

reset reset
Synchronous Reset

Q Q

reset reset
Q
D D

Q
Q
Asynchronous Reset

reset
reset
D
D



reset
reset



Set / Reset

Set forces output high when enabled

Flip-flop with asynchronous set and reset


reset
set Q
D




set
reset


Sequencing Methods
Tc

Flip-flops

Flip-Flops
clk

Pulsed Latches
clk clk

Flop

Flop
Combinational Logic

2-Phase Transparent Latches

1
tnonoverlap tnonoverlap
Tc/2
2

1 2 1

Latch

Latch

Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches

p tpw

p p
Latch

Latch
Combinational Logic
Timing Diagrams
Contamination and
Propagation Delays
tpd Logic Prop. Delay
A tpd
Combinational
A Y
tcd Logic Cont. Delay Logic
Y tcd

tpcq Latch/Flop Clk->Q Prop. Delay

clk clk tsetup
thold
tccq Latch/Flop Clk->Q Cont. Delay

Flop
D Q D

Latch D->Q Prop. Delay tpcq

tpdq Q tccq

tcdq Latch D->Q Cont. Delay

clk tsetup thold
clk
tsetup Latch/Flop Setup Time Latch
tccq tpcq

D Q D tpdq
thold Latch/Flop Hold Time tcdq
Q
Max-Delay: Flip-Flops

t pd Tc tsetup t pcq
clk clk

Q1 D2

F1

F2
sequencing overhead Combinational Logic

Tc

tsetup
clk
tpcq

Q1 tpd

D2
Max Delay: Pulsed Latches

t pd Tc max t pdq , t pcq tsetup t pw p p

D1 Q1 D2 Q2

L1

L2
Combinational Logic
sequencing overhead
Tc

D1 tpdq

(a) tpw > tsetup

Q1 tpd

D2

tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2
Min-Delay: Flip-Flops
clk

tcd thold tccq Q1

F1
CL

clk

D2

F2
clk

Q1 tccq tcd

D2 thold
Min-Delay: Pulsed Latches

tcd thold tccq t pw Q1

L1
CL

p
Hold time increased
D2
by pulse width

L2
p
tpw
thold

Q1 tccq tcd

D2
Time Borrowing
In a flop-based system:
Data launches on one rising edge
Must setup before next rising edge
If it arrives late, system fails
If it arrives early, time is wasted
Flops have hard edges
In a latch-based system
Data can pass through latch while transparent
Long cycle of logic can borrow time into next
As long as each loop completes in one cycle
Time Borrowing Example
1

2
1 2 1
Latch

Latch

Latch
Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
1 2
Latch

Combinational Logic Latch Combinational

(b) Logic

Loops may borrow time internally but must complete within the cycle
How Much Borrowing?
1 2

D1 Q1 D2 Q2

L1

L2
Combinational Logic 1

2 tnonoverlap
Pulsed Latches Tc

tsetup
tborrow t pw tsetup Tc/2
Nominal Half-Cycle 1 Delay
tborrow

D2
Clock Skew

We have assumed zero clock skew

Clocks really have uncertainty in arrival time
Decreases maximum propagation delay
Increases minimum contamination delay
Decreases time borrowing
Skew: Flip-Flops
clk clk

t pd Tc t pcq tsetup tskew

Q1 D2

F1

F2
Combinational Logic

Tc

sequencing overhead
clk

tcd thold tccq tskew

tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1

F1
CL

clk

D2

F2
tskew

clk
thold

Q1 tccq

D2 tcd
Skew: Latches
2-Phase Latches 1 2 1

2t
D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
t pd Tc pdq
Logic 1 Logic 2

sequencing overhead 1

tcd 1 , tcd 2 thold tccq tnonoverlap tskew 2

tsetup tnonoverlap tskew

Tc
tborrow
2
Pulsed Latches
t pd Tc max t pdq , t pcq tsetup t pw tskew
sequencing overhead

tcd thold t pw tccq tskew

tborrow t pw tsetup tskew

Safe Flip-Flop
Past years used flip-flop with nonoverlapping clocks
Slow nonoverlap adds to setup time
But no hold times
In industry, use a better timing analyzer
Add buffers to slow signals if hold time is at risk

X
D Q

Summary

Flip-Flops:
Very easy to use, supported by all tools
Pulsed Latches:
Fast, some skew tol & borrow, hold time risk