Acknowledgements!

l Some materials from various sources!

n Dr.
Phil Nigh, IBM!
Fault models! n Principles of Testing Electronic Systems by
S. Mourad & Y. Zorian!
n Essentials of Electronic Testing by M.L.
Mani Soma! Bushnell and V.D. Agrawal!

Soma 1! Soma 2!

Defects, faults and errors! Faults and time duration!

l Physical defects! l Permanent: failure, fault or error always present
n fabrication defects (missing or extra materials)! and stable.!
l Faults! l Intermittent: fault or error only occasionally

n behavior due to defect or abstract model of present due to unstable hardware or varying
defect! hardware states.!
l Errors! l Transient: fault or error resulting from temporary

n incorrect operation! environmental conditions.!

n design errors, fabrication errors, faults! l Reliability: failure, fault or error not initially

n physical failures (including wear-out, etc.)!

present, but occurs during operation due to a
physical change in hardware.!
Soma 3! Soma 4!

Physical defect mechanisms! Fault types!

Vdd
l Abstract models of physical defects!
Missing
Contact l Structural faults!
l Functional faults!
Gate Input B
oxide
short
l Timing and delay faults!
Output l Permanent, intermittent, transient faults!
Input A
Metal
open
Open
polysilicon Metal
short
Soma 5! Soma 6!
GND
 Fault assumptions! Stuck-at fault examples!
l Single fault!
n fan-out issues: stem and branch faults! Z
RL
l Structural: ! B
n Interconnect faults! Z
A
A s-a-0 (A/0) or s-a-1 (A/1)! A R1
bridging fault (short): AND, OR! A Z
R2 B
open fault (break)! A Z
n Component (transistor) faults! (b)
(a)
Stuck-open (or stuck-off), stuck-short (or stuck-on)!
Soma 7! Soma 8!

Test vector! Detecting stuck-at faults!

l A test vector t is a specification that
includes both:! A

Z

n inputto be applied! B

n expected output!
n example: t = I/O (e.g. 0001/11)! Inputs Fault Free Faulty Responses at Z
AB Response A/0 B/0 Z/0 A/1 B/1 Z/1
l A test vector detects a fault if the output 00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
under fault is different than expected output! 10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1

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Example! Fault detection requirements!

X1 0 l fault: OR-bridge l Activation of the faults!
0 Z1
between X1 and X2! n apply appropriate inputs!
X2
1 l test: 011/01 detects l Propagationof the fault effect(s) to output
X3
Z2 this fault (Z1 -> 1)! (or observable point)!
1
1 l what if:! n concept of path sensitization !
n AND-bridge? detect at n controlling inputs of a logic block!
Z2!
l f
is detectable if there exists a test t that
n X2/0?!
n X3/0?!
detects f!
Soma 11! Soma 12!
 Fault detection example! Undetectable faults!
A 1 l Invalidation of single-fault assumption!
0
a 0 1 l Path re-convergence!
1
C
D 1 0/1
n negative re-convergence!
0 1
0
n positive re-convergence!
1 1
B
1/0
0/1 l Design with redundancies!
b 1/0
n unintentional:
needs to be optimized!
l b/0 detectable!
n intentional:
redundancy (e.g. triple-modular
l a/1 undetectable!
redundancy), hazard reduction!
l b/0 undetectable if a/1 exists!
Soma 13! Soma 14!

Hazard reduction vs. fault! Notes on fault detection!

l Remove or disable intentional design
redundancies while testing!
abc = 111

l Fault detection: NP-complete problem!
--> 011

l Polynomial algorithms exist for realistic
cases!

OUT = ab + bc + a c = ab + a c ==> Y/0 undetectable

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Single stuck-at fault (SSF) model! Notes on SSF detection!

l represents many physical faults! l Combinational fanout-free circuits: need
l independent of technology! to detect only SSFs at PIs.!
l detecting SSFs also detects many other l Combinational circuits with fanouts:
faults! detects SSFs at PIs and fanout
l reasonable test set size: ~ 2n faults for n-
branches.!
net circuits! l Core of most test generation tools.!

l can be used to model other faults! l Can be used for sequential circuits with
DFT (e.g. scan).!
Soma 17! Soma 18!
 Bridging faults! Detection!
l 2 or more lines shorted together! l Procedure:!
l Common occurrence with open faults! n set two signals to opposite values!
n propagate two fault effects!
l Deterministic: wired-OR, wired-AND!
n justify lines for both values!
l Indeterminate: bridge with impedance
(CMOS)! l Feedback fault: potential oscillation,
sequential problem!
l Feedback or non-feedback!
l IDDQ detection!
n feedback: rare occurrence!
l Determined by layout (NOT schematic)!
Soma 19! Soma 20!

IDD current waveform! IDD waveform with fault!

Input
Input
transitions
transitions
IDD of fault-
IDD of fault- free circuit
free circuit

l Monitor quiescent IDD (IDDQ) current! IDD of faulty

circuit
l Some defects generate high IDDQ current while
not creating any stuck-at effects!
High-Current state
Soma 21! Soma 22!

Test for bridging faults! Gate oxide shorts!

pinhole connection
gate & source node
l SSF tests detect a large number gate

(80%-90%) of bridging faults!

Vdd
l Dual-path propagation to generate tests!
l May need 2 or more tests to detect one
p+ p+
bridging fault! drain source

l IDDQ test generation and DFT! n-well

l conservative layout rules to reduce faults! p-substrate (GND)

Soma 23! Soma 24!

 Gate oxide shorts (2)! Gate oxide shorts (3)!
Vdd
Vdd l Predominant cause of reliability failures and
quality problems!
off off

pinhole A=1 l Degrades over time!

R n 1 M to 10 K to 10 !
Out=?
on l Maycause high IDD before affecting
Input B B=1
performance!
Output on

GND
GND
Soma 25! Soma 26!

Open faults! Resistive metal opens!

metal wire
l Common in ICs and systems (boards,
MCMs)!
Visually, this
l Modeling problem:! appears to be Thin film of conductive material
a typical open
n high-valueresistor may be inappropriate!
n other models: capacitor, controlled source!

l Introduces state into a circuit!

n CMOS inverter example! l longer delay!
l IDDQ test techniques! l detectable with SSF tests!

Soma 27! Soma 28!

Various open faults! MOS faults!

l Polysilicon opens! l Stuck-open (or stuck-off), stuck-short (or
n Before fan-out:! stuck-on)!
similar to metal opens! l G, D,S, B open; two-terminal short (6
detectable with SSF tests! faults)!
n After fan-out!
l Oxide defects and breakdown!
longer delays, higher IDD!
l Effects: sequential operation, changes in
l Contacts, source, drain!
timing, etc.!
n Longer delays, higher IDD!
l Possible detection by IDDQ!

Soma 29! Soma 30!

 Stuck-open example! Stuck-short example!
Vector 1: test for A s-a-0
(Initialization vector) Test vector for A s-a-0
Vector 2 (test for A s-a-1)
pMOS VDD pMOS VDD
Two-vector test
FETs FETs IDDQ path in
can be constructed by
faulty circuit
A ordering two s/a tests A Stuck-
1 0 1
Stuck-
short
open
0 0
B 0
B Good circuit state
C 0 1(Z)
C 0 (X)

Good circuit states

nMOS nMOS
FETs Faulty circuit states FETs Faulty circuit state

Soma 31! Soma 32!

Sequential circuits and faults! Faults in a latch!

l More complex behavior due to feedback! R

1

l Test sequence (instead of a single vector) A
Q

required.!
S
2

l A test sequence T detects a fault f iff for
every pair of initial states q and qf, the
output sequences are different for some Inputs
Fault-free
Faulty Response Qn

SR
Qn
A/0
S/0
R/0
A/1
S/1
R/1

sub-vector in T! 01
0
0
0
Qn-1 0
0
0

00
Qn-1
1
Qn-1 Qn-1 0
1
0

10
1
1
Qn-1 1
0
1
0

Soma 33! 11
0
0
0
1
0
0
0
34!
Soma

Sequential circuit example! Sequential fault detection!

l State table (next l Output sequence
state,out)!
with input T=10111!
X=0 X=1 l State transition:

A A,0 D,0 ADADBC!

Initial Fault-free a/1 b/0
state
B C,1 C,1
A 01011 01010 01101
C B,1 A,0 B 11100 11100 11101
C 00011 00010 01010
D A,1 B,1 D 11001 10010 11010

Soma 35! Soma 36!

 Test sequences! Fault equivalence!
l Initialization sequence! l Equivalence: same outputs under two
n toget the circuit to a known state! faults!
n design guideline: Master-Reset to all FFs! l No test can distinguish 2 equivalent
n note: fault detection on the Reset line! faults!
l Homing sequence: to get to the state where l Fault equivalence classes: disjoint and
fault is manifested! cover entire fault set (Set Theory
l Propagation sequence: to get the fault results)!
effect to the output or observable point!
Soma 37! Soma 38!

Fault dominance and collapsing! Fault collapsing example!

l Fault dominance! l Test set reduction !
n f1dominates f2 if the test set T2 for f2 is a n good for test cost reduction!
subset of the test set T1 for f1! a/0 ~ b/0, d/0 ~ h/0, g/1 ~ f/1, e/1 ~ i/1!
24 faults -> 10 faults!
n Any test detecting f2 also detects f1!
n bad for fault diagnosis!
n Sufficient to generate tests for f2 only!
a f
l Fault collapsing to reduce fault list size! b
j

g
n Use equivalence relations! c m
h
n Use dominance relations! i
d k
e
Soma 39! Soma 40!

Multiple Stuck-at fault model! Other fault models!

l eachline has 3 states: good, s/0, s/1.! l Functional faults!
l number of faults: 3n - 1.! n based on functions and specifications!
l assume only k faults at a time:! l Timing and delay faults!
n i faults at a time -> number of faults is2i! n gate delay faults, path delay faults!
Usually two-pattern tests!
n number of possible combinations of i lines in
! n$ critical path: static and dynamic!
an n-line circuit is ! #" i &%
n i can vary from 1 to k! n veryimportant in high-speed circuits!
k! n some techniques rely on SSF model!
n number of MSF = ! ! i!
Si=1!! ni!! 2! n see papers in IEEE Trans. CAD, ITC!
Soma 41! Soma 42!
 Other fault models (2)! Transition Fault Model!
l Transient faults! A
n Power supply, radiation! OUT
l Metastability! B

n Latch or FF switches only halfway! Six transition faults

l Intermittent faults! 1. A slow-to-rise
n Pattern-sensitivity
(e.g. in RAM)! 2. A slow-to-fall
n Crosstalk, ground bounce, etc.! 3. B slow-to-rise
n Possible thermal causes! 4. B slow-to-fall

l Design needs to stay within margins! 5. OUT slow-to-rise

6. OUT slow-to-fall
Soma 43! Soma 44!

Defect-fault correspondence! Defect level vs. Fault coverage!

Defect type" Behavior" 30
Net-to-net short" Logical fault & high IDD"
Net-to-net power supply short" Stuck fault & IDD"
25
Power supply-power supply short" Gross logical failure & IDD" 20
Opens causing a global net open" Stuck fault (IDD?)" Theoretical
Opens causing a single floating gate" Delay fault & IDD"
15
Open source/drain node" Logical fault or very long delay fault 10 Experimental
(IDD?)"
Resistive source/drain contact" Delay or logical fault" 5
Source-to-drain shorts" Delay or logical fault & IDD" 0
Gate-oxide shorts" Delay or logical fault & IDD"
0 10 20 30 40 50 60 70 80 90 100
P-n junction leakage" Delay or logical fault & IDD"
Fault Coverage, %
Blocked implant" Delay or logical fault" Soma 45! Soma 46!

Fault coverage comparison! Defect vs. Coverage vs. Yield!

Hardware measurements (Sematech project)
Test Coverage
Defect Level
100%
% DPM Y=50% Y=90%
1 10000
5000

0.1 1000
500
50% Stuck-fault
coverage 0.01 100
IDDq coverage 50

0.001 10
Number of
test 99.99 99.9 99 90
Fault coverage, %
vectors

4 16 32 128 512 Soma 47! Soma 48!

 Conclusion!
l Fault models and effects for digital systems!
l Test vectors and detection methods!
l New issues: deep-submicron technologies,
high operating frequencies, power supply
reduction, increasing noise!
l Faults in mixed analog-digital systems!

Soma 49!