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Basic debug functionality includes processor halt, single-step, processor core register access,
Reset and HardFault Vector Catch, unlimited software breakpoints, and full system memory
access. See the ARMv6-M Architecture Reference Manual.
The processor implementation can be partitioned to place the debug components in a separate
power domain from the processor core and NVIC.
When debug is implemented, ARM recommends that a debugger identifies and connects to the
debug components using the CoreSight debug infrastructure.
To discover the components in the CoreSight debug infrastructure, ARM recommends that a
debugger follows the flow shown in Figure 7-1. In this example, a debugger reads the peripheral
and component ID registers for each CoreSight component in the CoreSight system.
Pointers
Optional component
To identify the Cortex-M0+ processor within the CoreSight system, ARM recommends that a
debugger:
1. Locates and identifies the Cortex-M0+ ROM table using its CoreSight identification. See
Cortex-M0+ ROM table identification values on page 7-3.
ARM DDI 0484C Copyright 2012 ARM. All rights reserved. 7-2
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