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INDEX
Sr. Page
Name Of Experiment DOS Sign
No. No.
2 Instrumentation Amplifier 5
7 2:1 multiplexer 21
VESIT-EXTC-ADIC-D9 Page 1
EXPERIMENT NO - 1 DATE :
1] Non-Inverting Amplifier-
VESIT-EXTC-ADIC-D9 Page 2
Theory:- The utility of an op-amp can be greatly increased by providing
negative feedback. The output in this case is not driven into saturation &
circuit behaves in a linear manner.
180
0
1
0
0
VESIT-EXTC-ADIC-D9 Page 3
Design:-
Result:-
VESIT-EXTC-ADIC-D9 Page 4
EXPERIMENT NO - 2 DATE :
Circuit Diagram:-
VESIT-EXTC-ADIC-D9 Page 5
to change two resistance values & still maintain equal ratios between / &
/ .
Optimally we would like to be able to change the gain by changing only a
single resistance value, the circuit called an Instrumentation Amplifier that
allows this flexibility. In this circuit two non-inverting amplifiers, and are
used as input stage, & a difference amplifier as second stage.
The voltages at the inverting terminals of the voltage followers are equal
to the input voltages. The current in resistor is then
The current in resistor is also , and output voltages of op-amp
and are respectively ,
1
And
1
Since the input signal voltages are applied directly to the non-inverting
terminals of and input impedance is very large, ideally infinite, which
is one desirable characteristic of instrumentation amplifier. Also, the
differential gain is a function of resistor , which can easily be varied by using
potentiometer, thus providing a variable amplifier gain with adjustment of only
one resistance.
VESIT-EXTC-ADIC-D9 Page 6
Design:-
Result:-
Sr.
"
No.
#$% &'%
1 0 012
100()) & 1*+, -%..
#$% &'%
2 0 012
100()) & 1*+, -%..
VESIT-EXTC-ADIC-D9 Page 7
EXPERIMENT NO - 3 DATE :
Circuit Diagram:-
VESIT-EXTC-ADIC-D9 Page 8
for long time because of supply voltage & temperature variations. So a value
greater than unity is chosen. This also gives an output waveform virtually
discontinuous at the comparison voltage, which leads to hysteresis or backlash.
Figure shows such a regenerative comparator also known as Schmitt Trigger.
The input voltage is applied to inverting ( - ) input terminal & feed-back voltage
to non-inverting (+) input terminal. The input voltage triggers the output
every time it exceeds certain voltage level. These voltage levels are called
upper threshold voltage 789 & lower threshold voltage
89 . The
hysteresis width is the difference between these two threshold voltages i.e.
789
89 . These voltages are calculated as follows
Suppose the output :;< . Therefore voltage at (+) terminal can be
given by using superposition
=> :;<
789 ? ? ? 1
Suppose the output :;< . Therefore voltage at (+) terminal can be
given by using superposition
=> :;<
89 ? ? ? 2
VESIT-EXTC-ADIC-D9 Page 9
If an input sinusoid of frequency - 1/D is applied to such a comparator, the
symmetrical square wave is obtained at the output.
Design:-
Given |789 | |
89 | 1.5, |:;< | 15, => 0
Assume 1*
Select input signal frequency 300Hz to 600Hz and amplitude must be such that
it crosses 789 &
89 .
Result:-
Observed values of
789
89
:;<
:;<
Conclusion:-
Schmitt Trigger is a comparator with positive feedback. A Schmitt trigger
converts slowly varying waveforms into square wave. In Schmitt trigger, the
input voltage triggers the output every time it exceeds certain voltage levels
called upper threshold & lower threshold voltages.
VESIT-EXTC-ADIC-D9 Page 10
EXPERIMENT NO - 4 DATE :
Aim:- Design & implement R-2R ladder Digital to Analog converter using
op-amp IC741.
VESIT-EXTC-ADIC-D9 Page 11
A D/A converter in its simplest form use an op-amp & either binary-
weighted resistor or R & 2R resistor as shown in figure. Wide range of resistor
is required in binary-weighted type DAC. This can be avoided by using R-2R
ladder DAC where only two values of resistors are required. It is well suited for
integrated circuit realization. The typical values or R ranges from 2.5K to
10K.
Consider a 3-bit DAC as shown in figure, where 2 FGH, 2 , 2 JGH
corresponds to binary inputs. Therefore voltage at point c can easily be
calculated for different binary input conditions. Since resistive network is
linear circuit, therefore for analysis purpose, we can select only four digital
data inputs i.e. 000, 100, 010, 001. Output voltage for other input conditions
can be calculated by using superposition theorem as shown in figure.
The output voltage equation can written in different ways as,
=>: K%L('M %.N'M%$O P- $)NO Q$'RS K'O' T2 , 2 , 2 U
2 2 2
=>
2 4 8
VESIT-EXTC-ADIC-D9 Page 12
Design:-
Observation Table:-
DIGITAL
INPUTES Decimal Output
Equivalent Voltage
2 2 2
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
Conclusion:- R-2R ladder type DAC requires only two values of resistors. DAC
using discrete components is not suitable for higher resolution e.g. 8-bit DAC
etc.
VESIT-EXTC-ADIC-D9 Page 13
EXPERIMENT NO - 5 DATE :
Circuit Diagram:-
VESIT-EXTC-ADIC-D9 Page 14
Theory:-
The 555 timer is a highly stable device for generating accurate time delay or
oscillation. The 555 timer can be used with supply voltage in the range of +5V
to +18V & can drive load upto 200mA. Three 5K internal resistors act as
voltage divider, providing bias voltage of (2/3) Vcc to upper comparator & (1/3)
Vcc to lower comparator. It is possible to vary time, by applying a modulation
voltage to the control voltage input terminal (pin 5), when not in use, it is
recommended by manufacturers that a capacitor (0.01F) be connected
between control voltage terminal & ground to by-pass noise or ripple from
supply.
The reset input (pin 4) provides a mechanism to reset the flip-flop in a manner
which overrides the effect of any instruction coming from flip-flop. This
overriding reset is effective when the reset input is less than about 0.4V. When
not in use it is connected to Vcc.
Circuit diagram shows IC555 connected in astable mode. When power supply is
connected, the external timing capacitor C charges towards Vcc with a time
constant ^ _ W. During this time pin3 is high(Vcc).
When capacitor voltage equals (slightly greater than) 2/3LL the upper
comparator triggers the flip-flop so that `a 1. This in turn makes transistor
` on and capacitor C starts discharging towards ground through _ and `
with a time constant _ W current also flows into transistor ` through ^ .
Resistor ^ & _ must be large enough to limit this current & prevent damage
of ` .
During discharge as voltage across reaches to (slightly less than) 1/3LL, the
lower comparator is triggered which turns `a 0 & voltage across capacitor C
VESIT-EXTC-ADIC-D9 Page 15
clamps to 1/3LL. The capacitor C is thus charged & discharged between
2/3LL and 1/3LL.
O 0.693^ _ W
O 0.693_ W
1 1.45
- +,
D ^ 2_ W
Duty cycle can be given as
O ^ _
2% i 100.
D ^ 2_
VESIT-EXTC-ADIC-D9 Page 16
Design:-
Result:-
a) Frequency of square waveform =
b) Peak value of output voltage =
c) Duty-cycle of square waveform =
d) Minimum & maximum voltage across W
Conclusion:- IC555 timer can produce very accurate & stable time delays, from
microseconds to hours.
VESIT-EXTC-ADIC-D9 Page 17
EXPERIMENT NO - 6 DATE :
Aim:- Design & implement second order low pass active filter circuit using
PSpice software
Schematic:-
Theory:-
A frequency selective electric circuit that passes electric signals of specified
band of frequencies & attenuates the signals of frequencies outside the band
is called an electric filter. In active filters along with passive components
active component like op-amp is used.
Active filters are typically specified by the voltage transfer function,
#
+#
#
VESIT-EXTC-ADIC-D9 Page 18
under steady condition +jk |+jk|% lmn
dt
&s%R% 1 V pass band gain of the filter
du
Design Steps:-
Expect having twice roll-off rate in the stop band, the frequency response of
the second-order low-pass filter is identical to that of first-order type.
1] Choose a value for high cutoff frequency
2] To simplify design calculation set and W W W.
3] Assuming C (e.g. v 1wx) Calculate the value of R.
4] For Butterworth response damping constant of second-order system must
be 0.707.
Select 0.586 . assume v 100y.
VESIT-EXTC-ADIC-D9 Page 19
Design:-
Result:-
Cutoff Frequency = Hz Roll-off = dB/dec
Conclusion:- The roll-off rate increases with order of filter. In active filters gain
greater than unity is possible.
VESIT-EXTC-ADIC-D9 Page 20
Experiment No-7 Date:
Aim:- Write a VHDL entity to describe a 2:1 multiplexer, synthesize a circuit from the code &
verify its functional correctness.
VHDL Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2 is
Port ( a,b,s : in STD_LOGIC;
f : out STD_LOGIC);
end;
begin
end;
RTL Schematic
VESIT-EXTC-ADIC-D9 Page 21
Technology Schematic
LUT3_E4
Simulation Result
Experiment No-8 Date:
Aim:- Write a VHDL entity to describe a 4:1 multiplexer using conditional signal assignment,
synthesize a circuit from the code & verify its functional correctness.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
Port ( a, b, c, d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR(1 downto 0);
f : out STD_LOGIC);
end ;
begin
f <= a when s = "00" else
b when s = "01" else
c when s = "10" else
d;
end;
RTL Schematic
VESIT-EXTC-ADIC-D9 Page 23
Technology Schematic
Simulation Result
Experiment No-9 Date:
Aim:- Write a VHDL entity to describe a 2:1 multiplexer ( 4-bit bus input ) using conditional
signal assignment, synthesize a circuit from the code & verify its functional correctness.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2_bus is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
f : out STD_LOGIC_VECTOR (3 downto 0));
end;
begin
end;
RTL Schematic
VESIT-EXTC-ADIC-D9 Page 25
Technology Schematic
Simulation Result
VESIT-EXTC-ADIC-D9 Page 26
Experiment No-10 Date:
Aim:- Write a VHDL entity to describe a 4:1 multiplexer ( 4-bit bus input ) using hierarchical
approach, synthesize a circuit from the code & verify its functional correctness.
Use 2:1 mux designed in previous example (mux2_bus) as a component.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_bus is
Port ( d0, d1, d2, d3 : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end mux4_bus;
begin
lowmux : mux2_bus port map (d0, d1, s(0), low);
highmux : mux2_bus port map (d2, d3, s(0), high);
finalmux : mux2_bus port map (low, high, s(1), y);
end hierarchy;
RTL Schematic
VESIT-EXTC-ADIC-D9 Page 27
Simulation Result
VESIT-EXTC-ADIC-D9 Page 28
Technology Schematic
VESIT-EXTC-ADIC-D9 Page 29
Another way of describing mux4:1 without using hierarchy technique. Only change in RTL
schematic no change in technology schematic.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_bus is
Port ( d0, d1, d2, d3 : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end mux4_bus;
RTL Schematic
VESIT-EXTC-ADIC-D9 Page 30
Experiment No-11 Date:
Aim:- Write a VHDL entity to perform 4-bit addition using ripple carry adder & verify its
functional correctness.
VHDl Code
-- hafadder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hafadder is
Port ( a,b : in STD_LOGIC;
y,c : out STD_LOGIC);
end hafadder;
begin
y <= a xor b;
c <= a and b;
end str;
-- fulladder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( x,y,cin : in STD_LOGIC;
f,cout : out STD_LOGIC);
end fulladder;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_bit_adder is
Port ( P, Q : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (4 downto 0) );
end four_bit_adder;
begin
H1: hafadder port map(P(0),Q(0),Y(0),c1);
F1: fulladder port map(P(1),Q(1),c1,Y(1),c2);
F2: fulladder port map(P(2),Q(2),c2,Y(2),c3);
F3: fulladder port map(P(3),Q(3),c3,Y(3),Y(4));
end hierarchy;
Simulation Result
VESIT-EXTC-ADIC-D9 Page 32
Experiment No-12 Date:
Aim :- Write & simulate VHDL code for 1011 sequence detector.
State Diagram:-
VHDL Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity example is
Port ( clk, rst : in STD_LOGIC;
A : in STD_LOGIC;
f : out STD_LOGIC);
end example;
-- output logic
f<='1' when state = s5 else '0';
end Behavioral;
Simulation Result
Experiment No-13 Date:
Aim:- Write & simulate VHDL code for 111 sequence detector
State Diagram:-
VHDL Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity asd is
Port ( clk,rst : in STD_LOGIC;
A : in STD_LOGIC;
f : out STD_LOGIC);
end asd;
VESIT-EXTC-ADIC-D9 Page 35
--next state logic
process (state,A)
begin
case state is
when s1=> if A='1' then nextstate <= s2;
elsif A='0' then nextstate <= s1;end if;
when s2=> if A='1' then nextstate <= s3;
elsif A='0' then nextstate <= s1;end if;
when s3=> if A='1' then nextstate <= s4;
elsif A='0' then nextstate <= s1;end if;
when s4=> if A='1' then nextstate <= s4;
elsif A='0' then nextstate <= s1;end if;
when others => nextstate <= s1;
end case;
end process;
-- output logic
f<='1' when state = s4 else '0';
'0'
end Behavioral;
Simulation Result
Experiment No-14 Date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
Simulation Result
Experiment No-15 Date:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ring_counter is
Port ( clk,clr,load : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0));
end ring_counter;
end Behavioral;
Simulation Result
library
library <LIB_NAME>;
use <LIB_NAME>.<PACKAGE_NAME>.all
use IEEE.math_complex.all;
use IEEE.math_real.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_unsigned.all;
Commonly used
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Operators
Arithmetic
--The following are the arithmetic operators as defined by the VHDL language.
+ ---- Addition
- ---- Subtraction
* ---- Multiplication
/ ---- Divide
mod ---- Modulus
** ---- Power Operator (i.e. 2**8 returns 256)
Bitwise
--The following operators can be used on two single bits to produce a single bit
--output or two equivelent sized bused signals where the operations are performed
--on each bit of the bus. In the case of the Invert, only one signal or bus is
--provided and the operation occurs on each bit of the signal.
Operator end
Ports
Input
<port_name> : in std_logic_vector(15 downto 0);
<port_name> : in std_logic;
Output
<port_name> : out std_logic_vector(3 downto 0);
<port_name> : out std_logic;
Bidirectional
<port_name> : inout std_logic_vector(7 downto 0);
<port_name> : inout std_logic;
Predefined types
STD_LOGIC --'U','X','0','1','Z','W','L','H','-'
STD_LOGIC_VECTOR --Natural Range of STD_LOGIC
BOOLEAN --True or False
INTEGER --32 or 64 bits
NATURAL --Integers >= 0
POSITIVE --Integers > 0
REAL --Floating-point
BIT --'0','1'
BIT_VECTOR(Natural) --Array of bits
CHARACTER --7-bit ASCII
STRING(POSITIVE) --Array of characters
TIME --hr, min, sec, ms, us, ns, ps, fs
DELAY_LENGTH --Time >= 0
VESIT-EXTC-ADIC-D9 Page 40
Finite State-machines (FSM)
There are several methods to code state-machines however following certain coding
styles ensures the synthesis tool FSM (Finite State-Machine) extraction algorithms properly
identify and optimize the state-machine as well as possibly improving the simulation, timing
and debug of the circuit.
The following examples are broken down into Mealy implementations.
The basic trade-offs for each implementation is explained below.
The general recommendation for the choice of state-machine depends on the target
architecture and specifics of the state-machine size and behavior however typically, Moore
style state-machines implement better for FPGAs and Mealy implement best for CPLDs.