Innovation of

Switched-Capacitor
Voltage Multiplier
Part 1: A brief history

Toru Tanzawa

T
he switched-capacitor (SC) voltage
multiplier is becoming one of the most
critical IC blocks for energy harvesting
in wireless sensor nodes to generate a
voltage high enough for microwatt sens-
energy sources such as mechanical vibration, electro-
magnetic wave, and temperature gradient. However, its
origin was a 10 m-scale particle accelerator generating
1 MV back to 1920s. There have been several innova-
tive design techniques to realize integrated SC voltage
image licensed by graphic stock

ing and computing ICs in a nanometer complementary
metaloxidesemiconductor (CMOS) from environmental
multipliers since the original one. This article overviews
such innovations for the last century and describes how
10 m-scale SC voltage multipliers have been integrated
in microwatt ICs and what technical considerations
are critical for area- and power-efficient design. It also
summarizes how device parameters determine circuit

Digital Object Identifier 10.1109/MSSC.2015.2495678

Date of publication: 21 January 2016

1943-0582/162016IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 16 51
 Table 1. THE power converter Category. and the SC converter, as shown in
Table 1. The switching converter
dcdc/acdc
is composed of one or more induc-
Switching converter SC tors, one or more capacitors, and
Voltage gain Inductor Capacitor several switching devices. The SC
(VOUT /VIN) Capacitor Switching device convertor is composed of one to
Switching device
many capacitors and one to many
>1 Boost converter Voltage multiplier or charge pump switching devices. The differences
<1 Buck converter Fractional regulator are 1) with or without inductors
and 2) single or many stages. Pres-
ently, the degree of integration is
Table 2. A brief history of the SC voltage multiplier. all components except for inductor
Year Author(s) Topology Experimental Reference for switching converter whereas all
or theoretical components for SC. This is because
1914 Greinacher Doubler Experimental [1] Phys. Zeit. the inductance of an integrated
1923 Marx Parallel to Experimental [2] German patent inductor is much smaller than the
serial value required for generating a high
voltage when the silicon area is lim-
1932 Cockcroft Ladder Experimental [3] Proc. Royal.
Walton Soc. ited. This concentrates on SC volt-
age multipliers or charge pumps.
1958 Kilby Invention of IC [4] U.S. Patent
Table 2 summarizes representa-
1971 Brugler Serialparallel Theoretical [5] JSSC tive two-phase clock SC voltage mul-
1973 Falkner Parallel Theoretical [6] Elec. Lett. tipliers. Grenacher is known as an
1976 Dickson Parallel Experimental [7] JSSC inventor of the so-called SC voltage
1991 Ueno et al. Fibonacci Experimental [8] ISCAS doubler in 1914 [1]. Marx developed
a pulse power generator for the R&D
1995 Cernea 2N Theoretical [9] U.S. Patent
of lightning in 1923 [2]. Cockcroft
and Walton built a voltage multi-
plier for a particle accelerator with
V1 = VIN a dc voltage gain greater than two
0V in 1932 [3]. After Kilby invented the
D2
C IC in 1958 [4], Brugler [5], Falkner
[6], and Dickson [7] have realized
Phase 1 the integration of SC voltage multi-
D1
VIN VOUT plier in ICs. Another direction was
2Q how the number of discrete capaci-
C
V1 = 2VIN tors and switching devices could be
Phase 2 VIN reduced for small form factor and
D2
Q low cost for high power applications.
VIN VOUT_MAX = 2VIN
Other types of circuit topology that
have been developed by Ueno et al.
D1 VOUT
0V [8] and Cernea [9] are also described
in this article.
Figure 1:An SC voltage doubler [1].
Greinacher SC Voltage
performance such as output volt- Part 1, detailing the history of the Doubler (1914) Figure 1
age current and power efficiency. SC voltage multiplier To generate 200-V dc from 110-V
There have been also several design Part 2, fundamentals of charge ac for an ionometer for measuring
innovations in switching circuits pump the intensity of ionizing radiation
to enable to work at extremely low Part 3, state-of-the-art switching in 1914, Greinacher built a voltage
voltages. This article shows state circuits and applications. doubler, using an ac power source,
of the art for switching circuits for one capacitor, and two diodes, as
both dc-dc and ac-dc voltage multi- A Brief History of shown in Figure 1 [1]. There are two
pliers and their applications as well. the SC Voltage Multiplier phases: charging the capacitor from
There will be three parts to this Voltage converters are categorized the power source in phase 1 and dis-
article series: into two groups, the switching converter charging the capacitor to the output

52 W I N T E R 2 0 16 IEEE SOLID-STATE CIRCUITS MAGAZINE

 Precharge Phase Discharge Phase
VOUT = 0 V VOUT_PEAK = (N + 1) VIN

R R
G G
VOUT

R R VOUT_PEAK ~ (N + 1) VIN
R RL R RL
G G

R R R R
G G TR TF

R R R Time
G R
G
(c)
+ +
VIN VIN

(a) (b)

Figure 2:A Marx generator [2].

terminal in phase 2. Thus, a maxi-
mum voltage gain of two was real-
ized. This simple and effective way
to generate a higher voltage became
the basis of the following innovation.
Marx Generator (1923) Figure 2
The Marx generator is composed
of N capacitors (Cs) connected in
parallel to the power supply VIN
and ground via resistors (Rs) and in
series to each other via spark gaps
(Gs) as shown in Figure 2 [2]. Ini-
tially, as shown in Figure 2(a), all the
capacitors are precharged to VIN .
When the first spark gap gets short,
the second and the following spark
gaps get short one after another.
As a result, all the capacitors are
connected in series to the load, as
shown in Figure 2(b). Because R is
made much larger than a load R L,
the output voltage VOUT can reach
the maximum of (N + 1) VIN in a
short time of period. After that, the
state gradually returns to its original
in a long period due to large R , as
shown in Figure 2(c). This technique
was originally aimed at research-
ing lightning, but it has been also
applied to generating pulsed X-ray
for photolithography or feed grain
preservation and medical care such
as eye surgery [10], [11].
CockcroftWalton (CW)
Ladder (1932) Figure 3
Cockcroft and Walton needed to
have a dc voltage gain greater than
two for a particle accelerator with an
output of up to 1 MV [3]. They used
ac power, N-capacitors, and (N + 1)
diodes. Figure 3(a) depicts a 2.5-MV
generator [12]. Later, the multiplier
had been also applied for industrial
applications such as X-ray medical
equipment and an electron gun for
a cathode-ray tube [13].
Figure 3(b) shows how the CW
multiplier works in steady state
using an example of five stages.
One arrow represents an amount
of charges Q , which is output per
cycle. In steady state, each diode
transfers one Q . In phases 1 and 2,
the input power needs to transfer
three Q s to the multiplier because
it sees three diodes. As a result, the
total injected charges per cycle are
six Q s. The factor of six is consid-
ered as the number of diodes or
the number of capacitors plus one.
Thus, in general, Q IN = (N + 1) Q OUT .
Figure 3(c) calculates the rela-
tionship between the output volt-
age and current by proceeding from
(1) through (11). For simplicity, the
threshold voltage of the diode is
assumed to be small enough in
comparison with the input voltage
amplitude. (1) The voltage across the
first capacitor C1 (i.e., V1) in phase 1
is equal to VIN . (2) The voltage
across C1 in phase 2 is reduced by
transferred charges, which is 3Q /C,
from the voltage across C1 in phase 1.
(3) The voltage across C2 (i.e., V2)
in phase 2 is equal to V1 because
V1 is given by VIN + (V IN - 3Q/C),
V1 = 2VIN - 3Q/C. (4) The voltage
across C2 in phase 1 is reduced
by transferred charges, which is
2Q /C, from the voltage across C2 in
phase 2. (5) The voltage across C3 in
phase 1 is equal to that across C2
because both terminals of C3 are
short to those of C2. (6)(10) In this
way, one can calculate the voltage
across each capacitor. (11) The out-
put voltage is a sum of the voltage
at the left terminal of C1 and the
voltages across C1, C3, and C5 in
phase 2. Thus, VOUT = 6VIN - 19Q /C.
The factor of VIN is six, which is
the same as the number of diodes,
as shown in Figure 3(b). The factor
of Q/C is 19. Now we know that
such a large number results from
the fact that the voltage drops in all
the previous capacitors are added.
As a result, the total voltage drop
increases more rapidly as the num-
ber of stages increases. As for a

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 16 53

 Voltage converters are categorized into
two groups, the switching converter
and the SC converter.
general number of stages, a voltage
drop of k th capacitor is propor-
tional to k 2, and so the total volt-
age drop is proportional to N 3 [5].
Therefore, the CW multiplier with
a large number of stages has very
large output impedance.
An advantage of the CW multi-
plier is that voltages across each
capacitor and diode do not exceed
2VIN . This means that the multi-
plier can be composed of low-volt-
age devices, which implies that the
circuit area can be smaller than
a multiplier using high-voltage
devices. You may have to take care
of isolation from ground to prevent
the devices from being broken when
low-voltage devices are used.
Brugler SerialParallel,
(1971) Figure 4
As the output impedance of the
CW multiplier increases by a factor
of N 3, the challenge was to reduce
the output impedance. Brugler pro-
posed serialparallel (SP) configu-
ration using switches rather than
diodes in 1971 as shown in Figure 4(a)
[5]. The procedure to derive the
I OUT VOUT equation is much easier
than the CW. Assuming Q is the
amount of charge to be transferred
to the output terminal, each capaci-
tor loses the same amount of Q in in-
series phase as shown in Figure 4(b).
Thus, each capacitor needs to be
charged by Q in in-parallel phase.
Before charging Q , each capacitor
voltage should be VIN - Q/C. Thus,
VCAP = VIN - Q/C. Consequently, VOUT
is calculated as
VOUT =VIN +N VCAP = (N + 1) VIN -N Q/C.
(1)
Thus, the output impedance is propor-
tional to N 1, which is much smaller
than that of CW multiplier of N 3 .

V1 V3 V5
0V
C1 C3 C5

VIN C2 C4
Phase 1
VOUT
V2 V4
QIN = 6Q
V1 V3 V5
VIN
Phase 2 C1 C3 C5 QOUT
=Q
0V C2 C4
VOUT
V2 V4
(b)
(5) 2VIN 5Q/C (9) 2VIN 8Q/C
(1) VIN
V1 V3 V5
0V C1 C3 C5

C2 C4
Phase 1 VIN VOUT
V2 V4
(4) 2VIN 5Q/C (8) 2VIN 8Q/C

(2) VIN 3Q/C (6) 2VIN 7Q/C (10) 2VIN 9Q/C

Phase 2 V1 V3 V5
VIN C1 C3 C5
Q

(a) C2 C4
0V VOUT
V2 V4 (11) VOUT = 6VIN 19Q/C
(3) 2VIN 3Q/C (7) 2VIN 7Q/C
(c)

Figure 3:(a) A 2.5-MV generator using CW voltage multiplier [12]. (b) The charge flow of CW voltage multiplier in steady state [3].
(c) A CockcroftWalton voltage multiplier (1932) [3].

54 W I N T E R 2 0 16 IEEE SOLID-STATE CIRCUITS MAGAZINE

 What is the voltage across the
diode and capacitor of the SP cell? VIN
As can be seen in Figure 4(a), the V IN N VIN
capacitor voltage in parallel state is
equal to VIN and that in serial state In Parallel VOUT
is lower than VIN by Q/C. There-
fore, the capacitor could be made of GND
a low-voltage device, which enables
the reduction of the capacitor area
with higher capacitance density. VIN
In Series N VIN
On the other hand, the switches
used closely to the output terminal
VOUT
see N times higher than VIN for
GND (N + 1) VIN
both states, resulting in a require-
(a)
ment for high-voltage switching
devices. To integrate voltage mul-
In Parallel In Series
tipliers in ICs, you have to take
the impact of parasitic capacitance VIN N-Caps Q
into consideration.
Q
We know the SP works by chang- VOUT
ing the state alternately. When all VCAP
the capacitors are connected in
parallel with the power supply, VIN
there is no impact of the parasitic 0V VOUT = VIN + N VCAP
VCAP = VIN Q/C = (N + 1)VIN N Q/C
capacitance on the stored amount of (b)
charge in the capacitors. As shown
in Figure 4(c), when the capacitors No Cp w/Cp
Charge Loss qk
are connected in series, if the para- Q Q (q1 + ... + qN) N2
sitic capacitance (C p) is negligibly VIN
qN
small, each capacitor transfers a
same amount of charge Q to the
next capacitor, resulting in output- Q qk k VIN Q (q1 + ... + qN1)
ting Q. However, if the parasitic q2
capacitance is not negligible, the 0V
transferred charge is reduced at
every node. To be worse, the charge Q q1 Q q1
loss at an upper node is larger than
that at a lower node. The k th node Q Q
has a voltage amplitude of k Vin
from the parallel to in-series period. VIN VIN
Thus, the k th capacitor reduces the (c)
charge proportional to k Vin . The
sum of charge loss from the bottom Figure 4:(a) A serial/parallel voltage multiplier [5]. (b) A serial/parallel [5]. (c) A serial/
to the top would be proportional to parallel [5].
N 2 [14], [15]. This means that the
charge loss increases as the voltage
gain increases. As a result, serial Capacitors in Parallel Rather Than in Series with Modern Transistors
connection can lose voltage gain
0V VOUT
significantly.

Falkner Parallel (1973) Figure 5

Falkner showed another voltage CT
multiplier topology with lower 1 2 3 1 2 3
output resistance using parallel CB
configuration with a three-phase
clock as shown in Figure 5 [6]. The Figure 5:Parallel configuration for lower output impedance [6].

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 16 55

 100 m

VIN VOUT
1
2
(b)
Qq
q Qq
q

q q

Q Q

VIN 0V VIN 0V VIN 0V

Oscillator Multiplier Chain
Clock Drivers Output Limiter (k 1)th k th (k + 1)th (k 1)th k th (k + 1)th
(a) (c)

Figure 6:The first Si verified on-chip voltage multiplier [7].

key point is that each capacitor is

VIN 1 2
2 1
1 2
2 1
VOUT connected with a next neighbor in
1 parallel in each phase. The num-
ber of switches or diodes are that
of capacitors plus one, which is
Load

the same condition as the CW. The

1 2 1 2 bottom plate capacitance is moved
from a high-voltage path to a low-
GND voltage path, therefore it should
(a) have less dependence of parasitic
capacitance on the voltage gain.
Voltage Gain:
N VOUT_MAX/VIN
Dickson First Si Verified On-Chip
1 2 Voltage Multiplier (1976) Figure 6
2 3 In 1976, Dickson theoretically and
3 5 experimentally, for the first time,
4 8 studied an on-chip high-voltage
5 13 generator including a voltage mul-
(b) tiplier, oscillator, clock drivers, and
1VIN 3VIN 3VIN 8VIN VOUT
a limiter as shown in Figure 6(a)
VIN [7]. The diode is made of a MOSFET
1VIN 2VIN 3VIN 5VIN whose gate and drain terminals are
Load

connected, as shown in Figure 6(b).

Phase 1
Dickson used a two-phase clock,
which allowed the clock frequency
GND
as fast as possible. Using a seven-
2VIN 2VIN 5VIN 5VIN stage voltage multiplier, he success-
VIN
fully generated 40 V from the power
1VIN 2VIN 3VIN 5VIN
supply voltage of 15 V.
Load

Phase 2 The effective output impedance

R PMP and the maximum attainable
GND voltage VMAX are calculated as fol-
(c)
lows. When the input terminal is
connected with VIN, VMAX is as high
Figure 7:An SC voltage multiplier with smaller number caps [8]. as (N + 1) VIN when the number of

56 W I N T E R 2 0 16 IEEE SOLID-STATE CIRCUITS MAGAZINE

stages or capacitors is N. It is well In the 1990s, concerns about the SC voltage
known that the effective resistance
of an SC is 1/ (fC ), where f is the multipliers were the reduction in the number of
clock frequency. Thus, a parallel capacitors and switching devices for discrete high-
voltage multiplier with N-stages has
R PMP of N/ (fC). As a result,
power applications.

I OUT = fC ((N + 1) VIN - VOUT) /N.(2)

Because the amount of output
charges per cycle (Q) is I OUT /f, (2) is
identical to (1). Thus, an ideal paral-
lel voltage multiplier has the exact
same characteristic as an ideal SP
multiplier.
What about the impact of para-
sitic capacitance on the Falkner/
Dickson parallel voltage multi-
plier? The charge supplied from
the power supply is Q indepen-
dent of the capacitor location.
Assuming each capacitor loses q,
every capacitor can transfer Q - q
independently of the capacitor
location unlike the SP as shown in
Figure 6(c) [14], [15]. Thus, paral-
lel connection allows the parallel
multiplier to have many input ter-
minals, resulting in low loss in the
voltage gain. A drawback is that
capacitor needs to be composed on
high voltage devices.
in parallel. Capacitors and diodes
need to be high-voltage devices. As
the number of stages increases, the
voltage gain increases more rapidly
than the number of stages. Each
stage has one capacitor and three
switches. Theoretically, it is proven
that this topology has the small-
est number of stages in two-phase
clock multipliers [25].
gnd
2 2
1 1
VIN 2 2
1 1
VIN
2 2
Cernea 2 N (1995) Figure 8
Another multiplier having a smaller
number of stages is Cerneas 2N
multiplier, as shown in Figure 8(a)
[9]. When the number of stages con-
nected between the input and the
output is N, the required number
of capacitors are 2N because two
arrays are required to complete the
multiplier unlike the other types
2 2
1 1
VOUT
2 2 1
1 1 2
2 2

Load
1 1 1 1
Ueno Fibonacci (1991) Figure 7
In the 1990s, concerns about the SC gnd
voltage multipliers were the reduc- (a)
tion in the number of capacitors
and switching devices for discrete gnd
Phase 1
high-power applications. Ueno et
al. proposed, in 1991, a multiplier,
2VIN 4VIN 8VIN 16VIN
as shown in Figure 7(a), whose max-
VIN 1VIN 2VIN 4VIN 8VIN VOUT
imum attainable voltage is given
by the Fibonacci number when
I OUT = 0, as shown in Figure 7(b) gnd
[8]. Each box of Figure 7(a) indi-
gnd Phase 2
cates a switch, and 1 and 2 means
the switch turns on in phase 1 or
2, respectively. In phase 1, an even
1VIN 2VIN 4VIN 8VIN
number of stages are connected VIN
2VIN 4VIN 8VIN 16VIN VOUT
in series with the output termi-
nal and odd number of stages are
connected in parallel to the serial
gnd
one as shown in Figure 7(c). In
(b)
phase 2, the situations are comple-
mentary. Thus, half of the stages
are in series, and the other half are Figure 8:An SC voltage multiplier with smaller number stages [9].

IEEE SOLID-STATE CIRCUITS MAGAZINE W I N T E R 2 0 16 57

 Table 3. A Comparison of SC voltage multipliers.
VCAP /VIN VDIO /VIN #Serial Cap # input terminal Impact of C_para
CW Ladder 2 2 N/2 2 +
Brugler SP 1 N N 1 +++
Falkner and Parallel N 2 0 N+1
Dickson
Ueno Fibonacci F(N2) F(N1) N/2 1 ++
N N1 N2
Cernea 2 2 3x2 N 2 +++

required area and resultant power

efficiency of SP, Fibonacci (FIB2),
SP FIB2 2N SP FIB2 2N
and 2 N (2 N) cells are normalized
Relative Power Efficiency

5 1.0
by those of Falkner-Dickson parallel
Relative Circuit Area

4 0.8 cell in Figure 9 [17]. All the capaci-

3 0.6
2 0.4
1 0.2
0 0.0
0 2 4 6
Voltage Gain
(a)
Figure 9:Multiplier area versus parasitic capacitance [17].
of voltage multipliers. The upper
side of Figure 8(b) shows a first half
period when I OUT = 0. The upper
stages are connected in series with
the output terminal, whereas the
lower stages are connected in par-
allel with the upper stages. As the
number of stages increases by one,
the maximum attainable voltage
increases by a factor of two in an
ideal case where no parasitic capac-
itance is considered. You may con-
sider the number of stages of the
2 N multiplier to be smaller than
that of the Fibonacci voltage multi-
plier. But thats not the case because
the 2 N voltage multiplier needs two
arrays. Capacitors and diodes need
to be high-voltage devices.
Comparison of Voltage Stress
on Devices and Impact
of Parasitic Capacitance
Table 3 summarizes the character-
istics of each SC voltage multiplier
[15], [16]. The CW and SP multipli-
ers can be composed of low-voltage
8 10 0 2 4 6
Voltage Gain
(b)
capacitors, but the number of seri-
ally connected stages is large and the
number of input terminals is small.
As a result, the impact of parasitic
capacitance (C_para) is significant.
On the other hand, the Falkner and
Dickson parallel multiplier has less
impact of parasitic capacitance on
charge transfer because the number
of serially connected stages is small
and the number of input terminals
is large. Ueno Fibonacci/Cernea 2 N
cells can have a fewer number of
capacitors than the others, but half
to all capacitors are connected in
serial, resulting in a significant loss
in voltage gain due to the high sensi-
tivity of parasitic capacitance.
Best Topology for Integrated
Voltage Multiplier
To identify the best topology for inte-
grated voltage multiplier especially
whose voltage gain is more than a
few, the area and power efficiency
of each topology cell are quantita-
tively compared one another. The
tors in a cell are assumed to be
uniform except for FIB2, where the
k th stage capacitor size is made
proportional to Fibonacci number of
(N - k) . In a typical CMOS process,
8 10 the top and bottom plate parasitic
capacitance can be as large as 10%
of the multiplier capacitor including
the parasitic capacitance of wiring
and switching devices. Each multi-
plier is designed to have the same
output current with the same clock
frequency. As seen in Figure 9(a),
any cell needs larger circuit area
than the parallel cell for a voltage
gain greater than three. The power
efficiency in Figure 9(b) has a simi-
lar trend as does the area. As the
number of multiplier capacitors
needs to be increased, more power
needs to drive the parasitic capaci-
tance, which results in lower power
efficiency. As a result, the Falkner-
Dickson parallel multiplier should
be selected for integration with
respect to area and power.
Figure 10 shows more evidence
about the best topology for inte-
gration across the voltage gain in
literature. I and D , respectively,
indicate integrated and discrete.
Two designs have been realized with
CockcroftWalton cells for earphone
to have a voltage gain of five with
no high-voltage devices [18], [19].
There have been some designs with
SP and Fibonacci cells that have volt-
age gains higher than five but either
has needed discrete capacitors and

58 W I N T E R 2 0 16 IEEE SOLID-STATE CIRCUITS MAGAZINE


[18] Tseng et al. (2007)
[19] Tsai et al. (2012)
[20] Tsukamoto et al. (2013)
[21] Karadi et al. (2014)
I [18], [19]
CW
D [21]
SP
Fib
Para I [7] I [23]
3 5 6 8
Voltage Gain
Figure 10:Circuit topology versus voltage gain in literature.
power FETs to have sufficiently
small parasitic capacitance and large
multiplier capacitance. On the other
hand, there have been many designs
with the Falkner-Dickson parallel
cell to have voltage gains as high as
over ten (e.g., [24]). The following
articles in this series focus on the
parallel voltage multiplier, which is
called charge pump afterwards.
References
[1] H. Greinacher, The ionometer and
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About the Author
Toru Tanzawa (toru.tanzawa.jp@
ieee.org) is a distinguished member
of technical staff at Micron Memory
Japan, Inc. He received the Ph.D. de-
gree in electrical engineering from
The University of Tokyo, Japan, in
2002. He has been with Toshiba and
Micron, where he has worked on the
circuit design of high-density NAND
flash, high-speed, low-voltage NOR
flash, and RF-CMOS wireless ICs
since 1992. He holds 165 granted
U.S. patents, has published 37 pa-
pers in IEEE conferences and jour-
nals, and wrote the book On-Chip
High-Voltage Generator Design: De-
sign Methodology for Charge Pumps,
Second Edition (Springer, 2015) and
Chapter 3: Low Power Memory De-
sign in Power Aware Design Method-
ologies (Kluwer Academic, 2002). He
is a Fellow of the IEEE.