Digital Logic

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RTL & Verilog

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Interview Questions

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A Practical Study Guide

for Design Engineers

VerilogCode.com

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Copyright2015byVerilogCode.com
Allrightsreserved.Thisbookoranyportionthereof
maynotbereproducedorusedinanymannerwhatsoever
withouttheexpresswrittenpermissionofthepublisher

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Forpermissionrequests,contactVerilogCode.com

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Digital Logic
RTL & Verilog

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Interview Questions

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A Practical Study Guide

for Design Engineers
VerilogCode.com

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Digital logic
RTL & VeriloG

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Interview Questions

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About the Author:
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Trey Johnson has been designing digital logic circuits and writing
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RTL code in both Verilog and VHDL languages for almost twenty years.

In the late 1990s, Johnson designed and developed some of the

first multimedia hardware components used inside early smartphones,
with his primary design focus in video and graphical subsystems, LCD and
camera subsystems, and 2D hardware accelerators. He has worked
closely and designed hardware components for both ARM and DSP
processors and cache subsystems. He also has experience designing I/O
peripherals such as resistive touch screen displays, magnetic card
readers, PCI Express controllers and SerDes subsystems, and memory
controllers.

Johnson has been granted three United States Patents for his
digital design solutions. He is the founder of
VerilogCode.comwhich is a
website dedicated to sharing information about Verilog and RTL design.

Please visit the website for more digital design and job interview
questions and to also share your own experiences.

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ThisbookisdedicatedtoBrandi,Tucker,GunnerandAlexa

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Thankyouforridingwithmeonlifeswavesofchange,
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...andforembracingthejourneyalongtheway.
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TableofContents
Introduction 17

RTLVerilogSyntaxQuestions..... 19

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RTLLogicDesignQuestions... 29

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ClockDividers,ClockGating,andResetQuestions. 49

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ClockDomainCrossingQuestions. 59
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PowerRelatedDesignQuestions.... 65
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DigitalLogicQuestions.... 71

LogicalThinkingQuestions...... 93

AnswerstoLogicalQuestions....... 99

FurtherReadingandStudyingonYourOwn........ 103

PersonalInterviewNotesandQuestions.... 105

CreditandSources. 119

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ListofQuestions
RTLVerilogSyntaxQuestions

1. Explainblocking nonblocking
versus statements
2. ShowVerilogcodefor bitwise
versusconditional
operators
3. Verilogcodeforlogicgates:
and,or,nand,nor,xor,xnor

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4. Verilogcodeforbitwisereduction

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5. Verilogcodemultiplyinganddividingbypowersof2
6. Verilogcodeforsignextensionandconcatenation

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7. WriteVerilogCodefor asynchronous andsynchronousFlipFlops
8. Verilogcodingwhatarethreewaystocodeamux

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9. Whattypeofcircuitwouldthesynthesistoolcreateformuxcode
10. Verilogcodeforlatchversusflipflopanddrawtimingdiagram

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RTLLogicDesignQuestions
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11. Designacircuittodetectifasignaltransitionsinanydirection
12. Designacircuittodetecta1cyclehighpulse(synchronously)
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13. Designasequencedetectorcircuittodetect1,0,1,1,0usingFSM
14. Verilogcodetodetectapattern10110anywhereinlast8samples
15. Forthetimingdiagramshow,writeVerilogcodetocreateit
16. Designadebouncecircuittoremoveinputglitches
17. WriteVerilogcodetoconvertBCDtograycode
18. DesignasynchronousfifomoduleusingdualportRAM
19. Designacircuittodetectifnumberisdivisiblebythree
20. DesignacircuittocalculateFibonaccisequence
21. Designacircuittofindthemaximumandsecondhighestnumber
22. Designacircuittooutputsecond,minute,andhourfrom1msinput
23. Giventhetimingdiagram,writetheequivalentVerilogcode
24. DrawthestructureofadigitalFIRfilterwith5taps

ClockDividers,ClockGating,andResetQuestions

25. Designaclockdivideby2circuit
26. Designaclockdivideby3circuit(with50percentdutycycle)
27. DesignaclockdividerbyNcircuit(with50percentdutycycle)
28. Designaglitchfreeclockgatingcellwithenablepin
29. Howtodetectarisingedgeofaninputsignalifclocksareoff
30. Designaresetcircuitwithasyncassertionandsyncdeassertion

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ClockDomainCrossingQuestions

31. Whatismetastability?
32. Designacircuitfromaslowclockdomaintoafastclockdomain
33. DesignacircuittohandleCDCfromfastdomaintoaslowdomain
34. Howwouldthecircuitchangeifyouneedtosynchronizeabus?
35. Graycodingtechniquestocrossclockdomains

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PowerRelatedQuestions

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36. Describetwocomponentsofpower

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37. Describehowtoreducestaticpower
38. DescribehowtoreduceDynamicpower

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39. DescribelowpowerRTLcodingtechniques

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Refresher:DigitalLogicQuestions og
40. Whatisdefinitionofsetupandholdtimeforaflipflop
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41. VennDiagramandBooleanLogic
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42. LogicGateDesignTransistorLevel
43. CrossSectionofatransistorunderstandtheprocessnode
44. KarnaughMaps(clkdivideby3circuitnot5050dutycycle)
45. HalfAdderusingXORgatesforadditionandANDgateforcarry
46. Usingonly2inputmuxes,createa nand nor
, inverter
, or
, and
, ,
xor
47. HowtouseandXORgatelikeacontrolledinverter?
48. Designaninverter and
, or
, xor
,and gateusingjustnandgates
49. Create4:1muxusing2:1mux
50. Whatisthefastestfrequencythiscircuitcanrun?
51. Convertthisdecimalvaluetobinary,hex,andoctalformat

LogicalThinkingQuestions
52. FourGallonsofWater
53. ThePathtoFreedom
54. ThreeLightSwitches
55. MultiplicationQuestion
56. EinsteinsRiddle

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ListofFigures
1. BlockingStatementsandEquivalentGates (Fig.1)
2. NonblockingStatementsandEquivalentGates (Fig.2)
3. TimingDiagramcapturewithlatchandflipflop (Fig.3)
4. Latchvs.FlipFloptimingdiagram (Fig.4)
5. EquivalentGatesfromRTLcodeinEx.11(Fig.5)

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6. TimingDiagramforEdgeDetectionusingclocks (Fig.6)

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7. SequenceDetectorusingFSM (Fig.7)
8. DecoderCircuitShiftRegisterandCombinatorialLogic (Fig.8)

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9. WritetheVerilogcodetoproducetheabovewaveform (Fig.9)

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10. ClassicSynchronizerCircuitusing2FlipFlops (Fig.10)
11. Circuittodetectlowtohightransition (Fig.11)

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12. BCDtoGrayCode (Fig.12) og
13. CircuittoGenerateFibonacciSeries (Fig.13)
14. WriteVerilogCodetoProducethisTimingDiagram (Fig.14)
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15. 5TAPDigitalFIRfilter
(Fig.15)
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16. TimingDiagramforClockDivideby3
(Fig.16)
17. TimingDiagramforClockDivideby3(5050dutycycle) (Fig.17)
18. TimingDiagramforClockDivideby4(5050dutycycle) (Fig.18)
19. TimingDiagramforClockDivideby5(5050dutycycle) (Fig.19)
20. LatchedBasedClockGatingCircuit (Fig.20)
21. Classic2StageSynchronizer (Fig.21)
22. ClockDomainCrossingusingFullHandshaking (Fig.22)
23. SynchronizeBusAcrossClockDomainsFullHandshake (Fig.23)
24. ExampleofCriticalPathinSequentialCircuit (Fig.24)
25. VennDiagram
(Fig.25)
26. LogicGatesforA&(B|C) (Fig.26)
27. CrosssectionofCMOSTransistor (Fig.27)
28. 3StateFSMforClockDivider (Fig.28)
29. Graycoding(withviolationfromstate11tostate00)
(Fig.29)
30. 2bitFSM(illegalgraycodetransition) (Fig.30)
31. SixstateFSMwithcorrectgraycodevalues (Fig.31)
32. EquivalentGatesResultandCarry (Fig.32)
33. FullAdderCircuit
(Fig.33)
34. MultibitAdder
(Fig.34)
35. Inverter
(Fig.35)
36. ANDGateImplementedwithNANDGates (Fig.36)
37. ORGateImplementedwithNANDGates
(Fig.37)
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 38. XORGateImplementedwithNANDGates (Fig.38)
39. 4:1Muxcreatedwith2:1muxes
(Fig.39)
40. 4:1muximplementedwithcombinatoriallogic(Fig.40)
41. Whatismaximumfrequencythiscircuitcanrun?(Fig.41)

ListofVerilogCodingExamples

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1. Operator:&versus&& (Ex.1)

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2. Operator:|versus||
(Ex.2)
3. Operator:~versus! (Ex.3)

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4. BitwiseOperators (Ex.4)

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5. BitwiseReduction (Ex.5)
6. ShiftOperations (Ex.6)

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7. ConcatenationOperations (Ex.7)
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8. Verilogcodingstylesfora4:1mux (Ex.8)
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9. PriorityEncoder (Ex.9)
10. ParallelMuxingSchemeusingfullcasestatement (Ex.10)
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11. VerilogcodeforLatchandFlipFlop (Ex.11)

12. VerilogCodeforEdgeDetection (Ex.12)
13. Circuittodetectpulse
(Ex.13)
14. ExampleVerilogCodefor Fig.9
waveform (Ex.14)
15. VerilogCodefor3bitGrayCode (Ex.15)
16. VerilogcodetoconvertBCDtoGrayCode (Ex.16)
17. FIFOcontrollogic (Ex.17)
18. FSMstatesfordivisibleby3circuit (Ex.18)
19. VerilogcodeforFibonacciGeneration (Ex.19)
20. Verilogcodetogenerateonesecond,minute,andhour (Ex.20)
21. VerilogCodefor Fig.14TimingDiagram (Ex.21)
22. VerilogCodeforClockDivideby2 (Ex.22)
23. VerilogCodeforClockDivideby3with5050dutycycle (Ex.23)
24. ExampleVerilogCodeforGenericClockDividebyN (Ex.24)
25. ExampleVerilogCodeforGlitchFreeClockGate (Ex.25)
26. AsynchronousEdgeDetectionCircuit
withnoclocks(Ex.26)
27. VerilogcodeforResetsynchronization (Ex.27)
28. Start/StopConditionsforCounters
(Ex.28)

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ListofTables
1. AsynchronousversusSynchronousFlipFlops (Table1)
2. InverterGate,TruthTable,andtransistorlevelcircuit (Table2)
3. NANDGate,TruthTable,andtransistorlevelcircuit
(Table3)
4. NORGate,TruthTable,andtransistorlevelcircuit (Table4)
5. ANDGate,TruthTable,andtransistorlevelcircuit
(Table5)

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6. ORGate,TruthTable,andtransistorlevelcircuit(Table6)

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7. SemiconductorManufacturingProcessingNodes
(Table7)
8. TruthTableforanAdder(Table8)

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9. InverterImplementedwith2:1mux (Table9)

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10. ANDGateImplementedwith2:1mux (Table10)
11. ORGateImplementedwith2:1mux (Table11)

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12. NANDGateImplementedwith2:1muxandinverter (Table12)
13. NORGateImplementedwith2:1muxandinverter
og (Table13)
14. XORGateImplementedwith2:1muxandinverter (Table14)

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15. XNORGateImplementedwith2:1muxandinverter (Table15)
16. XORGateUsedasControlledInverter (Table16)
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17. PathtoFreedomDoors
(Table17)
(
18. MultiplyQuestionTable18)

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Introduction

Im30,000feetabovetheground,onaplaneheadedtoSanDiego
forajobinterview.Imalittleanxious,andItakesomecomfortin
lookingoutofthesmallwindowpanenexttome.Myeyeswanderback

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downtothemagazinearticlesittingonmylap,thenIreadthesewords:

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Transitions
.
Thatsalllifeis,anditstougherthanphysics.

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Fromschooltoworktoretirementtodead .

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Themagazinearticleisaboutchildrenwhoareinterviewingfor

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preschool,andthemostimportantcharacteristicthattheadministrators
lookforishowwellcanthechild
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adapt tochangewithnewsurroundings
andnewrules.Butthisarticlecouldhavebeenwrittenaboutme:an
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engineerwhospenteighteenyearsworkingforthesamecompany,and
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onedaywassuddenlyletgoasaresultofacorporatedownsizing.Iam
nowtheonewhomustadapttochange,newsurroundings,andnewrules.

ThisbookdocumentsrealinterviewquestionsthatIencountered
frommyownpersonaljobinterviewingexperienceswithsomeofthe
toptiersemiconductorcompaniesintheworld.Thisbookalsocontains
fundamentaldigitaldesignmaterialandpracticalVerilogcodeexamples
thatIcreatedbasedonthethemesfromthetypesofquestionsthatI
experiencedfirsthand.Thisbookwillhelpprepareyouforyourown
interviewingprocess.Itisbynomeanstheendall,butrather,consider
thisbookasagreatstartingpoint.Asyoureadthroughsomeofthe
questions,Iwillalsosharewithyousomeofmypersonalinsightand
knowledgeinthe AuthorsTips section,whichIhaveacquiredthroughmy
careerasadigitallogicprofessional.

Interviewingforajobislikegoingonadateatfirstyoumayfeel
alittlenervousorawkward,butaftersometimeandmoreinterviewsyou
soonbecomemorecomfortableandconfident.Donotgetdiscouragedin

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thebeginning!Thejobinterviewingexperiencecanbedaunting.Itwill
testyourmentaltoughness.Iexperiencedheadachesduringmyfirstfew
interviewsbecauseofthelonghoursofmentalstress.Butthesayingis
truethatpracticemakesperfect
.Afterseveralmoreinterviewattempts,I
becamemorecomfortable,developedasenseofcalmness,andfeltmore
preparedtoanswerthequestions.

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Iveencounteredmanydifferenttypesofinterviewquestions

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rangingfromrealworldpracticalexamples,toacademictextbookor

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theoreticalquestions(usuallyaskedbypeoplewithPHDswithnotmuch

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practicalexperience),totrickyquestionsusingsomeobscurecircuit
(whichwouldneverbeapplicableintherealworld),tobehavioral

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questions(usuallyaskedbyHumanResourcerepresentatives).This
og
bookfocusesonrealworldpracticalexamples,anditalsodiscussessome
ofthetrickyandobscurequestionsthatareasked.Preparingfor
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behavioralquestionsisimportantandiscoveredonourwebsite.
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Thisbookisdividedintomultiplesectionscoveringthefollowing
topics:RTLVerilogcodingsyntax,RTLLogicDesign(includinglow
powerRTLdesignprinciples),clockingandresetcircuits,clockdomain
crossingquestions,digitaldesignfundamentals,andlogicalthinking
questions.Eachsectionisunrelatedtotheothersoyoucanjumparound
toanysectionorquestionthatinterestsyou.

Thisbookisagreatstartingplaceforyoutobeginpreparingfor
yourjobinterview.Thisbookprovidesyouwithabroadrangeof
informationandcoversmanytopics.Bytheendofthisbook,youwill
havemoreknowledgeandinsightintothetypesofdigitaldesigninterview
questionsbeingaskedinthefieldofsemiconductordigitaldesign.

Rememberthatlifewillalwaysbringaboutchange,anditshow
wellyoucantransitionandadaptthatisimportant.Haveastrongand
positiveattitudeandyouwillsucceed!

Goodluckonyournewjourney!

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RTL Verilog Syntax Questions
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1. What is the difference between blocking and
non-block statements, and when are they used?

BlockingstatementsarecodedinVerilogwiththe=operator,and
blocks
areusedwhencreatingcombinatoriallogic.Thisoperator the
simulatorfromexecutingsubsequentstatementsuntilthecurrent

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evaluationandassignmentisdone.Considerthefollowingcode(Eis

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assignedtheimmediatenewvalueofC):

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BlockingStatementsandEquivalentGates
(Fig.1)

NonblockingstatementsarecodedinVerilogwith<=operator,
arealwaysusedwhencodingflipflopsinsideaclockedprocess.The
assignmentispostponeduntilallthesubsequentstatementsareevaluated.
Thisallowsforparallelorconcurrentexecutionofstatements.Inthis
example,EisassignedthepreviousvalueofC(nottheimmediate):

NonblockingStatementsandEquivalentGates
(Fig.2)

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2. Explain the difference between logical and bitwise
operators

InVerilog,youshouldunderstandthedifferentsyntaxusedfor
writingconditionalifstatementoperationscomparedtowritingcodefor
creatinglogicalgateswithbitwiseoperations.

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Forbitwiseoperationsresultinginan ANDgate,usethe&operator

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and
assign C = A & B; //This will create an gate

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Forconditional and
ifstatements,usethe&&operator

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if ( cond1 == 1b1 && cond2 == 1b1) {...}
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Operator:&versus&&
(Ex.1)

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Forbitwiseoperationsresultinginan ORgate,usethe|operator
or
assign C = A | B; //This will create an gate

Forconditional or
ifstatements,usethe||operator
if ( cond1 == 1b1 || cond2 == 1b1) {...}
Operator:|versus||
(Ex.2)

Forbitwiseoperationsresultingin invertergate,usethe~operator
assign A = ~B; //This will create an
inverter

Forconditional not
ifstatements,usethe!
if (!cond1) { }
Operator:~versus!
(Ex.3)

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3. Write code for logic gates:
and, or, xor, nand, nor,
xnor
assign C = (A & B); AND
// gate
assign C = (A | B); OR
// gate
assign C = (A ^ B); XOR
// gate
assign C = ~(A & B); NAND
// gate

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assign C = ~(A | B); NOR
// gate

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assign C = ~(A ^ B); XNOR
// gate

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BitwiseOperators
(Ex.4)

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4. How can you bitwise reduce a multibit signal?

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wire [15:0] databus; og
wire all_ones_detected;
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wire is_databus_odd;
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wire signal_not_zero;

AND
assign all_ones_detected = &databus; // all the bits together;
assign is_databus_odd = ^databus; // XOR
all the bits together;
assign signal_not_zero = |databus; // OR all the bits together;
BitwiseReduction
(Ex.5)

5. What code multiplies or divides by powers of 2?

assign C = A << 2; // shift left ( multiply by 4)
assign C = A >> 3; // shift right (division by 8)
ShiftOperations
(Ex.6)

6. How would you perform sign extension?

reg [4:0] A;
wire [9:0] C;
assign C = { {5{A[4]}} ,A}; // sign extension
ConcatenationOperations
(Ex.7)

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7. What are three ways to code a 4:1 mux in Verilog?

Assumethe4:1muxinputsarenamedA,B,C,D,youwillneed
select
a2bit output
line(tochoosebetween4inputs)andhavea1bit :

Coding Style 1:

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assign output = (select == 2b00 ) ? A :

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(select == 2b01) ? B :
(select ==2b10) ? C : D;

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Coding Style 2:

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always @(*)
if (select == 2b00) og
output <= A;
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else if (select == 2b01)
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output <= B;
else if (select == 2b10)
output <=C;
else
output <= D;

Coding Style 3:
always @(*)
case (select):
2b00: output <= A;
2b01: output <= B;
2b10: output <= C;
2b11: output <= D;
end case;
Verilogcodingstylesfora4:1mux (Ex.8)

Youcouldalsoinstantiateamuxcelldirectlyifitexistsinyourlibrary.

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8. What circuit would synthesis create for previous
mux coding styles?

CodingStyles1and2areequivalentcircuitsbutusedifferent
codingstyles,andbothproduceapriorityencoder(pathAishighest)
Style 1:

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assign output = (select == 2b00) ? A :

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(select == 2b01) ? B :

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(select ==2b10) ? C :
D;

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Style 2:
always @(*) og
if (select == 2b00)
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output <= A;
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else if (select == 2b01)

output <= B;
else if (select == 2b10)
output <=C;
else
output <= D;

PriorityEncoder
(Ex.9)
Style 3
always @(*)
case (select):
2b00: output <= A;
2b01: output <= B;
2b10: output <= C;
2b11: output <= D;
end case;

ParallelMuxingSchemeusingfullcasestatement
(Ex.10)

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9. Write Code for Asynchronous/Synchronous Flip
Flops and discuss the pros and cons of each

Asynchronous Synchronous

always @(posedge clk or always @(posedge clk)

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negedge rst) If (!rst )
Verilog

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If (!rst ) Q <= #1 1b0;
Code Q <= #1 1b0; else

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else Q <= #1 D;
Q <= #1 D;

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Schematic
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Noneedtoworryabout
Pros Noneedforclockstoberunning
asynchronoustiming

Anyglitchonresetsignalwill
resetflops(Iftherearecross
Needtotimeboththe
clockdomainpaths,thenyou
Cons assertionofresetand
needtosynchronizetheresetto
alsodeassertionofreset
eachclockdomain).Needto
timetheremovalofreset

AsynchronousversusSynchronousFlipFlops(Table1)

AuthorsTip :ThequestionssofarhasfocusedonVerilogsyntax.
BasicsyntaxquestionscaneasilybelookeduponGoogle( after
you
haveajob),however,onajobinterviewitsimportanttobeprepared
forthesequestionsandknockthemoutofthepark.

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10. Write Verilog to capture input below with a latch
and a flip flop, and draw the timing outputs of each.

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TimingDiagramcaptureinputintoalatchandflipflop
(Fig.3)

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//purposely coding latch

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always @(clk or input)
if (clk == 1b1)

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Q_latch <= input;
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//flip flop coding a Latch
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always @(posedge clk)
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Q_flop <= #1 input;

VerilogcodeforLatchandFlipFlop
(Ex.11)

Theoutputsofthelatchandflipflopisbelowinthetimingdiagram:

Latchvs.FlipFloptimingdiagram
(Fig.4)

Theoutputoftheflipfloponlychangesontherisingedgeofclock,and
willequalthevalueoftheinputcapturedattherisingedgeofclock.The
latchoutputwillfollowtheinputsignalwhilethelatchisopen(inthis
casewhileclockishigh).Whenthelatchcloses(clockislow),theoutput
holdsitspreviousvalue.

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RTL Logic Design Questions
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11. Design a circuit that can detect if an input signal
transitions in either direction. Draw a timing diagram.

Forthisanswerletsassumethereisaclockavailable,andalsothe
inputsignalDisonthesameclockdomainasourcircuit.Aswithall
interviewquestions,youshouldstateyourassumptionsbeforeanswering

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thequestionsorconfirmwiththeinterviewersoyouarebothonthesame

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page.
Theeasiestwaytodetectifaninputsignalhaschangeditsimply

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comparecurrentsignalattimeTtothepreviousversionofthesignalat

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timet1.Therefore,aflipflopisusedtocapturethesignal,andthenyou
cancompareittothepreviousversionofthesamesignal:

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//capture the signal to have a delayed version
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always @ ( posedge clk or negedge reset)
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if (~reset)
Q <= #1 1'b0;
else
Q <= #1 D;

//detect signal transitions

assign Toggle = (Q ^ D) ; //xor gate
assign Falling = ~D & Q; / /D is low, but was high
assign Rising = D & ~Q; // D is high, but was low
VerilogCodeforEdgeDetection
(Ex.12)

EquivalentGatesfromRTLcodeinEx.11
(Fig.5)
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 Thetimingdiagramisshownbelow.Thiswaveformwasdrawn
withtoolcalledTimeGen,downloadedfromXFusionSoftware.com:

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TimingDiagramforEdgeDetectionusingclocks
(Fig.6)
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12. Design a circuit to detect a 1 cycle pulse input
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Usingdelaystatestorememberthestateofthesignalforprevioustwo
cycles,youcansimplecheckfor0,1,then0.YoucouldalsouseanFSM.

//capture the signal and delay 2 cycles

always @ ( posedge clk or negedge reset)

if (~reset) begin
Q1 <= #1 1'b0;
Q2 <= #1 1'b0;
end
else begin
Q1 <= #1 D; //delay T-1
Q2 <= #1 Q1; //delay T-2
end;

assign pulse_high= ~D & Q1 & ~Q2;

Circuittodetectpulse(Ex.13)

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13. Design a sequence detector for the pattern: 10110

OnemethodistodesignaFSMtodetectthesequence.IftheFSM
reachesstate5,thengenerateavalidoutputpulse(alltheotherstateswill
outputlow).Itsalsoimportanttomakesureyougobacktocorrectstate
ifthewrongvaluecomesin(youdontalwaysneedtogobacktoidle

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state).Youneedtocheckifsomeofthesequencehasalreadystartedand

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gobacktotheappropriatestate.

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SequenceDetectorusingFSM
(Fig.7)

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