Electronic and MEMS Packaging using
3D Integration Technologies
1. General Description
3D integration is of major interest for several
applications in fields of microelectronics and
MEMS technology. Hereby chips are stacked
vertically with electrical contacts through the
silicon to minimize electrical path lengths and
thus enhance the electrical and thermal
performance as well as to minimize the chip
size as well as parasitic capacitances. The
fabrication technology comprises processes
such as wafer thinning, Through-Silicon-Via
(TSV) drilling/etching, TSV filling and wafer
bonding.
2. TSV etching
The geometry of TSVs has large impact on the
subsequent filling with conductive materials. We
are developing etch processes for optimized via
profiles such as tapered openings.
aspect ratios up to 9
smallest TSVs: 3x10 m with depths up
to 70 m
Tapered via opening with 86 top to
sidewall angle
Fig. 1: TSV etching (3 TSVs 10 m x 70 m)
Fig. 2: TSV Copper metallization by MOCVD
3. TSV metallization
The metallization scheme is as following:
MOCVD TiN
Deposition of adhesion layer (TiN based)
In situ MOCVD Cu (CupraSelectTM)
Electroplating (Cu)
4. Chemical Mechanical Polishing CMP
For planarization of deposited layers and
bonding preparation different kinds of CMP
processes have to be integrated. Starting from
metal polishing, especially copper and barrier
materials up to silicon and silicon oxide
processes must be performed for 3D
integration. The applications connected to these
processes range from back-end of line
integration schemes in microelectronics to the
fabrication of specific substrates as well as
MEMS packaging.
5. Waferbonding
The stacking technology for 3D integration is
mostly based on wafer bonding using metallic
or conducting intermediate layers for the
electrical contact but also for the bonding
interface. Beside anodic bonding or silicon
direct bonding, also eutectic bonding, metal
thermo compression bonding, glass frit
bonding, adhesive bonding and laser assisted
bonding are applied to package sensor and
actuator components as well as electronics at
wafer level.
6. Equipment
DRIE etching tool (150 mm)
PECVD tools (200 mm)
ECD tools (150/200 mm
CMP tools (150/200 mm)
Substrate bonders (150/200 mm)
7. Contact
Dr.-Ing. Ramona Ecke (TSV metallization)
Tel.: +49 (0) 371/531-35614
Fax: +49 (0) 371/531-835614
E-Mail: ramona.ecke@zfm.tu-chemnitz.de
Dr.-Ing. Maik Wiemer (Bonding and Packaging)
Phone: +49 (0) 371/5397-1474
Fax: +49 (0) 371/5397-1310
E-Mail: maik.wiemer@enas.fraunhofer.de