DTMOS
DTMOS Power Switch in 28 nm UTBB FD-
FD-SOI Technology
J. Le Coz1, B. Pelloux-Prayer1, B. Giraud2, F. Giner1, P. Flatresse1
1 STMicroelectronics, Crolles, France 2 CEA-LETI-MINATEC, Grenoble, France
julien.le-coz@st.com
1. UTBB 28nm FD-
FD-SOI Technology
Ultra-Thin Body and Box (UTBB) Fully Depleted
Silicon-On-Insulator (FD-SOI) Technology has become
mainstream in the industry with the objective to serve a wide
spectrum of mobile multimedia products [1]. Transistors (fig 1)
are fabricated in a 7nm thin layer of silicon sitting (Tsi) over a
25nm buried oxide (Tbox). Thanks to its better electrostatic
control [2]; UTBB FD-SOI technology brings a significant
improvement in terms of performance and power saving,
complemented by an excellent responsiveness to power
management design techniques for energy efficiency
optimization. However, looking for a steady increase in
performance for a voltage supply value constantly lowered with
the evolution of technologies, BULK or FD-SOI, involves a
decrease in the threshold voltage (Vt) and leads to an increase
of the stand-by leakage current, requiring the implementation
of a leakage current reduction technique.
2. Power Switch Technique
Among low-power design solutions, the power switch (PS)
design technique [3][4] (fig 2) appears as the most efficient in
terms of leakage current reduction. The two main parameters
to be taken into account are the equivalent resistances in ON
and OFF states, respectively Ron and Roff. Ron creates a
voltage drop (Vdrop), whereas the leakage current of the logic
circuit in a quescient state (Iddq) is reduced in OFF mode to a
lower value (Ioff) equals to VDD/Roff. The higher Roff/Ron
ratio, the better the solution. As demonstrated in [4], it is
important to notice the power switch network area must also
be taken into account.
In the present work, the power switch has been derived in
two versions associated to a flip-well low-Vt (LVt) logic block,
as describe in [5]. Both versions use specific PMOS into NWELL
transistor enabling wide voltage range on the gate [0V-VVDIO
1.8V] and therefore super cut-off when OFF [6]. The first version
is based on a classical power switch solution while the second
one is based on a Dynamic Threshold MOS transistor, also
called DTMOS or BIMOS [7] (fig 3). When comparing the two
approaches, the DTMOS exhibits a higher Roff/Ron ratio
induced by the dynamic extended Body Biasing (BB) thanks to
the direct gate-to-body conection: Forward (FBB) when ON -
reducing Ron - and Reverse (RBB) when OFF (Vbs=VDDIO-
VDD>0) - increasing Roff. The DTMOS solution is only
applicable in SOI because the drain and source are isolated
from the well thanks to the buried oxide eliminating the
978-1-4799-1361-9/13/$31.00 2013 IEEE
parasitic junction leakage currents when the device is ON as
shown in fig 1.
This specific UTBB FD-SOI transistor enables a reduction
of the unitary power switch Ron by more than 20% (VDD<1.1V),
with respect to the classical FD-SOI solution (fig 4). Thereby,
with the DTMOS solution designed with VDD=1V10%, the
number of power switch (Nsw) composing the network can be
reduced by 20% for the same total Ron. Furthermore,
compared to its 28 nm BULK counterpart, Ron of the FD-SOI
DTMOS is reduced by 35% for a 1.1V power supply.
A digital block based on Low Density Parity Checker,
LDPC, commonly used in wifi applications [5][8] has been
implemented in silcon in order to compare and validate the 3
power switch options, classical BULK, classical FD-SOI and
DTMOS FD-SOI.
When OFF, the power switch solution, whathever the
technology considered, exhibits more than 3 decades leakage
reduction, demonstrating the efficiency of power switch design
technique. The UTBB FD-SOI DTMOS power switch solution
appears as most efficient approach: with 20% less Nsw, it
shows a Ioff current 40% lower than the classical FD-SOI
When ON and at same speed [5], the LDPC in LVt BULK
with a FBB of 300mV is supplied at 1V when the LVt FD-SOI is
supplied at 0.8V (-20%) and the flip-well LVt FD-SOI LDPC is
supplied at 0.7V (-30%). In the last condition, the Iddq of the
flip-well LVt FD-SOI LDPC is around two times lower than the
Iddq of LVt BULK LDPC. Moreover, when OFF and compared to
the classical power switch BULK solution, the Ioff of the
classical FD-SOI solution is 21 times lower and is divided by 35
with the DTMOS FD-SOI solution, as illustrated fig 5 and
summarized in table 1.
The wake up time (fig 6) is similar for the 3 solutions. Even
if the DTMOS FD-SOI solution has 20% less power switches
because can drive 25% more current than classical FD-SOI
solution ; the wake-up time is defined by the controller which
provides a current on VDDI maintaining a constant ramp on
VDDI rise, for VDD > 0.7V in FD-SOI and VDD > 0.8V for BULK.
3. Conclusion
In conclusion, a power switch solution is mandatory with
low-Vt logic. The FD-SOI DTMOS power switch solution, for
same equivalent Ron and wake-up time, outperforms the
classical FD-SOI solution, leading to 20% less area and 40% of
leakage reduction. Compared to BULK at same speed, Ioff is
divided by 35. This solution has been validated on silicon
through a circuit designed using an industrial design flow.
 figure 4 : Unitary power switch Ron of the 3 solutions at 30C in typical

figure 1 : BULK and FD-SOI PMOS & Conventional and Flip well configuration

figure 5 : Power switch Ioff current of the 3 solutions at 30C in typical

figure 2 : Power switch library description

figure 6 : Power switch wake-up time of the 3 solutions at 30C in typical

[1] N. Planes, et al. 28nm FDSOI Technology Platform for High-Speed

Low-Voltage Digital Applications Symposium on VLSI, 2012
[2] J.P. Noel, et al. Multi-VT UTBB FDSOI Device Architectures for Low-
figure 3 : Schematic and Layout views of Classical and DTMOS FD-SOI power
Power CMOS Circuit TED, vol.58, n8, 2011
switch extended Body Bias connection
[3] S. Mutoh, et al. 1-V power supply high-speed digital circuit technology
with multithreshold-voltage CMOS, IEEE J. Solid-State Circuits, 1995
LDPC @ same Classical Classical DTMOS [4] J. Le-coz, et al. Power Switch Optimization and Sizing in 65nm PD-SOI
speed BULK (ref) FD-SOI FD-SOI Considering Supply Voltage Noise, ICICDT, 2010
[5] P. Flatresse, et al. Ultra Wide Body Bias Range LDPC decoder in 28nm
Iddq (LDPC) 1 2 (same LDPC) UTBB FDSOI Technology ISSCC, 2013
[6] A. Valentian & E. Beign Automatic Gate Biasing of an SCCMOS Power
Ioff (PS) 1 21 35 Switch Achieving Maximum Leakage Reduction and Lowering Leakage
Area (PS) 1 1 -20% Current Variability JSSCC, vol.43, n7, 2008
[7] F. Assaderaghi, et al. A dynamic threshold voltage MOSFET (DTMOS)
Dynamic Power for very low voltage operation, IEEE Electron Device Letters, 1994
1 -49% (same LDPC)
(LDPC) [5] [8] J. Le-coz, et al. Comparison of 65nm LP Bulk and LP PD-SOI with
table 1: Sum-up of DTMOS FD-SOI advantages vs Classical FD-SOI and BULK Adaptive Power Gate Body Bias for an LDPC Codec ISSCC, 2011

978-1-4799-1361-9/13/$31.00 2013 IEEE