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R-S Flip-Flop
Reset Q
Reset Q
* This is a race condition and not stable, as for the non-clocked RS FF.
The D Flip-Flop
(S+) S
D
Q
Clock+
R Q
D
(R+)
Clocked D Flip-Flop
D Input
p
1
Clock
0
D
1
Clock
0
Time
Master-Slave, or Delay Flip-Flops
It is often desirable to have a flip-flop whose output does not
change immediately when its internal state is altered from set
(Q=1) to reset (Q=0), or vice-versa.
This sort of ff is called a master-slave or delay ff.
The idea behind the master slave ff is to have a master
master-slave master (i.e.,
controlling) ff change states on one edge of a clock pulse (normally
the leading edge) and have a second ff connected to the first
change to the same state as the master on the trailing edge, or
backside of a clock pulse.
In this way, the internal state of the ff changes one-half clock cycle
prior to the time in which the changed state appears on the circuit
outputs.
11
The Master-Slave D Flip-Flop
D
Q
Clock+
Q
Master Slave
D
Q
Clock+
Q
Master Slave
Slave FF (Q)
M t FF (Q)
Master
D
1
Clock
0
D Flip-Flop Symbols
Flip-flop detail is not usually shown in diagrams. D Q
One symbol for a D FF is shown to the right.
C
There is no small circle on either input. Therefore,
1 is the active state (when clock and D = 1, output Simple D FF
will 1).
D FFs with asynchronous set and reset are also
available. D
S
Q
Circles on S and R inputs mean that set and reset are
CR Q
negative-true signals (active at level 0).
Q-not output is also available.
D FF With
Set and reset have the same p problems discussed Asynchronous S/R
before: If S = R = 0, output may be indeterminate.
The J-K Master-Slave Flip-Flop
Q
Clock
J-K Master-Slave Flip Flop
6
JK Flip Flop Truth Table
1 3
J Q
K
2
4 Q
Clock
Inputs Outputs AND Outputs OR Outputs New Outputs
J K Q Q 1 2 3 4 Q Q
0 0 0 1 0 0 0 1 Same Same
0 0 1 0 0 1 1 0 Same Same
0 1 0 1 0 0 0 1 Same Same
0 1 1 0 0 0 0 1 0 1
1 0 0 1 1 0 1 0 1 0
1 0 1 0 1 0 1 0 Same Same
1 1 0 1 1 0 1 0 1 0
1 1 1 0 0 0 0 1 0 1
The Toggle Flip-Flop
J
T Q
K
Q
Clock
T Master-Slave Flip-Flop
The T FF is like a JK FF with J and K tied together (K input inverted).
Then if T = 1, and clock = 1, the ff toggles to the opposite state.
If T = 0,, the ff does not change
g state on the clock tick.
The T FF is a master-slave ff; output changes on the back edge of the clock.
Set T = 1 permanently, and the T FF toggles on every clock pulse.
Note Q ttieded to the
t e K input
put aand
dQQ-not
ot ttied
ed to tthee J input.
put. Thiss feedback,
eedbac ,
along with the connected J and K inputs, enables the T FF to work properly.
Toggle Flip Flop Truth Table
T 1 3
Q
2
4
Q
Clock
T FF #3
T FF #2
T FF #1
1
Clock
0
Timing (Continued)
1
f/8
Clock
f/2 f/4 Pulse Out
C
Clock ffrequency = f
1 2 3 f/8
Clock
f/2 f/4 Pulse Out
T FF #3
T FF #2
T FF #1
Clock 1
0
We know that the output of FF #1 clocks FF#2, and so-on, for
number 3.
On the first falling edge of the clock,
clock FF #1 toggles.
toggles On the falling
edge of the Q output of FF #1, FF #2 toggles, etc.
22 s
Timing (Concluded)
1
1 2 3 f/8
Clock
f/2 f/4 P l Out
Pulse O t
Pulse
T FF #3
T FF #2
T FF #1
1
Clock
0
With the signals plotted, we look for the time when the output of
clock and the three Qs are high.
We then diagram Pulse Out based on the AND of the 4 signals.
Flip Flop Summary
1 2 3 f/8
Clock
f/2 f/4 Pulse Out
T FF #3
T FF #2
T FF #1
1
Clock
0
Flip-Flop Circuits
Frequency Divider as Ripple Counter
1 Count
MSB
f/2 f/4 f/8
Clock ((at
LSB
frequency f)
Consider a variation of the T FF frequency divider.
The three Q outputs become counter digits.
digits The f/8 ff is the most
significant bit (MSB), f/2 the least significant bit (LSB).
The outputs of the ffs represent the binary value of the number of
clock pulses up to 77. Every eight pulses
pulses, the counter starts over.
over
This is a ripple counter, since each stage of the counter must
first change to its new state (which takes a small amount of time)
before it can be the clock
clock for the next stage.
stage It counts modulo
modulo-
8 since it counts 0-7 over and over again.
T FF Counter
1 Count
MSB
f/2 f/4 f/8
Clock (at
LSB
frequency f)
T FF #1 LSB
1
Clock 1 2 3 4 5 6 7 0
Flip-Flop Circuits
Problems with the Binary Ripple Counter
While the so-called ripple counter works well and dependably in
many situations, it has some problems associated with its name.
The chief problem is that the Q output of each T FF acts as the
clock for the next stage of the counter.
This means that there is some delay due to the circuit parameters
after the clock has set and reset the LSB before the output will
change and clock the next stage.
Each
c sstage
ge adds
dds another
o e set
se of
o delays
de ys too thee process.
p ocess.
For a very large counter (with many stages), the delays could get
so serious that the final stage was not clocked until after the clock
to the LSB had started the next clock cycle.
y
Actual Counting Cycle with Ripple Counter
T FF #3 000 001 010 011 100 101 110 111 MSB
T FF #2
T FF #1 LSB
1
Clock 1 2 3 4 5 6 7 0
The real-time cycle of a ripple counter is shown above.
Each succeeding stage is further delayed from the input clock.
By the time the counting pulses get to the third T FF, the delay
may be 1/2 of the original clock cycle!
We will see a solution to this ripple problem in the next lecture.
Flip-Flop Circuits
Exercise 2
Least Bit y Bit x
Significant
Digit Most
Clock Significant
Digit
Reset