IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 08 | February 2017

ISSN (online): 2349-784X

A Double-Tail Comparator with Reduced Delay

and Low Power Dissipation
Anika Kuchhal Prakash Chandra Joshi
M. Tech. Student Assistant Professor
Department of Electronics & Communication Engineering Department of Electronics & Communication Engineering
Galgotiya College of Engineering, Greater Noida, India Galgotiya College of Engineering, Greater Noida, India

Abstract
A decrease in technology demands circuit which consumes low power and gives less delay while working. Considering this in
mind we proposed a new double-tail comparator which gives digital signal when analog signal is applied as input .A proposed
comparator is made up of power gating technique, which reduces power consumption in circuit by shutting down of current in
unnecessary blocks when there is no need of that part in working. Test structures of the comparators, designed in TSMC180 nm
are measured to determine offsetvoltage, power - dissipation and speed. These are compared and the superior features of the
proposed comparator are established.
Keywords: Double-Tail Comparator, Dynamic Clocked Comparator, High-Speed Analog-To-Digital Converters (ADCS),
Low-Power Analog Design
________________________________________________________________________________________________________

I. INTRODUCTION

The schematic symbol and basic operation of a voltage comparator are shown in fig1.1 The comparator can be thought of as a
decision making circuit.

Definition

Fig. 1: Voltage comparator

The comparator is a circuit that compares an analog signal with another analog signal or reference and outputs a binary signal
based on the comparison.
If the +, VP, the input of the comparator is at a greater potential than the -, VN, input, the output of the comparator is a logic 1,
where as if the + input is at a potential less than the input, the output of the comparator is at logic 0.
GND Vo Vp Vn VDD
VP < VN then VO = VSS= logic 0.
VP >VN then VO = VDD= logic 1.

Comparator Operation
What is meant here by an analog signal is one that can have any of a continuum of amplitude values at a given point in time .In
the strictest sense a binary signal can have only one of two given values at any point in time, but this concept of a binary signal is
too ideal for real-world situations, where there is a transition region between the two binary states. It is important for the
comparator to pass quickly through the transition region. The comparator is widely used in the process of converting analog
signals to digital signals. In the analog-to-digital conversion process, it is necessary to first sample the input. This sampled signal
is then applied to a combination of comparators to determine the digital equivalent of the analog signal. In its simplest form, the
comparator can be considered as a 1-bit analog-digital converter. The presentation on comparators will first examine the
requirements and characterization of comparators. It will be seen that comparators can be divided into open-loop and
regenerative comparators. The open-loop comparators are basically op amps without compensation. Regenerative comparators

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use positive feedback, similar to sense amplifiers or flip-flops, to accomplish the comparison of the magnitude between two
signals.
The rest of this paper is organized as follows. Section II investigates the operation of the conventional clocked regenerative
and the pros and cons of structure is discussed. The proposed comparator is presented in Section III. Section IV Simulation
results are addressed in Section. Followed by conclusions in Section Section V.

II. CLOCKED REGENERATIVE COMPARATORS

Conventional Double-Tail Dynamic Comparator

Fig. 2: Conventional Double-Tail Dynamic Comparator

Fig. 3: Schematic diagram of the dynamic comparator

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 A Double-Tail Comparator with Reduced Delay and Low Power Dissipation
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Fig. 2.1 demonstrates the schematic diagram of the proposed dynamic double-tail comparator. Due to the better performance
of double-tail architecture in low-voltage applications, the proposed comparator is designed based on the double-tail structure.

Operation of the Double-Tail Dynamic Comparator

The operation of the proposed comparator is as follows. During reset phase (CLK = 0, Mtail1 and Mtail2 are off, avoiding static
power), M3 and M4 pulls both fn and fp nodes to VDD, hence transistor Mc1 and Mc2 are cut off. Intermediate stage transistors,
MR1 and MR2, reset both latch outputs to ground.
During decision-making phase (CLK = VDD , Mtail1 , and Mtail2 are on), transistors M3 and M4 turn off. Furthermore, at
the beginning of this phase, the control transistors are still off (since fn and fp are about VDD). Thus, fn and fp start to drop with
different rates according to the input voltages. Suppose VINP > VINN, thus fn drops faster than fp, (since M2 provides more
current than M1). As long as fn continues falling, the corresponding pMOS control transistor (Mc1 in this case) starts to turn on,
pulling fp node back to the VDD; so another control transistor ( Mc2 ) remains off, allowing fn to be discharged completely.
In other words, unlike conventional double-tail dynamic comparator, in which Vfn/fp is just a function of input transistor
transconductance and input voltage difference, in the proposed structure as soon as the comparator detects that for instance node
fn discharges faster, a pMOS transistor ( Mc1 ) turns on, pulling the other node fp back to the VDD. Therefore by the time
passing, the difference between fn and fp ( Vfn/fp) increases in an exponential manner, leading to the reduction of latch
regeneration time Despite the effectiveness of the proposed idea, one of the points which should be considered is that in this
circuit, when one of the control transistors (e.g., Mc1 ) turns on, a current from VDD is drawn to the ground via input and tail
transistor (e.g., Mc1 , M 1, and Mtail1), resulting in static power consumption. To overcome this issue, two nMOS switches are
used below the input transistors.

Fig. 4: Transient simulations of the double-tail dynamic comparator for input voltage difference of Vin = 5 mV, Vcm = 0.7 V, and VDD = 0.8
V.

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 A Double-Tail Comparator with Reduced Delay and Low Power Dissipation
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III. PROPOSED DOUBLE-TAIL DYNAMIC COMPARATOR

Fig. 5: Schematic diagram of the proposed dynamic comparator

Operation of proposed is same as dynamic double-tail comparator. But for further reduction in parameter such as power delay
pdp energy we analysis the circuit and apply power gating technique.

Fig. 6: Power gating technique

In power gating technique we establish our compotator circuit in-between two sleep transistor. One at upper side and one at
lower side which gives virtual Vdd and ground rasp to circuit. For this purpose upper pmos transistor is given by negative clk
while lower transistor is driven by clk. rest of the operation of proposed comparator is same as dynamic double tail-comparator

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 A Double-Tail Comparator with Reduced Delay and Low Power Dissipation
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Fig. 7: Transient simulations of the proposed double-tail dynamic comparator for input voltage difference of Vin = 5 mV, Vcm = 0.7 V, and
VDD = 0.8 V

IV. SIMULATION RESULTS

In order to compare the proposed comparator with the conventional and double-tail dynamic comparators, all circuits have
been simulated in a 0.18-m CMOS technology with VDD = 0.8V.
Table - 1
Performance Comparisons
Parameters Based Paper Double -Tail Comparator New Double-Tail Comparator
Technology 180nm 180nm
Applied Voltage 0.8v 0.8v
Power(nw) 904.58 761.48
Delay(outp)(ns) 1.1577 0.8811
Delay( outn) (ns) 1.1280 0.8749
PDP( outp) (fJ) 1.0472 0.6710
PDP (outpn) (fJ) 1.204 0.6662
Energy(fJ) 72.36 60.91

V. CONCLUSION

In this paper we proposed a novel design of double-tail comparator with power gating technique. Power gating technique turn off
transistor when there is no use of that transistor while operation. Proposed comparator is used in ADC to compare two analog
signals and to give digital signal as output. Proposed designs are simulated using TSMC 180 nm technology, simulation give
15% reduction in power, 20% reduction in delay.

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