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HomeELECTRONICSVLSI/VHDL/VerilogDSPApplicationsAnEfficientVLSIArchitectureofaReconfigurablePulseShapingFIRInterpolationFilterforMultistandardDUC2015

AN EFFICIENT VLSI ARCHITECTURE OF A RECONFIGURABLE PULSE-SHAPING FIR

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INTERPOLATION FILTER FOR MULTISTANDARD DUC 2015
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DSPApplications February3,2017

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An Efficient VLSI Architecture of a Reconfigurable PulseShaping FIR

InterpolationFilterforMultistandardDUC2015
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Abstract:
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This brief proposes a twostep optimization technique for designing a
reconfigurableVLSIarchitectureofaninterpolationfilterformultistandarddigital Re: An Efficient VLSI Architecture of a Reconfigurable PulseShaping FIR Interpolation
up converter (DUC) to reduce the power and area consumption. The proposed
Message
technique initially reduces the number of multiplications per input sample and
additionsperinputsampleby83%incomparisonwithindividualimplementation
of each standards filter while designing a rootraisedcosine finiteimpulse
responsefilterformultistandardDUCforthreedifferentstandards.Inthenextstep,a2bitbinarycommonsubexpression(BCS)based
BCS elimination algorithm has been proposed to design an efficient constant multiplier, which is the basic element of any filter. This
technique has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with 36% improvement in
operating frequency over a 3bit BCSbased technique reported earlier, and can be considered more appropriate for designing the
multistandardDUC.

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