Digital Logic Design, EE Department, Wah Engineering College

EXPERIMENT NO. : 14

(a) Introduction to Combinational Circuit Modeling Using the

Verilog Hardware Description Language
(b) Implementation of basic and universal gates using Verilog

Objective:
This laboratory assignment introduces the Verilog Hardware Description Language
(HDL) and shows you how to model and simulate basic combinational circuits. HDLs,
such as, Verilog, are used extensively in the process of designing and implementing
digital computer hardware.

Theory:

Verilog:
Verilog is a great low level language. Structural models are easy to design and
Behavioral RTL code is pretty good. The syntax is regular and easy to remember. It is the
fastest HDL language to learn and use. However Verilog lacks user defined data types
and lacks the interface-object separation of the VHDL's entity-architecture model.

History of Verilog:

Verilog was started initially as a proprietary hardware modeling language by

Gateway Design Automation Inc. around 1984. It is rumored that the original language
was designed by taking features from the most popular HDL language of the time, called
Hilo, as well as from traditional computer languages such as C. At that time, Verilog was
not standardized and the language modified itself in almost all the revisions that came out
within 1984 to 1990.

Verilog simulator was first used beginning in 1985 and was extended substantially
through 1987. The implementation was the Verilog simulator sold by Gateway. The first
major extension was Verilog-XL, which added a few features and implemented the
infamous "XL algorithm" which was a very efficient method for doing gate-level
simulation.

The standard, which combined both the Verilog language syntax and the PLI in a
single volume, was passed in May 1995 and now known as IEEE Std. 1364-1995.

After many years, new features have been added to Verilog, and the new version
is called Verilog 2001. This version seems to have fixed a lot of problems that Verilog
1995 had. This version is called 1364-2001.
 Digital Logic Design, EE Department, Wah Engineering College

VHDL
VHDL is good for designing behavioral models and incorporates some of the
modern object oriented techniques. It's syntax is strange and irregular, and the language is
difficult to use. Structural models require a lot of code that interferes with the readability
of the model.
C++:
C++ as an hardware modeling language is excellent choice for high-level
behavioral analysis of a system (like evaluating different data flow architectures in a
microprocessor). However C++ lacks the basic hardware concepts like knowledge of
strengths, connections, and concurrent execution which complicates model generation for
lower level simulations.

Verilogs View of Digital Hardware

Verilog provides the capability to design a digital system in a modular fashion.

Entire systems can be viewed as being composed of multiple individual modules. A
Verilog module is a system block with well defined
1. Input signals, say x1, x2. . . xn,
2. Output signals, say y1, y2. . . ym, and
3. Internal structure and connections or behavior.
Combinational circuits (CCs) produce output signals based on the value of their current
input signals. A CC can have any number of input variables (input signals).

Verilog modules, Ports and wires:

Module components can be simple logic gates or they can be instances of other
modules. Module components are interconnected by wires. Wires represent the actual
conductors connecting the output of a gate to the input of another.

The port list of a module is the interface between the module and its environment.
In this example, the ports are the inputs and outputs of the circuit. The port list is
enclosed in parentheses, and commas are used to separate elements of the list. The
statement is terminated with a semicolon (;). Next, the keywords input and output
specify which of the ports are inputs and which are outputs. Internal connections are
declared as wires. The circuit in this example has one internal connection, at terminal w1,
and is declared with the keyword wire. The structure of the circuit is specified by a list of
(predefined) primitive gates, each identified by a descriptive keyword (and, not, or). The
elements of the list are referred to as instantiations of a gate, each of which is referred to
as a gate instance. Each gate instantiation consists of an optional name (such as G1, G2,
etc.) followed by the gate output and inputs separated by commas and enclosed within
parentheses. The output of a primitive gate is always listed first, followed by the inputs.
For example, the OR gate of the schematic is represented by the or primitive, is named
G3, and has output D and inputs w1 and E. (Note: The output of a primitive must be listed
first, but the inputs and outputs of a module may be listed in any order.) The module
description ends with the keyword endmodule. Each statement must be terminated with a
semicolon, but there is no semicolon after endmodule.
 Digital Logic Design, EE Department, Wah Engineering College

The waveforms of the input signals are abstractly modeled (generated) by Verilog
statements specifying waveform values and transitions. The initial keyword is used with
a set of statements that begin executing when the simulation is initialized; the signal
activity associated with initial terminates execution when the last statement has finished
executing. The initial statements are commonly used to describe waveforms in a test
bench. The set of statements to be executed is called a block statement and consists of
several statements enclosed by the keywords begin and end. The action specified by the
statements begins when the simulation is launched, and the statements are executed in
sequence, left to right, from top to bottom, by a simulator in order to
provide the input to the circuit. Initially, A, B, C = 0. (A, B, and C are each set to 1b0,
which signifies one binary digit with a value of 0.) After 100 ns, the inputs change to
A, B, C = 1. After another 100 ns, the simulation terminates at time 200 ns. A second
initial statement uses the $finish system task to specify termination of the simulation.

Boolean Expressions:
Boolean equations describing combinational logic are specified in Verilog with a
continuous assignment statement consisting of the keyword assign followed by a
Boolean expression. To distinguish arithmetic operators from logical operators, Verilog
uses the symbols (&), (/), and (~) for AND, OR, and NOT (complement), respectively.

The logic of a module can be described in any one (or a combination) of the
following modeling styles:

Gate-level modeling using instantiations of predefined and user-defined primitive

gates.
Gate-level (structural) modeling describes a circuit by specifying its gates and
how they are connected with each other.
The circuits are modelled by specifying the internal structure of the block. It is
common to directly use the most primitive building-blocks available, such as, logic gates,
or larger blocks which have already been defined elsewhere. Verilog provides NOT, OR,
XOR, NAND, XNOR, NOR gates, among others. Verilog allows each logic gate to have
any valid number of inputs.

For example
or or1( z, x1, x2, x3, x4 );
and and1( x1, a, b );
and and2( x2, a, c );
not not1(na, a);
not not2(ne, e);
and and3( x3, na, d );
and and4( x4, ne, d );

Dataflow modeling using continuous assignment statements with the keyword

assign.
Behavioral modeling using procedural assignment statements with the keyword
always.
 Digital Logic Design, EE Department, Wah Engineering College

Dataflow modeling is used mostly for describing the Boolean equations of

combinational logic. Behavioral modeling is used to describe combinational and
sequential circuits at a higher level of abstraction. Combinational logic can be designed
with truth tables, Boolean equations, and schematics.
Dataflow modeling of combinational logic uses a number of operators that act on
binary operands to produce a binary result. Verilog HDL provides about 30 different
operators. It is necessary to distinguish between arithmetic and logic operations, so
different symbols are used for each. The plus symbol 1+2 indicates the arithmetic
operation of addition; the bitwise logic AND operation (conjunction) uses the symbol &.
There are special symbols for bitwise logical OR (disjunction), NOT, and XOR. The
equality symbol uses two equals signs (without spaces between them) to
distinguish it from the equals sign used with the assign statement. Dataflow modeling
uses continuous assignments and the keyword assign. A continuous assignment is a
statement that assigns a value to a net. The data type family net is used in Verilog HDL to
represent a physical connection between circuit elements

Behavioral descriptions use the keyword always, followed by an optional event

control expression and a list of procedural assignment statements. The event control
expression specifies when the statements will execute. The target output of a procedural
assignment statement must be of the reg data type. Contrary to the wire data type,
whereby the target output of an assignment may be continuously updated, a reg data type
retains its value until a new value is assigned.
Writing a Simple Test Bench:
A test bench is an HDL program used for describing and applying a stimulus to an
HDL model of a circuit in order to test it and observe its response during simulation. Test
benches can be quite complex and lengthy and may take longer to develop than the
design that is tested. The results of a test are only as good as the test bench that is used to
test a circuit. Care must be taken to write stimuli that will test a circuit thoroughly,
exercising all of the operating features that are specified. However, the test benches
considered here are relatively simple, since the circuits we want to test implement only
combinational logic. The examples are presented to demonstrate some basic features of
HDL stimulus modules. In addition to employing the always statement, test benches use
the initial statement to provide a stimulus to the circuit being tested. We use the term
always statement loosely. Actually, always is a Verilog language construct specifying
 Digital Logic Design, EE Department, Wah Engineering College

how the associated statement is to execute (subject to the event control expression). The
always statement executes repeatedly in a loop. The initial statement executes only once,
starting from simulation time 0, and may continue with any operations that are delayed
by a given number of time units, as specified by the symbol #.
initial
begin
A 0; B 0;
#10 A 1;
#20 A 0; B 1;
end

The block is enclosed between the keywords begin and end . At time 0, A and B are set
to 0. Ten time units later, A is changed to 1. Twenty time units after that (at t 30 ), A is
changed to 0 and B to 1.
The response to the stimulus generated by the initial and always blocks will appear in
text format as standard output and as waveforms (timing diagrams) in simulators having
graphical output capability. Numerical outputs are displayed by using Verilog system
tasks. These are built-in system functions that are recognized by keywords that begin
with the symbol $ . Some of the system tasks that are useful for display are
$displaydisplay a one-time value of variables or strings with an end-of-line return,
$writesame as $display, but without going to next line,
$monitordisplay variables whenever a value changes during a simulation run,
$timedisplay the simulation time,
$finishterminate the simulation.

Example:

// Verilog model of above Figure.

module Simple_Circuit (A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;
and G1 (w1, A, B); // Optional gate instance name
not G2 (E, C);
or G3 (D, w1, E);
endmodule

The first line of text is a comment (optional) providing useful information to the
reader. The second line begins with the keyword module and starts the declaration
(description) of the module; the last line completes the declaration with the keyword
 Digital Logic Design, EE Department, Wah Engineering College

endmodule. The keyword module is followed by a name and a list of ports. The name
(Simple_Circuit in this example) is an identifier. Identifiers are names given to modules,
variables (e.g., a signal), and other elements of the language so that they can be
referenced in the design. In general, we choose meaningful names for modules.
Identifiers are composed of alphanumeric characters and the underscore (_), and are case
sensitive. Identifiers must start with an alphabetic character or an underscore, but they
cannot start with a number.

MODEL SIM
Model sim is used to design the circuits .Here we dicuss the work of model sim.
Creating a project to create a project in Model Sim, select File > New > Project.... A Create
Project window will appear.

The create project window consists of several fields: project name, project location, default library
name, and copy settings field. Project name is a user selected name and the location is the directory where
the source files are located.
 Digital Logic Design, EE Department, Wah Engineering College

Compiling a Project

Once the project has been created, it is necessary to compile it. Compilation in
ModelSim checks if the project files are correct and creates intermediate data that will be
used during simulation. To perform compilation, select Compile All from the Compile
menu. When the compilation is successful, a green check mark will appear to the right
of the serial.vhd file in the Project tab.

Simulation:

To begin a simulation of the design, the software needs to be put in simulation

mode. To do this, select simulate > Start simulation.
 Digital Logic Design, EE Department, Wah Engineering College

PART (B)
(a) Implementation of basic and universal gates using Verilog

Verilog code for AND GATE

Verilog code for OR GATE

Verilog code for NOT GATE

Verilog code for NAND GATE

 Digital Logic Design, EE Department, Wah Engineering College

Verilog code for NOR GATE

Comments:

Conclusion: