Digital Logic Design

Course code: EEE241 (3+1)

Prerequisites: None

Co requisites: None

Course Catalog Description:

Introduction to Digital Computer and Systems, Number Systems, Binary Arithmetic, Boolean Algebra,
Algebraic Manipulation, Canonical and Standard Form & Conversions, Logical Operations and Gates,
Simplification of Functions, Karnaugh Map Methods, Two Level Implementations, Dont Care Conditions,
Prime Implicants, Combinational Logic Design, Arithmetic Operations and Circuits, Analysis Procedures,
Multilevel NAND/NOR Circuits, Decoders, Encoders, Multiplexers, Demultiplexers, Memory Types, Read
Only Memory, Random Access Memory, Programmable Logic Array (PLA), Sequential Logic, Flip-Flops,
Clocked Sequential Circuits, State Machine Concept, Design of Sequential Circuits using State Machines,
Counters and their Design, Synchronous Counters, Asynchronous Counters, Shift Registers etc.

Textbook:

1. M. Morris Mano & Charles R. Kime, Logic and Computer Design Fundamentals (2nd Edition
Updated, Prentice Hall, 2000)

Reference Books:

1. Thomas L. Floyd, Digital Fundamentals (7th Edition)

Course Learning Objectives:

Overall Educational Objective: The student will develop the ability to design both combinational and
sequential digital logic circuits. He will learn to design with common library hardware components.

Course Learning Outcomes:

After successfully completing this course, the students will be able to:

1. Describe number system, basic logic gates, boolean algebra and basic properties of boolean algebra.
(C1-PLO1)
2. Explain the correlation between Boolean expression and their corresponding logic diagrams. (C2-
PLO1)
3. Simplify and optimize simple logics using basic boolean properties and Karnaugh Maps. (C3-PLO1)
4. Analyze and design combinational circuits (C5-PLO3)
5. Realize basic sequential circuit and perform analysis of Sequential logic circuits using different
types of flip-flops (C4-PLO2)
6. Design Sequential logic circuits using different types of flip-flops. (C5-PLO3)
7. Illustrate and design sequential components used in typical digital Systems: Adder, Subtracters,
Registers, Shifters, Comparators, counters etc. (C5-PLO3)
8. Understand and use HDL/Proteus/Multisim to implement combinational and sequential circuits.
(C3/C4-PLO5)
9. Work as a team to build semester projects (C5-PLO9)
Course Schedule:

3 credit hours/week
One laboratory session/week (3 hours/session)

Topics Covered:

1. Introduction to digital system and different number systems, Binary arithmetic (3 lectures)
2. Boolean algebra, Axioms of boolean algebra (2 lectures)
3. Simplification of logic circuits using K-maps, Product of sum simplification, dont care condition,
NAND & NOR implementation. (3 lectures)
4. Combinational logic, Binary multiplier & magnitude comparator, Decoder & encoder, MUX &
DEMUX. (6 lectures)
5. Latches & Flip-Flops, Characteristic tables, state equations, diagrams, clocked sequential circuits. (2
lectures)
6. Analysis of D, JK, T-Flip flops, Mealy & Moore models, State reduction. (4 lectures)
7. Design of clocked sequential using Flip-Flops. (2 lectures)
8. Registers, shift registers, universal shift registers, Ripple counters, synchronous counters, Registers
with parallel load, shift registers, Universal shift registers. (6 lectures)
9. Introduction to ROM, PAL, PLA, CPLD ROM Designing. (3 lectures )

Assessment Plan:

Theory Quizzes (minimum 4) 15%

Homework assignments (minimum 4) 10%
2 Sessional exams (in class, 60-80 minutes each, 10%+15%) 25%
Terminal exam (3 hours) 50%
Total (theory) 100%
Lab work Lab reports (12) 25%
2 Lab sessionals 25%
Lab project and terminal exam 50%
Total (lab) 100%
Final marks Theory marks * 0.75 + Lab marks * 0.25
Learning Outcomes Assessment Plan (Tentative):

Sr. # Course Learning Outcomes Assessment

1. 1,2 Assignment 1
2. 4 Assignment 2
3. 5 Assignment 3
4. 6-7 Assignment 4
2. 1 Quiz 1
5. )4 Quiz 2
7. 5 Quiz 3
9. 6 Quiz 4
3. 1-3 Sessional 1
8. 3-5 Sessional 2
11. 1-7 Terminal

Table 1 Tentative Assessment Plan for Course Learning Outcomes

Computer Resources:
CircuitMaker software is used for building simple digital circuits covered in this course. Proteus/Multisim
is used for designing and analysis of logic circuits. MSI circuit is used to design moderately complex
digital circuits. However, main emphasis is to build the digital circuits on hardware platforms available in
the lab.

Laboratory Resources:
VLSI / Microprocessor / DLD Labs in Z block of the campus are used for DLD lab experiments. They
contain work benches equipped with oscilloscopes, power supplies, function generators digital
multimeters. Electronic kits are available to perform lab assignments according to the designed lab
manual.
Mapping Course Learning Outcomes (CLOs) to Program Learning Outcomes (PLOs):

PLO 1 Engineering Knowledge: An ability to apply knowledge of mathematics, science,

engineering fundamentals and an engineering specialization to the solution of
complex engineering problems.
PLO 2 Problem Analysis: An ability to identify, formulate, research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences and engineering sciences.
PLO 3 Design/Development of Solutions: An ability to design solutions for complex
engineering problems and design systems, components or processes that meet
specified needs with appropriate consideration for public health and safety, cultural,
societal, and environmental considerations.
PLO 4 Investigation: An ability to investigate complex engineering problems in a
methodical way including literature survey, design and conduct of experiments,
analysis and interpretation of experimental data, and synthesis of information to
derive valid conclusions.
PLO 5 Modern Tool Usage: An ability to create, select and apply appropriate techniques,
resources, and modern engineering and IT tools, including prediction and modeling,
to complex engineering activities, with an understanding of the limitations.
PLO 6 The Engineer and Society: An ability to apply reasoning informed by contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to professional engineering practice and
solution to complex engineering problems.
PLO 7 Environment and Sustainability: An ability to understand the impact of professional
engineering solutions in societal and environmental contexts and demonstrate
knowledge of and need for sustainable development.
PLO 8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of engineering practice.
PLO 9 Individual and Team Work: An ability to work effectively, as an individual or in a
team, on multifaceted and /or multidisciplinary settings.
PLO 10 Communication: An ability to communicate effectively, orally as well as in writing, on
complex engineering activities with the engineering community and with society at
large, such as being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear
instructions.
PLO 11 Project Management: An ability to demonstrate management skills and apply
engineering principles to ones own work, as a member and/or leader in a team, to
manage projects in a multidisciplinary environment.
PLO 12 Lifelong Learning: An ability to recognize importance of, and pursue lifelong learning
in the broader context of innovation and technological developments.
 PLOs PLO PLO PLO PLO PLO PLO PLO PLO PLO PLO PLO PLO
1 2 3 4 5 6 7 8 9 10 11 12
CLOs

CLO 1 C1

CLO 2 C2

CLO 3 C3

CLO 4 C5

CLO 5 C4

CLO 6 C5

CLO 7 C5

CLO 8 C4

CLO 9 C5

Table 2: Mapping CLOs to PLOs

PLO Coverage Explanation:

PLO 1 - Engineering Knowledge:
The boolean conversion, sequential circuits designing, project design, homework, exams and studies
require direct application of mathematics, scientific, and engineering knowledge to successfully
complete the course. This includes logical simplification, arithmetic Boolean calculations, hardware
implementation, circuit analysis, project design and implementation.

PLO 2 - Problem Analysis:

Students become eligible to analyze basic gates and simple logic circuits which will help them in the
design of higher complex digital systems.

PLO 3 - Design/Development of Solutions:

The course shows the value of theory, by making it possible for the students to solve relevant
engineering problems. The design process along with simplification techniques and hardware
implementation drives the students towards solving real problems in an efficient way.

PLO 5 - Modern Tool Usage:

The MSI circuit, CircuitMaker, Proteus/Multisim simulation tools are introduced and used in the class
and are extensively used for implementation of digital circuits before hardware level
implementations.

PLO 4, 6-8, 10-12: These PLOs are not directly addressed in this course.
 ANNEXURE-I
Tentative Lecture Breakdown (30 Lectures):
Topic Week

Digital Computers and Information Week 1 - 2

Digital computers and Binary Numbers
Other base numbers (base-8, base-16 etc.)
Number base conversions
1s and 2s Complements
Unsigned and Signed numbers and Arithmetic operations (Addition, subtraction,
Multiplication and Division)

COMBINATIONAL LOGIC CIRCUITS Week 2 - 4

Binary Logic and Introduction to Logic Gates
Timing Diagrams
Introduction to Boolean Algebra
Standard forms
Positive and Negative Logic
Boolean Functions and their implementation
Canonical and Standard Forms (Minterms, Maxterms, Conversions)
Minimization of Boolean functions using K-Map
Don't Care States
Universal gates and implementation of Boolean functions using universal gates

COMBINATIONAL LOGIC DESIGN Week 5-6

Combinational Circuits
Analysis Procedure
Design Procedure
Decoders
Encoders
Multiplexers / Demultiplexer
Binary Adders (Half Adder, Full Adders, Binary Ripple Carry Adder, Carry Look
ahead Carry Adder)

COMBINATIONAL LOGIC DESIGN Week 6-7

Binary Subtractor
Binary Adder/Subtractor
Binary Multipliers
Code Conversion
Magnitude Comparator
Parity Generators/ Checkers
Design Applications

SEQUENTIAL CIRCUITS Week 8 - 11

Introduction to Sequential Circuits
Introduction to Latches
Introduction to Flip Flops
Type of Flip Flops
Analysis of Sequential Circuits
Design Procedures
Introduction to develop state diagram and state table
State reduction excitation tables
 ANNEXURE-I
REGISTERS AND COUNTERS Week 12 - 13
Registers
Counters
Synchronous/Asynchronous
Shift Registers
Serial Shift Registers

REGISTERS AND COUNTERS Week 13 - 14

Loading Registers
Parallel Registers
Ripple Counters
Synchronous Binary Counters
Other Counters

MEMORY AND PROGRAMMABLE LOGIC DEVICES Week 15 - 16

Read-Only Memories
Programmable Logic Array Devices
Random Access Memory
Static and Dynamic RAM
Array of RAM ICs
Memory construction using RAM Integrated Circuits

Course review Week 16

 ANNEXURE-II
List of Experiments:

Lab # Details

01 DLD Trainer and Proteus Software

Introduction to basic logic gates (use and practice AND, OR, NOT)
02 Universal gates (use and practice NAND, NOR, XOR, XNOR)

03 Construct XOR using NAND

04 Boolean Algebra

05 Subtractors

06 Comparator

07 Lab Sessional + Viva + project proposal

08 Multiplexer

09 Demultiplexer

10 Decoders

11 7-Segment display, BCD to 7 segment

12 Encoders

13 Flip flops (D,JK,T)

14 Lab sessional 2 + Viva + project evaluation.

15 Shift registers
Asynchronous counters

16 Lab Project / Viva