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Chapter 1
iout 2rmR1/R3
1.1-6. 5
iin R 1 R1 2 rm
v2 gmRL v1 1
1.1-7. 5 5 RL 1
v1 1 1 gmRL i1 gm
vout 2R2
1.1-8. 5
vin R1
vout 2rmR3
1.1-9. 5
vin R1R2 1 R1R3 1 R1rm 1 R2R3
vout 2gmR1R2R3
1.1-10. 5
vin R1 1 R2 1 R3 1 gmR1R3
1.1-12. Rin 5 5 M
727
728 HOMEWORK PROBLEM ANSWERS
Chapter 2
3e 1/3
2.2-3. xp 5 2xn 5 a b (0 2 VD)1/3
2qa
2.2-5. BV h 58.27 volts
v2DS
c (vGS 2 VT0) vDS 2 (1 1 a) d
WnCox
2.3-3. iD 5
L 2
2.3-5. For tox 5 210 : VT0 5 0.331 V
For tox 5 200 : VT0 5 0.306 V (Example. 2.3-1 result)
The difference is 25 mV.
Also Rpoly 5 R 5 252 3 50 5 12.6 k and CMOS 5 6308 m2 3 2 fF/m2 5 12.6 pF
1
(b) Maximum 23dB frequency 5 5 1.6MHz
2(0.7)(12.6k)(0.9)(12.6pF)
1
Minimum 23dB frequency 5 5 0.7MHz
2(1.3)(12.6k)(1.1)(12.6pF)
2.4-5. VOUT 5 1.22713 V
2.4-8. R 5 150
1 dvD
2.5-1. 5 2.775 3 1023
vD dT
Chapter 3 729
Chapter 3
W
3.1-5. iD 5 K (vGS 2 VT)2[1 1 (vDS 2 vDS (sat))], 0 , (vGS 2 VT) # vDS
2L
3.2-1. Off: CGB 5 11.3 fF, CGS 5 1.1 fF, and CGD 5 1.1 fF
Saturation: CGB 5 0.575 fF, CGS 5 7.868 fF, and CGD 5 1.1 fF
Nonsaturation: CGB 5 0.574 fF, CGS 5 6.18 fF, and CGD 5 6.18 fF
3.2-2. NMOS: CBX(0) 5 5.2 fF and CBX(20.75 V) 5 4.07 fF
PMOS: CBX(0) 5 4.31 fF and CBX(10.75 V) 5 3.425 fF
3.2-3. The device is in saturation; therefore, CGB 5 0.575 fF, CGS 5 7.868 fF, and CGD 5 1.1 fF.
3.2-4. (a) RD 5 RS 5 7.95 V 1 0.2 V 5 8.15 V, (b) CBD 5 CBS 5 176 fF, (c) W 5 22 m and L
5 2 m, and (d) CGD 5 4.8 fF
3.2-5. |p1| 5 835.7 kHz
vout(s) 1
3.3-1. 5
vin(s) s
11
13.77 3 109
3.3-2. WM2 5 592 m
3.3-3. Example 3.3-1, NMOS: gm 5 332 S, gmbs 5 40.4 S, and gds 5 0.5 S
Example 3.3-1, PMOS: gm 5 224 S, gmbs 5 38.2 S, and gds 5 0.5 S
Example 3.3-2, NMOS: gm 5 1.1 mS, gmbs 5 134 S, and gds 5 3.28 mS
Example 3.3-2, PMOS: gm 5 500 S, gmbs 5 85.2 S, and gds 5 1.428 mS
3.3-4. gm 5 1.12 mS, gmbs 5 136 S, gds 5 0.0228 S, CGB 5 0.575 fF, CGS 5 15.8 fF, and CGD 5
2.2 fF
1
3.3-5. ID(TOTAL) 5 (vGS 2 vT)2 (1 1 vDS)[
Wi]
L
i
3.3-6. LEQUIVALENT 5 o0 Li
W
3.5-3. ID 5 2K [n(kT/q)]2
L
3.6-1. Part (a)
Problem 3.6-1 (a)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Part (b)
Problem 3.6-1 (b)
M1 2 1 0 0 nch W=1u L=1u
M2 2 3 4 4 pch w=1u L=1u M=2
M3 3 3 4 4 pch w=1u L=1u
R1 3 0 50k
Vin 1 0 dc 1
Vdd 4 0 dc 5
.MODEL nch NMOS VTO=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
.MODEL pch PMOS VTO=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
.op
.end
Chapter 4
L2COX(5 2 VS 2 VT) 21
4.1-12. W2 5 W1 a2 1 b
CGDO (VS 1 VT)
Design L2 to be the minimum allowed device length and calculate W2.
4.1-13. Error due to charge injection is 116 V.
4.1-14. RON 5 1606 ohms. Loss 5 28.32dB. The bridge switch dissipates more power, has higher
ON resistance, and couples more signal during the OFF phase than the single switch.
1
4.2-1. RAB 5 In general, for the same-size transistors, Fig. P4.2-1 will be more linear
2(VC 2 VT)
than Fig. 4.2-3.
1 2iD 1 1
4.5-4. Iout 5 I 5 2
R E K E (W/L)1 E (W/L)2
Chapter 5
5.1-7. Active load inverter: Rout 5 14.14 kV, Av 5 22.097 V/V, and f23dB 5 10.9 MHz
Current source inverter: Rout 5 222.22 kV, Av 5 232.93 V/V, and f23dB 5 0.697 MHz
Pushpull inverter: Rout 5 222.22 kV, Av 5 248.63 V/V, and f23dB 5 0.697 MHz
5.1-8. Av 5 2170.9 V/V (ID 5 0.1 A), Av 5 270.27 V/V (ID 5 5 A), and Av 5 215.71 V/V (ID 5 100 A)
5.1-9. VGG 5 2.05 V, Vin 5 3.406 V, Av 5 224.85 V/V, and f23dB 5 2.51 MHz
5.1-10. f23dB 5 1.102 MHz, e
ni 5 6.277 nV/ 2Hz
5.1-11. (a) Circuit 5 has the highest gain. (b) Circuit 4 has the lowest gain (assuming normal values
of gm/gmb). (c) Circuits 5 and 6 have the highest output resistance. (d) Circuit 1 has the low-
est output resistance.
5.1-12. Av 5 243.63 V/V, and f23dB 5 283.36 kHz
5.1-13. Active area of active load inverter 5 4546 m2, active area of current source load inverter 5
4.64 m2, and active area of pushpull load inverter 5 2.55 m2.
5.1-14. Av 5 243.63 V/V, Rout 5 55.55 kV, and f23dB 5 286.5 kHz
5.2-1. (a) gm 5 104.8 S and Av 5 23.31 V/V. (b) gm 5 331.4 S and Av 5 36.82 V/V.
5.2-2. (a) gm 5 70.71 S and Av 5 15.7 V/V. (b) gm 5 223.6 S and Av 5 24.84 V/V.
IDD IDD
5.2-3. VIC (max) 5 VDD 2 ZVT1Z 2 2
E KP(W1/L1) E KP(W5/L5)
IDD
VIC(min) 5 VSS 2 ZVT1Z 1 VT3 1
E KP(W1/L1)
5.2-4. VIC(max) 5 4.86 V, VIC(min) 5 0.93 V, and ICMR 5 3.93 V
5.2-5. Av 5 233.1 V/V, and f23dB 5 7.16 kHz
5.2-6. Rout 5 2.22 kV, Av 5 104.1 V/V, VIC(max) 5 2.184 V, and VIC(min) 5 1.2147 V
5.2-7. ISS 5 10 A: gmd 5 23.36 S and Av 5 249.69 V/V. ISS 5 1 A: gmd 5 7.07 S and Av 5
2157.11 V/V.
5.2-8. SR 5 0.1 V/s (ISS 5 10 A) and SR 5 0.01 V/s (ISS 5 1 A)
5.2-9. Avcm < 0.02 V/V
5.2-10. Av 5 0.74V/V
vo 1
5.2-11. 52 if gmrds >> 1
vic (gm32rds5)
ISS
5.2-12. VG1(max) 5 VDD 1 VT1 2 VT3 1
E KP(W/L)3
ISS 2ISS
VG1(min) 5 VT1 1 1
E K N (W/L)1 E K N (W/L)5
734 HOMEWORK PROBLEM ANSWERS
1 gm1gm2 0.5gm2
2 5
gds2 1 gds8 (gm1 1 gm2)(gds2 1 gds8) gds2 1 gds8
1 gm1 1 gm2
3
gds2 1 gds8 2(gds2 1 gds8)
1 gm6 (gm1 1 gm2)gm6
4 5
gds6gds8 gds6 gds8 1 gm6gds2 2(gm6gds2 1 gds6gds8)
gds2 1
gm6
gm4gm6 (gm1 1 gm2)gm4gm6
5
gds2gm6gds4 1 gm6gds4gds8 2(gds2gm6gds4 1 gm6gds4gds8)
5.2-16. eeq 5 1.567 nV/ 2Hz and ito 5 164 fA/ 2Hz
gm1 a0.25 2 b
gds1
gm3
5.2-17. vs1 5 vid
a0.75gm1 1 gds1 a2 2 b 2 gds5 b
gm1
gm3
The value of vs1 is nonzero because the loads (M3 and M4) seen by the input transistors (M1
and M2) at their drains are different.
5.2-18. (a) v1(max) 5 2 V and v1(min) 5 0.9302 V. (b) ICMR 5 1.07 V. (c) Av 5 149.8 V/V. (d) f23dB
5 111.4 kHz.
gm1 2 2
5.2-19. e eq
2
5 4 e nl
2
1 2a b e n6
gm6
5a ba b
v3 20.5gm1 sC2 1 gm5 1 gm6 2gm1
5.2-20. as s 0
vin sC1 1 Gout sC2 1 gm6 gds1 1 gds5
v3
5 273.69 V/V, p1 5 24.5 3 106 rad/s, p2 5 2223.6 3 106 rad/s, and z1 5 2447.2 3 106
vin
rad/s
vout 2KN(W/L)1 2 2
5.2-21. 52 and Rout 5 5
vin E IBIAS( 1 1 3)2 (gds1 1 gds3) IBIAS( 1 1 3)
5.2-22. VIC(min) 5 VT1 1 Vdsat1 1 Vdsat5, VIC(max) 5 VDD, and VDD 5 2Vdsat 1 VT1
5.2-23. SR 5 ISS/(2CL) for capacitive load. SR 5 ISS/CL for resistive load.
Chapter 5 735
5.3-1. Av 5 220 V/V. From the transfer characteristics, the small-signal gain is approximately 210 V/V.
5.3-2. Hint: Assume that VGG2 2 VT2 is greater than vDS1 and express Eq. (5.3-4) as iD2 < 2(VGG2
2 VT2)vDS2. Solve for vOUT as vDS1 1 vDS2 and simplify accordingly.
3
(VDD 2 VGG3 2 ZVT3Z)2 c d (1 1 3 VDD)
1 1
5.3-3. Vout(min) 5 2
21 VDD 2 VT1 VGG2 2 VT2
gm3rds3rds4
5.3-4. RS2 5 5 rds
gm2rds2
5.3-14. Choose ID3 5 ID2 5 ID1 5 25 A. The maximum output swing gives W3/L3 5 W4/L4 5 1.
From the gain we get W1/L1 5 3. The minimum output swing gives W2/L2 5 1. Therefore,
VGG2 5 1.76 V and the power dissipation is 0.125 mW.
vo R2/R1
5.4-1. 5
vs 1 1 (1/Ai)
5.4-2. W2 5 10 m and L2 5 1 m, Rin 5 6.74 kV and Rout 5 25 kV
5.4-3. Ai(0) 5 0.988, Rin 5 2796 V, Rout 5 250 kV and f23dB 5 973 MHz
vx gds3 1 gds4
5.4-4. Rin 5 <
ix gm1gm3
3.25
5.4-5. Rin 5 and Rout < rdsP
gmN2rdsN
vx
5.4-7. Rin 5 < gm1rds1gm3rds3rds2
ix
vx 1
5.4-8. Rin 5 < . Plot iout 5 2iin.
ix g m3 m4rds3
g
rds1 1 rds2
1 1 gm2rds(gm3 1 gm4)rds3 7 rds4
5.4-9. Rin 5
5.5-9. (a) Circuit 5 has the highest voltage gain. (b) Circuit 4 has the lowest voltage gain. (c) Circuit
6 has the highest output resistance. (d) Circuit 1 has the lowest output resistance. (e) Circuits
2, 4, and 6 have the highest output swing. (f) Circuits 1, 3, and 5 have the lowest output
swing.
V2DD
2RL
5.5-10. 5 which is /4 when VDD2VSS 5 VDD/2
V2DD
(VDD 2 VSS)a b
RL
a b a bZVT2Z
K P W2 L1
VT1 2
E K N L2 W1
5.5-11. VBias 5
a ba b
K P W2 L1
12
E K N L2 W1
VDD
5.5-13. Vout(max) 5
1
11
W2
KP Rl(VSS 2 VDD 1 VTR2 1 ZVT2Z)
L2
VSS
Vout(min) 5
1
11
W1
KN RL(2VSS 1 VDD 1 VTR2 2 ZVT2Z)
L1
5.5-14. Set up a means for monitoring the output sinking and sourcing current and then connect this
current through the drain of a transistor to the drain of an opposite-type transistor whose cur-
rent is fixed at the short-circuit limit. Use the voltage between these drains to ground to drive
a circuit that will protect the sinking (M2) and sourcing (M3) transistors.
Rout 5 c d 7 RL
2 2
5.5-15. Rout 5 and
gm1 1 gm2 gm1 1 gm2
738 HOMEWORK PROBLEM ANSWERS
5.5-16.
Fig. 5.2-1 Fig. 5.3-1 Fig. 5.3-6 Fig. 5.5-1 Fig. 5.5-3b
Chapter 6
vout R2
6.1-1. 511
vin R2
vS
6.1-2. vin 5 where vin 5 input to op amp, vS 5 external input signal, f 5 feedback factor, and
1 1 fAv
Av 5 differential voltage gain of the op amp. As Av , then vin 0.
6.1-3. Use the definitions to show that vout 5 Acmvcm.
6.1-6. The gain in the circuit is already at the level of a two-stage op amp. The gain could easily be
increased by making the W/L ratio of M7 to M4 and M6 to M5 greater than one.
6.2-2. The actual phase margin is 51.83 compared to 45 estimated from the Bode plot.
6.2-7. The RHP zero occurs because there are two paths from the gate of M6 to the drain and at
some value of the complex variable, s, these paths will cancel, giving a zero. The RPH zero
has a stronger influence on MOSFETs because gmMOS < gmBJT.
6.2-8. (a) p2 5 214.2 3 106 rad/s. (b) PM 5 71.7 (c) PM 5 34.4.
6.2-10. W1/L1 5 10 and W6/L6 5 12.33
6.2-11. (a) Rz 5 2 kV, p1 5 24,444 rads/s, p2 5 2100 3 106 rad/s, and p4 5 2500 3 106 rad/s.
(b) Rz 5 2.33 kV, p1 5 24,444 rad/s, and p4 5 2429 3 106 rad/s.
6.3-1. I5 5 20 A, I6 5 125.66 A, W1 5 W2 5 7.17 m, W3 5 W4 5 10 m, W5 5 20 m, W6 5
125.66 m, and W7 5 125.66 m
Noise Worse but not by much because Better but degraded by the lower
the first-stage gain is higher first-stage gain
Phase margin Poorer (gmI larger but gmII smaller) Better
Gain bandwidth Larger (GB 5 gmI/Cc) Smaller
Vicm(max) Larger Smaller
Vicm(min) Smaller Larger
Sourcing output current Large Constrained
Sinking output current Constrained Large
Chapter 6 739
gm1gm6
6.3-14. Av 5
(gds2 1 gds4)(gds6 1 gds7)
6.3-16. The compensation capacitor, CC, is removed from the op amp when the output voltage is high
because M10 is off. This is due to the fact that the drain-source voltage of M10 is the same
as the output and the gate is connected to VDD. M10 needs to be moved to the right of CC or
paralleled with a PMOS connected to VSS or both.
6.4-2. PSRR1 5 1737 V/V, PSRR2 5 2171 V/V, p1 5 172.4 kHz, z1 5 11.6 MHz, and z2 5 p2
5 6.2 MHz.
6.4-3. Fig. P6.4-3 has a PSRR1 that is approximately Cgd/Cc less than Fig. 6.4-2(a).
21
5 c d
vout 2gmIgmII GI(gds6 2 gds7 2 gm7)
6.4-4. and z1 < .
vground GI(gds6 2 gds7 2 gm7) Cc(GI 1 gm6 2 gm7 1 gds6 2 gds7)
The two poles are the same as given by the zeros of Eq. (6.4-14) in the text.
6.5-1. VBIAS 5 1.3 V, R 5 12.65 kV, and Av 5 26248 V/V.
6.5-2. WB1/LB1 5 WB2/LB2 5 WB3/LB3 5 WB4/LB4 5 1 and WB5/LB5 5 0.25. I5 5 110 A
740 HOMEWORK PROBLEM ANSWERS
6.5-3. (a) RC1 < gmC1 and RC2 < rds. (b) RC1 < gmC1 and RC2 < gmC2.
6.5-4. W1/L1 5 W2/L2 514.5 m/1 m
6.5-5. Av 5 22620 V/V
6.5-6. I5 5 250 A and W6 5 W7 5 W3 5 W4 5 W8 5 40
6.5-7. Rout 5 11.11rdsN and Av 5 18,518 V/V
6.5-8. Rout 5 20 rdsN and Av 5 100,000 V/V
6.5-9. ICMR 5 Vin(max) 2 Vin(min), where
I7 2I7
Vin(max) 5 VDD 1 VT1(min) 2 1
E K N(W3/L3) E K N(W5/L5)
I7 2I7
Vin(min) 5 VSS 1 VT1(max) 2 1
E K N(W1/L1) E K N(W7/L7)
W1/L1 5 W2/L2 5 64 m/10 m, and W3/L3 5 W4/L2 5 135 m/10 m
8K NK P(W1/L1)(W8/L8) 1
6.5-10. Av 5 and Rout 5
E I7I9( P 1 P)2 2P gds8 1 gds9
2
6.5-11. Rout 5 0.2gmNrdsN and Av 5 2000 V/V if k 5 1
6.5-12. pout 5 25000 rad/s, pA < pB < 2416.7 Mrad/s, p6 < 2909 Mrad/s, p8 < 2181.2 Grad/s,
and p9 < 2909 Mrad/s
Chapter 7
7.1-1. W18/L18 5 13.5, W19/L19 5 4.9, W21/L21 5 10.5, and W22/L22 5 55.
7.1-2. VA 5 0.9 V, VB 5 1.0 V, and VC 5 0.1 V
vout 2gm1gm4
7.1-5. 5
vin gm2gm4 2 (gm3 1 gds4)(gds1 1 gds2)
7.1-6. Rout 5 67.3 V and f23dB 5 236 MHz
7.1-7. Rout 5 294.5 V, f23dB 5 10.81 MHz, max/min output 5 1 V, and Pdiss 5 3.9 mW
7.1-8. In a bulk CMOS p-well (n-well) technology, npn (pnp) BJTs (both substrate and lateral) are
available. The advantage of using a BJT in a Class A output is a reduced output resistance.
The disadvantages include unsymmetrical drive and limited output current.
1 1
7.1-9. Rout > 1 and Rout 5 1152 V
gm10 (1 1 F)gm9
7.1-10. p1 5 284.3 Mrad/s, p2 5 223.32 Mrad/s, and z1 5 2614 Mrad/s. Neither p1 nor p2 is greater
than 10GB if GB 5 5 MHz, so they will deteriorate the phase margin of the amplifier of
Example 7.1-2.
7.1-11. I1 5 I2 5 I3 5 I2 5 60 A, I5 5 120 A, I6 5 I7 5 40 A, IQ1 5 2 A and IQ2 1 I9 5 200
A. Av 5 532.2 V/V and Rout 5 287.4 V.
7.2-1. GB 5 26.79 MHz and Cc 5 18.66 pF
7.2-2. GB < 0.23p6
7.2-3. PM 5 16
7.2-4. GB 65 MHz and CL 1.54 pF
W1 W2 W5 W6
7.2-5. 5 50, 5 5.6, 5 50.5, and 5 5.6
L1 L2 L5 L2
7.2-6. pin 5 2466 MHz and pout < 250 MHz
7.2-7. Rin 5 1076 V, Rout 5 636V, and f23dB 5 13.87 MHz.
7.2-8. R1 5 1/gm13
7.3-1. Fig. 7.3-3 Fig. 7.3-5 Fig. 7.3-6 Fig. 7.3-8 Fig. 7.3-11
7.3-2. 0.5RL
7.3-3. For Fig. P7.3-3(a) Av 5 3673 V/V, and for Fig. P7.3-3(b) Av 5 9117 V/V
7.3-4. Avd < (gm2rds2)/4 and rout < rds/2
7.3-5. Avd < (gm2rds2)/2 and rout < rds/2
7.3-6. Avd < (gm2rds2)/6 and rout < 2(gmrds2)/3
7.3-7. Avd < (gmrds)/2 and rout < rds
7.3-8. Avd < (gm2rds2)/2 and rout < 2(gmrds2)/3
7.3-9. Avd < (gm2rds2)/2 and rout < (gmrds2)
7.3-11. (a) CMFB LG 5 2111.8 V/V. (b) CMFB LG 5 23290 V/V
gmC2gm4
7.3-12. ZLGZ 5
2gmC5 a b
gds4gds6 gds8gds10
1
gm4 gm10
The compensation of the common-mode feedback loop can be done using the output load
capacitor (single-ended load capacitors to ac ground).
7.3-13. Avd < (gm3rds3)/6 and rout < 2(gmrds3)/3
7.3-14. Avd < (gm2rds2)/3 and rout < 2(gmrds2)/3
7.4-1. Av(0) 5 19,508 V/V, GB 5 61.43 kHz, SR 5 0.05 V/s, and Pdiss 5 1.35 W
7.4-2. Av(0) 5 73,846 V/V, GB 5 122.5 kHz, SR 5 0.1 V/s, and Pdiss 5 0.9 W. W15/L15 5 2.02
and W13/L13 5 0.7.
7.4-3. vin /nVt 5 0.908
7.4-4. W2 /L2 5 100 and Vds2 5 7 mV
7.5-1. Veq < 10 nV/ 2Hz
7.5-2. fc 5 150.4 kHz and Veq(rms) 5 4.45 V for a 100 kHz bandwidth
14.72 310212 2
7.5-3. e2eq(1/f) 5 V /Hz, e2eq(Thermal) 5 2.42 310217 V2/Hz,
f
fc 5 608 kHz and Veq(rms) 513.1 nV/2Hz
7.5-4. Veq(rms) 5 75.5 V
7.5-5. Veq(rms) 5 55.73 V
7.6-1. VDD 5 0.671 V
7.6-2. VDD 5 0.411 V
7.6-3. VDD 5 0.711 V
7.6-4. Vonn 5 1.578 V and Vonp 5 0.57 V
Chapter 8 743
7.6-7. Interchange IVBE and IPTAT in Fig. 7.6-16(a). Add the two correction terms, INL and K3INL1, to
the uncorrected IVBE 1 K1IPTAT to achieve the desired temperature compensation.
7.6-8. p2 5 220 MHz, p6 5 21.2 GHz, and p3 5 2101 MHz. GB = 58 MHz and Cc 5 2 pF.
7.6-9. ICMR 5 0.9 V
7.6-10. ICMR 5 0.8 V
Chapter 8
8.1-3. tp 5 500 ns
8.1-4. Vin > 100.05 mV
8.2-1. VOH 5 2.43 V; VOL 5 2VSS 5 22.5 V
Vin(min) 5 1.5 mV; p1 5 1.074 MHz; p1 5 0.67 MHz
8.2-2. Slew rate should be greater than 36.79 V/ms
8.2-3. When Vin 5 10 mV, k 5 15.576 and tp 5 35.8 ns
When Vin 5 100 mV (assuming no slewing), k 5 155.76 and tp 5 11.3 ns
When Vin 5 1 V (assuming no slewing), k 5 1557.6 and tp 5 3.58 ns
8.2-5. VTRP 5 1.89 V; VTRP(max) 5 3.22 V; VTRP(min) 5 0.39 V
8.2-6. The total propagation delay is 133.2 ns.
8.2-7. The total output fall time is 79.8 ns, and the total output rise time is 9.5 ns; thus, the total prop-
agation time delay of the comparator is 44.7 ns.
8.2-8. tfo1 5 6 ns; tr, out 5 2.36 ns; tp1 5 8.36 ns; tro1 5 27.3 ns
tf, out 5 131.6 ns; tp2 5 158.9 ns
The average propagation delay is 83.63 ns.
8.2-9. (W/L)6 5 120; (W/L)7 5 55; (W/L)1 5 (W/L)2 5 12; (W/L)5 5 16; (W/L)3 5 16 5 (W/L)4
8.2-10. (a) tp 5 0.513 s, (b) tp 5 0.100 s, and (c) tp 5 0.100 s
8.2-11. tp 5 125 ns
8.2-12. (W/L)1 5 (W/L)2 5 4.5; I5 5 30 mA
Vdsat5 5 0.2 V, thus (W/L)3 5 (W/L)4 5 15
(W/L)7 5 31.5, (W/L)6 5 210, and I7 5 210 mA
VTRP2 5 23.1 V
tfo1 5 15 ns; tr, out 5 2.4 ns; tp1 5 17.4 ns; tro1 5 35 ns
tf, out 5 21.4 ns; tp2 5 56.4 ns
The average propagation delay is 36.9 ns, which is well below 1000 ns.
744 HOMEWORK PROBLEM ANSWERS
8.3-1. tp 5 20 ns
8.3-2. |p1| 5 10318 rps. The maximum slope is 0.77 V/s and since the SR 5 20V/s, the compara-
tor does not slew. The propagation delay time is tp 5 3.3 s.
8.3-3. The total gain is 5.052 3 109 V/V and tp 5 57.5 ps.
8.3-4. SR2 5 216 V/s and SR 1 5 48.4 V/s
8.4-1. T 5 0.47 s; as t vout (t) 5 0.999 VOS
8.4-2. R2 5 2R1 5 200 k; VREF 5 2/3 V
8.4-3. R2 5 R1 5 100 k
8.4-4. ZLGZ 5 22.6
8.4-5. R2 5 3R1 5 200 k; VREF 5 0 V
1 2
8.4-6. VTRP 5 0.215 V; VTRP 5 20.215 V
8.4-7. There are two possibilities that could account for the differences. The first is due to the sim-
ple Sah model, which does not model the saturation voltage very well. This voltage is the
point at which transistors make the transition from active to saturation and is an important part
of the development of the trip points. The second is the neglect of the bulk effects on transis-
tors M1 and M2.
8.5-2. The NMOS latch would be faster because it has a larger small-signal loop gain.
8.5-3. For Vin 5 0.01(VOH 2 VOL), tp 5 422 ns
For Vin 5 0.1(VOH 2 VOL), tp 5 174 ns
8.5-4. For Vin 5 0.01(VOH 2 VOL), tp 5 188 ns
For Vin 5 0.1(VOH 2 VOL), tp 5 76.8 ns
Fig. 8.5-3 Work with smaller power supply Class A outputcant source an
sink with the same currentslow
Fig. 8.5-8 Pushpull is good for sinking and Needs larger power supply
sourcing a lot of currentfast
8.6-1. (a) The closed-loop gain is 225. Thus, the 23 dB bandwidth becomes for 2 3 dB 5 400
krad/s.
(b) The closed-loop gain is 25. Thus, the 23 dB bandwidth becomes for 2 3 dB 5 2000
krad/s.
8.6-2. Av 5 6.6 V/V; p1 5 5.15 MHz
8.6-3. Av 5 6.873 V/V; f23dB 5 2.62 MHz
8.6-4. The minimum delay is 20.08 ns and if it is achieved then x 5 1/8.
8.6-5. tp 5 t1 1 t2 5 3.13 ns 1 16.095 ns 5 19.226 ns
8.6-6. tp 5 t1 1 t2 5 1.131 ns 1 0.916 ns 5 2.047 ns
8.6-7. tp 5 t1 1 t2 5 3.16 ns 1 1.477 ns 5 4.637 ns
Chapter 9
9.1-4. INL: 11LSB, 22.5LSB, DNL: 11.5LSB, 22LSB. The converter is not monotonic.
9.1-5. SNR 5 54 dB
9.1-6. Rms noise 5 21.6 mV; fractional temperature coefficient 5 0.3052 ppm/(C
I1 I2 I4
9.2-1. IOUT 5 IO, , ,
2 4 8
2i2N
9.2-2. (a) Tolerence of ith current sink is 3 100%
2
2i2N
(b) Tolerence of ith current sink is 3 100%
2N
7
9.2-3. (a) vout 5 3 ideal characteristic
8
VREF
(b) Gain error of 1/16 and offset of
15
(c) INL 5 10.5LSB and 21.0LSB, DNL 5 10.5LSB and 21.5LSB. This converter is not
monotonic.
9.2-4. (a) INL 5 10.5LSB and 22.0LSB, DNL 5 10.5LSB and 21.5LSB
32
(b) For 0010, R3 5 R0; for 1000, R3 5 2R0
5
9.2-5. (a) VOS 5 0.01613VREF. (b) A 56.2 V/V. (c) T 5 1.0488 s.
746 HOMEWORK PROBLEM ANSWERS
(a) FS 5 RI a1 2 b . (b) I 5
1 VREF
9.2-7.
2N
b
1
Ra1 2
2N
(c) N 5 12. (d) f 5 87.4 3 103 conversions/s.
9.2-8. Time for conversion 5 6 ms
9.2-9. DC/C 0.0488%
1
(a) vout 5 CL a 1 1 p 1 N21 1 N bVREF
b0 b1 bN22 bN21
9.2-10.
11 2 4 2 2
2C
C
(b) If CL << 2C, the error is a gain error. (c) CL .
2N
i51 i51
bi bi
9.2-11. vOUT 5 2VREF
on
2i
(b0 5 1) and vOUT 5 2VREF o2
n
i (b0 5 0)
i51
bi
vOUT 5 (VREF 2 VOS)
o2 n
i (b0 5 0)
Cx
(c) # 1.685%.
Cx
1
9.3-11. fclock 5 5 283 kHz
Tclock
vOUT (2) b1
9.3-12. 5 1 f(b2, 4) 1 f(b3, 2) 1 f(b4, 4). INL 5 13LSB and 0LSB, DNL 5 11LSB
VREF 2
and 23LSB. The converter is not monotonic.
R R
9.3-13. (a) INL(R) 5 2M21 a b LSBs and DNL(R) 5 ;2K a bLSBs
R R
C 2KC
INL(C) 5 ;2K21 a b LSBs and DNL(C) 5 a bLSBs
C C
R C
INL 5 INL(R) 1 INL(C) 5 2M21 a b 1 2N21 a b
R C
R C
DNL 5 DNL(R) 1 DNL(C) 5 2K a 1 b
R C
R
(b) INL(R) 5 2N21 a b LSBs and DNL(R) 5 a bLSBs
;R
R R
C C
INL(C) 5 ;2N21 a b LSBs and DNL(C) 5 2N a bLSBs
C C
R C
INL 5 INL(R) 1 INL(C) 5 2N21 a 1 bLSBs
R C
C R
DNL 5 DNL(R) 1 DNL(C) 5 a2N21 1 bLSBs
C R
9.3-14. The DAC combination where the MSBs are charge scaling and the LSBs are voltage scaling
gives the most bits when both INL and DNL are 1LSB. The number of bits is n 5 9 with m 5
7 bits of charge scaling for the MSB DAC and k 5 2 bits of voltage scaling for the LSB DAC.
748 HOMEWORK PROBLEM ANSWERS
2 2 V2 VREF
9.3-15. vx 5 vAnalog 2 V1 1 2 . For ABCD 5 1011 and vanalog 5 0.8VREF, the compara-
5 5 10 16
tor output will be low.
9.3-16. Errors are (1) Op amp/comparator gain, GB, SR, settling time (offset not a problem). (2)
Resistor and capacitor matching. (3) Switch resistance and feedthrough. (4) Parasitic capaci-
tances. (5) Reference accuracy and stability.
9.4-1. vC1 5 vC2 5 0.6340VREF.
9.4-2. The output voltage is 0.6340VREF.
9.4-3. Error occurs at the third bit.
9.4-4. Vout 5 0.60156VREF. For k 5 0.55, Vout 5 0.3066VREF.
9.4-6. INL 5 11LSB and 20.5LSB, DNL 5 10.5LSB and 21.5LSB. DAC is nonmonotonic.
9.4-7. INL 5 10LSB and 21.1875LSB, DNL 5 11.1875LSB and 20.8125LSB
9.4-9. 0.205 # A # 0.590
9.4-10. 0.41 # A # 0.77
9.4-11. At 4th bit conversion
9.4-12. At 4th bit conversion
9.5-1. Max DNL 5 62 LSB
9.5-2. (a) INLA 5 11LSB, 2INLA 5 21.5LSB; DNLA 5 10.5LSB, 2DNLA 5 21.5LSB
(b) INLD 5 12LSB, 2INLD 5 21LSB; DNLD 5 11LSB, 2DNLD 5 22LSB
9.5-3. (a) INL 5 13LSB and 23LSB, DNL 5 12LSB and 23LSB. (b) WC INL 5 0.5LSB.
9.5-4. N58
9.5-5. N59
9.6-1. For vinp 5 0.25VREF Clock periods 5 1.25NREF
For vinp 5 0.7VREF Clock periods 5 1.7NREF
9.7-1. 10110011
9.7-3. 1001
Chapter 9 749
9.7-4. 111001
9.7-5. 10101001
9.7-6. 10100111
9.7-7. (a) Minimum e 5 0.0178. (b) minimum VOS 5 60.2 V.
9.7-8. Error at 7th bit
9.7-9. Error occurs at 4th bit when vinp 5 0.1VREF and offset voltage 5 0.1 V
9.7-10. (a) 10001101. (b) 10001011 and the 7th bit is in error.
9.7-11. (a) # 0.0417. (b) VOS 0.2 V.
9.7-12. Error occurs in the 4th bit.
9.7-13. (a) 01001100. (b) Vanalog 5 0.296875VREF. (c) Never go smaller than 60.2VREF.
9.8-2. 1110000
9.8-3. C1 5 C/3, C2 5 C, C3 5 3C
ADC Comp. Offset Conv. Speed Accuracy Other Aspects