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HomeELECTRONICSVLSI/VHDL/VerilogCoreProjectsDesignandFPGAImplementationofaReconfigurable1024ChannelChannelizationArchitectureforSDRApplication2016

DESIGN AND FPGA IMPLEMENTATION OF A RECONFIGURABLE 1024-CHANNEL

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CHANNELIZATION ARCHITECTURE FOR SDR APPLICATION 2016
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CoreProjects February13,2017

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Design and FPGA Implementation of a Reconfigurable 1024Channel

ChannelizationArchitectureforSDRApplication2016
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Abstract:
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During this paper, we present a completely unique channelization architecture,
whichwillsimultaneouslymethod2channelsofadvancedinputinformationand Re: Design and FPGA Implementation of a Reconfigurable 1024Channel Channelizatio
provideupto1024freelancechannelsofcomplicatedoutputdata.Theproposed
Message
design is very modular and generic, therefore that parameters of each output
channelwillbedynamicallychangedevenatruntimeintermsofthebandwidth,
center frequency, output sampling rate, and therefore on. It consists of one
tunablepipelinedfrequencytransform(TPFT)basedcoarsechannelizationblock,onetuningunit,andoneresamplingfilter.Primarily
based on the analysis of the data dependence between the subbands, a completely unique channel splitting scheme is proposed to
enablemultiplesubbandstosharetheproposedTPFTblock.Themultiplierblock(MB)andsubexpressionsharingtechniquesareused
toreducethequantityofarithmeticunitsoftheTPFTblock.Moreover,theproposedFarrowprimarilybasedresamplingfilterdoesnot
need division operation and twinport RAMs ensuing in vital area saving. Finally, we have a tendency to implement the proposed
channelizationdesigninanexceedinglysinglefieldprogrammablegatearray.Theexperimentresultsindicatethatourdesignprovides
theflexibilityassociatedwiththepresentworks,howeverwithlargerresourceefficiency.

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