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Tessent ATPG DRC Debug

Student Workbook

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Part Number: 073412


Table of Contents

Module 1: Overview DRCs 4


Objectives 5
Introduction 6
ATPG Design Rule Checks (DRC) 7
ATPG Design Rule Checks (DRC) (Cont.) 8
ATPG Design Rule Checks (DRC) (Cont.) 9
A Rules (RAM/ROM Rules) 10
B Rules (BIST Rules) 11
C Rules (Clock Rules) 12
D Rules (Scan Cell Data Rules) 13
DFT_C Rules (Pre-DFT Clock Rules) 14
E Rules (Extra Rules) 15
F Rules (EDT Finder Rules) 16
FN/FP/FG Rules (Flattening Rules) 17
G Rules (General Rules) 18
I Rules (ICL Extraction Rules) 19
ICL Semantic Rules 20
K Rules (EDT TestKompress Rules) 21
P Rules (Procedure Rules) 22
R Rules (Core Mapping) 23
S Rules (Scannability Rules) 24
T Rules (Scan Chain Trace Rules) 25
V Rules (Power-Aware Rules) 26
W Rules (Timing Rules) 27
Design Rule Checks (DRC) for ATPG 28
ATPG DRCs you Should pay Attention to 29
Why Should I pay Attention to These ATPG DRCs? 30
Getting Help With Tessent Tools 31
Getting Help With Tessent Tools (Cont.) 32
Getting Help With Tessent Tools (Cont.) 33
Accessing UNIX Commands From the Tool Command Line 34
Getting Help: Useful Tool and System Commands 35
SupportNet 36
Lab 1: Using the Tessent Bookcase 37
Module 2: Debugging C, D and A Rules 38
Objectives 39
How to Debug DRCs? 40
Reporting DRC Data 41
Reporting DRC Data (Cont.) 42
Reporting DRC Data (Cont.) 43
Reporting DRC Data (Cont.) 44
Reporting DRC Data: DFTVisualizer 45
Analyzing the DRC Data 46
Analyzing the DRC Data (Cont.) 47
Analyzing the DRC Data: DFTVisualizer 48
Analyzing the DRC Data: DFTVisualizer (Cont.) 49
State Stability Analysis 50

Tessent ATPG DRC Debug


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State Stability Analysis (Cont.) 51


Adding Input Constraints Vs Forcing in Test Procedure 52
Clock and Data Rules (C, D, A) 53
Clock Rules 54
C1 Unstable Scan Cells When Clock is off 55
C1 Unstable Scan Cells When Clock is off (Cont.) 56
C1 Unstable Scan Cells When Clock is off (Cont.) 57
C6 Clock Must not Affect Data it Captures 58
C6 Clock Must not Affect Data it Captures (Cont.) 59
C7 - Scan cell Capture Ability Check 60
C7 - Scan cell Capture Ability Check (Cont.) 61
C8/C9 PO Connected to a Clock Line 62
C16 - Capture Value Disturbed due to Constraints 63
C16 - Capture Value Disturbed due to Constraints (Cont.) 64
Lab2 : Debugging Clock DRCs 65
D1 Loaded or Captured Data Disturbed 66
D1 Loaded or Captured Data Disturbed (Cont.) 67
D5/D6 Non-scan Memory Elements and Latches 68
D12 - Non-scan Memory Element Initialized By Multi-Shift Cycles 69
Lab 2: Debugging Data DRCs 70
RAM/ROM Rules 71
A1/A7 Unstable RAM cells When W/R Controls off 72
A1/A7 Unstable RAM cells When W/R Controls off (Cont.) 73
A6 Unstable RAM During Test Procedure Sim. 74
A6 Unstable RAM During Test Procedure Sim.(Cont.) 75
Lab 2: Debugging RAM DRCs 76
Module 2: Debugging Design and Trace Rules 77
Objectives 78
Debugging Design Trace & EDT Rules 79
T Rules: Scan Chain Trace Rules 80
T3/T4/T5 Scan Chain Path Tracing 81
T3/T4/T5 Scan Chain Path Tracing (Cont.) 82
Lab 3: Debugging Trace Rules 83
EDT Finder 84
EDT Finder Rules 85
EDT Finder Rules (Cont.) 86
F Rules Location 87
F5 Channel Inputs Must Drive a Decompressor 88
F8 Channel Outputs Driven by Compactor 89
F19 - Mask Hold Register not Stable 90
F19 - Mask Hold Register not Stable (Cont.) 91
F20 Verifies Masking Modes of Compactor 92
F20 Verifies Masking Modes of Compactor (Cont.) 93
F Rule Violation Common Sources and Resolutions 94
Lab 3: Debugging Finder Rules 95
K Rules TestKompress Rules 96
K Rules Location 97

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K19 - EDT Decompressor Verification 98


K19 Rule Violation Source and Resolution 99
K19 Rule Violation Source and Resolution (Cont.) 100
K22 EDT Compactor Verification 101
K22 Rule Violation Source and Resolution 102
K22 Rule Violation Source and Resolution (Cont.) 103
Lab 3: Debugging TestKompress Rules 104
E Rules Extra Rules 105
BUS Contention Check 106
E4 Conflicting Values Driving Same net 107
E4 Conflicting Values Driving Same net (Cont.) 108
E10 BUS Contention During Capture 109
E10 BUS Contention During Capture (Cont.) 110
P/W Rules -Test Procedure and Timing Rules 111
P/W Rules -Test Procedure and Timing Rules (Cont.) 112
Summary 113
Effect of DRCs 114
Lab 3: Debugging Extra Rules 115

Tessent ATPG DRC Debug