ISSN (Print) : 0974-6846

Indian Journal of Science and Technology, Vol 10(2), DOI: 10.17485/ijst/2017/v10i2/110615, January 2017 ISSN (Online) : 0974-5645

VLSI Implementation of Low Power and High Speed

Architecture of DWT-IDWT using Lifting based
Algorithm
Chetan H1 and Dr.Indumathi G2
Visvesvaraya Technological University, Jnana Sangama, Belagavi 590018, Karnataka, India;
1

Chetan.h.gowda@gmail.com
2
Cambridge Institute of Technology, SR Layout, Chikkabasavanapura, Krishnarajapura, Bengaluru 560036,
Karnataka, India; indumathi.ece@citech.edu.in

Abstract
Objective: The purpose of this study is to optimize DWT1-IDWT2 architecture for different Image Compression techniques
using lifting based algorithms. Statistical Analysis: The data in form of image and video are transmitted as signal. Because
of limited channel bandwidth the data has to be compressed and this reduces the quality of the image. An algorithmic
concept of encoding information is given by wavelets in a manner that is layered according to level of detail. The analysis of
this implementation includes speed optimization, accuracy, and power reduction. This study uses pipelined architecture of
1D-DWT architecture and is combined with another 1D-DWT module in parallel to obtain 2D-DWT architecture to analyze
the speed.Findings: The study was done using VLSI cad tools and coding was done using Verilog, by implementing the
proposed algorithm with pipelined-parallel architecture for image compression using DWT, we analyzed the timing wrt*
clock speed and we analyzed PSNR and SNR for different video and image compression techniques. Improvements: Our
study shows higher speed can be achieved by using DWT for image compression and by using VLSI architecture, the study
can be optimized to any further extent.

Keywords: Compression, DWT, IDWT, Lifting Algorithm, Low Power

*wrt: - with respect to in communication technology. Rich cellular data com-

1DWT- Discrete Wavelet Transform
2IDWT-Inverse Discrete Wavelet Transform
1. Introduction
The demand for bandwidth and storage capacity dur-
ing transmission in uncompressed multimedia devices
is high. Though currently available technologies have
shown good progress in speed, storage density and sys-
tem performance the requirements for storage capacity
transmission and bandwidth far outweighs them. Web
applications area demand for efficient encoding tech-
niques for signal compression which is also key for storage
munication is in demand for enabling high bandwidth
requirements in various data formats like voice, data,
image and video. The significant challenge in multimedia
information service is the need to process and transmit
vast information. It forces extreme requests on battery
assets of resources and transfer speed necessities of appli-
ances. Despite the fact that the data transmission change
is achievable, the battery technology wont be in standard
with the future energy prerequisites. One strategy to beat
this problem is to lessen the volume of multimedia data
transmission over wireless channel through information
compression method, for example, JPEG, JPEG 2000
and MPEG1. These methodologies focus on enhancing

*Author for correspondence

 VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm
compression without degrading quality of picture and
transmitting in a channel specified. While transmitting
data we overlook at power consumption by decreasing the
data information which is transmitted through informa-
tion compression strategy, for example, JPEG and MPEG
over the wireless channel can be one of the ways to deal
with the above issue. The focus of these methodologies is
basically without the penance of nature of picture getting
higher compression ratio. Here, handling power is addi-
tionally one of the parameters.
Figure 1. Discrete Wavelet Transform2.
The block diagram shown in Figure 1 describes the
communication system using discrete wavelet transform.
The communication system represents orthogonal fre-
quency division multiplexing which effectively increases
the spectrum efficiency. The discrete wavelet transform
used is designed without using multiplication operation
to employ the factor of speed in the whole communica-
tion system.
2. Literature Analysis
Performance of OFDM and WPM over multipath
wireless channel having WPM is compared depict-
ing utilization of time domain Minimum Mean Square
Error (MMS E) when compared with OFDM system
WPM possessing a time domain MMS E equalizer gives
higher noise immunity to NBI for multipath wireless
channels. The developments in ubiquitous connectivity
technologies and convergence of ICT-Information and
Figure 2. Wavelet - based Compression Algorithms2
2 Vol 10 (2) | January 2017 | www.indjst.org
Communication Technologies have thrown wide array
of challenges to emerging technologies and architectures
which is capable of handling huge volumes of data under
minimum constraints of bandwidth and power.
Further3 proposes Wavelet packet based FFT also;
application of Wavelet to SNR estimation is discussed.
The computed solution matches the exact results, and its
computational complexity is of same order of FFT3.
Further implementing the wavelet packets, the effects
of implementation and requirements considered in the
design of usable wavelets are studied4, also the constraints
imposed by lossless reconstruction make way for use of
bi orthogonal wavelets. But however, this affects the per-
formance. The frequency behavior of the wavelet packet
transform is complex in practical use of this transform in
a multicarrier system4. For our work, we need DWT to be
used for compression of data, hence Figure 1 shows 2D
DWT and 2D-IDWT compression algorithm.
Wavelet coding schemes are better suited for charac-
teristics of HVS (Human Visual System). Wavelet coding
methodologies when used at higher compression rate
avoids block-artifacts.
As the transformation process, can be repeatedly
applied with wavelets compression is scalable resulting in
very high compression ratios. With wavelets, parametric
gain control on sharpening and image softening is pos-
sible also, wavelet based coding scheme is robust during
transmission and error decoding. Progressive transmis-
sion of images is also feasible. Efficient compression is
achieved at low bit rates also, it facilitates for efficient
decomposition of signals prior to compression. Further
DWT is designed using Lifting scheme2, the transform
module of DWT includes two horizontal filters and two
vertical filters working in parallel and pipeline. The per-
formance analysis of the results shows that it provides
better image compression ratio with simple steps which is
suitable for VLSI implementation.
Hence in our paper for implementing we have used
lifting based CDF 5/3 DWT architecture5, proposed for
Indian Journal of Science and Technology

Figure 3. a, b Block Diagram of Lifting based Schema4.
Figure 4. Three-levels Wavelet Decomposition Tree (DWT)5.
parameterized to tackle diverse word length and picture
sizes. The model is low unpredictable due to unit blocks,
offers a simple approach for higher DWT modeling out-
comes of the 2DDWT and it can work with frequency of
198MHz.
3. Principle Method
DWT based Lifting schema is a better approach for oper-
ational speed. The principle applied is first factorizing
the polyphase matrix of a wavelet filter into a sequence
of alternating upper triangular matrices, lower triangular
matrices and a diagonal matrix. Secondly banded-matrix
multiplications are applied to implement wavelets. A.
Two Lifting schema
The Figure 3 depicts that factorization carried out
results in non-unique values, here si(z) (primary lifting
steps) and ti(z) (dual lifting steps) are filters and K is a
constant. This computation results in several si(z), ti(z)
and K values.
The Wavelet transform provides optimized time-
frequency representation of the data signal than other
existing transforms like FFT transformation6. Following
equation provides the Continuous Wavelet Transform
(CWT).
The DWT is calculated by successive low pass and
high pass filtering of the discrete time-domain signal as
shown in figure. The Low pass filter is denoted by G0
while the high pass filter is denoted by H0. At each level,
Vol 10 (2) | January 2017 | www.indjst.org
Chetan H and Dr.Indumathi G
the high pass filter produces detail information; d[n],
while the low pass filter associated with scaling function
produces rough details, a[n].
In the design of the transceiver for wavelet modula-
tion and its implementation in an AWGN channel, it has
showed that the Bit error rate with SNR in the AWGN
channel is precise. In another channel medium, it was
concluded that DWT-OFDM performs much better than
DFT-OFDM6.
4. Implementation
The architecture is developed by using Lifting scheme of
wavelet filter with value N=2. Here N=2 denotes that the
lifting scheme uses 2 stages viz. predict_1 and update_1
in first stage and predict_2 and update_2 in second stage
respectively. This scheme reduces computational com-
plexity. The Figure 5 depicts block diagram of forward
lifting scheme transforms. Here there are basically three
steps split, lifting and scaling respectively.
Input sequences are orderly split to decompose the ip
signal into even & odd. The spliced even and odd signals
are predicted and updated in accordance with the splitting
operation. In predicting stage, the predict value is selected
from the decomposed input signal; this operation is suc-
cessively iterated four times and updated inherently. In
DWT, main operation would be addition and in inverse
DWT the subtraction operation is used.
Some constants used are alpha, beta, gamma and
delta, should be rounded off. The multiplication opera-
Indian Journal of Science and Technology 3
 VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm

tion plays a major role in performing wavelet operation The lifting Scheme algorithm is applied as:
using lifting scheme. The multiplication operation inher- I. Split step
ently consumes more clock cycle with which latency
parameter would come into picture. The latency increases
by increasing the number of stages in lifting scheme. The
latency can be decreased by replacing multiplication by
shifting operation which will boost the speed of the sys- II. Lifting Steps, N=2
tem comparatively.
The prime objective of lifting scheme is to split the orig-
inal 1D signal into odd and even indexed sub sequences
and compute a trivial wavelet. Further these values are
updated with subsequent prediction and updating steps.
The lifting based scheme algorithm steps are as fol-
lows:
III. Scaling step
Splitting Stage: Split the input (main) signal X
(n) into odd and even number of samples.
Lifting Stage: Its executed in N sub stages
(depending up on the type of the filter), Here the
prediction and update filters Pn(n)and Un (n) Where a=-1.586134342, b-0.0529801185,
are used to filter odd and even samples. c=0.882911076, d=-0.443506852 and K=1.149604398.
Scaling Stage: On completion of N Lifting stage,
a scaling parameters K and 1/K are applied to the
odd and even samples respectively to obtain the
low pass band YL (i) and the high pass band YH (i).

Figure 7. Block Diagram of Lifting Based.

The Figure 7 shows the block diagram of implementa-

Figure 5. Block Diagram for Forward LDWT5.
Figure 6. Diagram of LDWT (9, 7) Filter5.
tion of DWT and IDWT. The design consists of clk and
rst as control inputs along with the data input sequences.
The input data is given to the lifting based algorithm. This
algorithm calculates DWT and IDWT. Lifting based algo-
rithm is designed using Verilog, and it consists of split,
predict and update operations and finally the data out-
put is scaled. The scaling operation is done to obtain the
constant value. The constant value represents the exact
input signal, there by verifying the design functional-
ity. The DWT implementation is performed by adding
the input sequence with the predict and update values
in the first four clock cycles whereas IDWT operation is
implemented using the subtraction operation in the next
alternate four clock cycles.

4 Vol 10 (2) | January 2017 | www.indjst.org Indian Journal of Science and Technology

The Optimized 1D-DWT architecture which is imple-
mented is as shown in Figure 8. Architecture consists of
6 shifters, 6 adders and 6 delay elements. The four adders
and four shifters are used to design low pass filter. The two
shifters and two adders are used to design the high pass
filter. Buffers are used to make zeros from negative values
filters coefficients and positive value is unchanged. D flip-
flop acts as a down sampler to generate high and low pass
filter Coefficients.
The original sequences of images size of 256x256 is
converted into low pass and high pass filter coefficients
of size 32768x1
Figure 8. O1D-DWT Architecture7.
Figure 9. O2D-DWT Architecture7.
2D-DWT is derived from 1D-DWT architecture
which is represented as shown above. Memory modules
and controller modules are added in the architecture is as
shown in Figure 9. The two-memory modules of 2DWT
are in parallel. The memory unit block is used to store
the low pass and high pass filter coefficients which are
obtained from the 1D-DWT. Memory unit-1 stores the
L band coefficients and memory unit-2stores the H band
coefficients. Both memory unit-1 and memory unit-2 are
accessed using 1D-DWT block 1 and 1D-DWT block 2
simultaneously to obtain sub bands of HH, HL, LL and
LH via MUX and DEMUX. HL and HH sub bands are
obtained from 1D-DWT block 1 and LL and LH sub
Vol 10 (2) | January 2017 | www.indjst.org
Chetan H and Dr.Indumathi G
bands are obtained from 1D-DWT block 2. The control-
ler module is optimized in terms of using (i) The low pass
and high pass filters are designed using shifters and addi-
tion operations. (ii) The architecture does not use any
multiplier which builds speed and decrease equipment
complexity. (iii) The four subgroups are implemented in
parallel.
A. Parallel Processing Memory Unit
The low pass and high pass coefficients of O1D-DWT are
put away in two squares of memory units as indicated in
fig 10 which is utilized to acquire transposition of info
picture. The LPF signal output and HPF signal output of
O1D-DWT squares are associated with parallel handling
memory unit through the signals Data in1 and Data in2
individually. The clock signal clk and clk_div are utilized
to peruse and compose the coefficients from both mem-
ory units at the same time. The clk_out of O1DDWT
square is utilized as info to clk_ div signal for memory
unit. The control signals like rd addr, wr addr, rd wr,
clk and clk_div are chosen by MUX. The memory unit is
utilized to change over O1D-DWT into O2D-DWT with
the assistance of control unit. The LPF and HPF coeffi-
cients are passed in parallel by utilizing clk and clk_div
as a part of memory-1 and memory-2 which expands the
rate compared with existing technique in which coeffi-
cients are handled in serial.
Figure 10. Memory Unit8.
Figure 11. Controller Architecture8.
Indian Journal of Science and Technology 5
 VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm

B. Proposed Controller Unit The above snapshot illustrates the output results of
The controller unit is utilized to peruse coefficients of DWT and IDWT lifting based algorithm. The output
rows and columns of network. The controller unit com- signal values X8, X9....X15 of IDWT obtained is shown
prises of three counters which are utilized for creating in the Figure 13.
read and compose locations demonstrated in the Figure
11 to get filter coefficients. The counter-1 performs com-
pose operation by resetting rd, wr control signal to
zero. The counter-2 and counter-3 are utilized to peruse
the filter coefficients from the memory by setting rd,
wr control signal to one. The counter-2 is incremented
for each 256 count of counter-3 to read column matrix
of coefficients. The counter-2 number will proceed till it
achieves 128 checks to get all the picture coefficients.

5. Results Figure 14. Input Values to DWT Block in Waveform for

The below figure illustrates the input signal given to the Lifting Based Algorithm DWT-IDWT using Shift Operator.
Lifting DWT Whose input signal values are taken in 3-bit
binary form. X0, X1, X2, X3 ... X7 are the input signals
shown in the Figure 12.

Figure 15. Output Values of DWT Block and Input Values

for IDWT Block in Waveform for Lifting Based Algorithm
Figure 12. Input Waveform Results for Lifting Based DWT-IDWT using Shift Operator.
Algorithm DWT using Multiplication Operator.

Figure 16. Output Values of IDWT Block in Waveform for

Figure 13. Waveform Results for Lifting Based Algorithm
Lifting Based Algorithm DWT-IDWT using Shift Operator.
DWT-IDWT using Multiplication.

6 Vol 10 (2) | January 2017 | www.indjst.org Indian Journal of Science and Technology

Figure 17. Input Values to IDWT Block in Waveform for
Lifting Based Algorithm IDWT-DWT using Shift Operator.
Figure 18. Output Values of IDWT Block and Input Values
of DWT Block in Waveform for Lifting Based Algorithm
IDWT-DWT using Shift Operator.
Figure 19. Output Values DWT Block in Waveform for
Lifting Based Algorithm IDWT-DWT using Shift Operator.
The comparison of PSNR, MSE of different video for-
mat is shown in the Figure 20 and Figure 21. HD video
has high PSNR compare to all other video formats. 3GP
video has less compare to all and reverse in case of MSE
the percentage of threshold co-efficient comparison of
Haar and CDF technique for different threshold which
are set is shown in the graph is also shown in the below
figures.
Vol 10 (2) | January 2017 | www.indjst.org
Chetan H and Dr.Indumathi G
Figure 20. PSNR of Different Video Format8.
Figure 21. MSE of Different Video Format8.
Figure 22. Percentage of Co-efficient Threshold between
Haar and CDF8.
6. Conclusion
The Optimized 2D DWT algorithm was basically used
for image compression technique and has provided
a better compression ratio but here in the proposed
architecture it has high compression ratio for the high
bit rate data and the quality of the data matrix is also
not lost after the compression. Only adders and shifters
were used to develop the FIR filters in the 02D-DWT
architecture so it reduces the memory and area space
required during the hardware implementation and
speed is increased due to parallel architecture and with
usage of shifters. The entire concept still has scope of
further extending the application to the image process-
Indian Journal of Science and Technology 7
 VLSI Implementation of Low Power and High Speed Architecture of DWT-IDWT using Lifting based Algorithm
ing domain for higher compression ratio requirement
by using highly parallel DWT architecture.
7. Acknowledgement
This research was supported by C M R Institute of
Technology. We thank Naveen H for assistance for
comments and paper building and improving the final
manuscript. We would also like to show our gratitude to
the Dr. B. Narasimha Murthy, Vice Principal, CMRIT for
guiding us and giving valuable insights during this paper.
8. References
1. Fei Wu B, Fu Lin C. A high-performance and memory-
efficient pipeline architecture for the 5/3 and 9/7 discrete
wavelet transform of JPEG2000 codec Circuits and Systems
for Video Technology, IEEE Transactions. 2005 Dec;
15(12):1615-28.
2. Cao P, Guo X, Wang C, Li J. Efficient architecture for two-
dimensional discrete wavelet transform based on lifting
scheme.7th International Conference-ASICON -07. 2007
October.
3. Manzoor RS, Gani R, Jeoti V, Kamel N, Asif M.
Implementation of FFT using discrete wavelet packet trans-
form (DWPT) and its application to SNR estimation in
OFDM systems. Kaula Lumpur, Malaysia: IEEE International
Symposium on Information Technology. 2008.
4. Bouwel CV. Wavelet Packet Based Multicarrier Modulation.
IEEE Communications and Vehicular Technology. 2000; p.
131-38.
8 Vol 10 (2) | January 2017 | www.indjst.org
5. Al-Azawi S, Abbas Y, Jidin R. Low complexity multidimen-
sional CDF 5/3 DWT architecture. 2014 9th International
Symposium Communication Systems, Networks & Digital
Signal Processing (CSNDSP). 2014 July.
6. Yifan S, Xiao S, Xiong Y, Hao S, Zhao X. Time-frequency
analysis system based on temporal Fourier transform, in
2015 IEEE International Conference on Communication
Problem-Solving (ICCP), Guilin, 2015.
7. S. S. Bhairannawar, S. Sarkar, K. B. Raja, K. R. Venugopal.
An Efficient VLSI architecture for fingerprint recognition
using O2D-DWT architecture and modified CORDIC
FFT. Signal Processing, Informatics, Communication and
Energy Systems (SPICES). 2015 Feb 19-21.
8. Chetan H, Indumathi G. Low power VLSI implementation
of data compression for multimedia devices using CDF
m/n DWT on to resource constrained dynamically recon-
figurable memories. New Delhi: 2016 3rd International
Conference on Computing for Sustainable Global
Development (INDIACom). 2016.
9. Baig S, Rehman FU, Mughal MJ. Performance comparison
of DFT, discrete wavelet packet and wavelet transforms.
OFDM transceiver for multipath fading channel, Multitopic
Conference. 2005.
10. Lakshmananm MK, Nikookar H. A review of wavelets
for digital wireless communication. Springer: Journal on
Wireless Personal Communication. 2006; 37(3-4):387-420.
11. Kang Lai Y, Fei Chen L, Chih Shih Y. A high-performance
and memory efficient VLSI architecture with parallel
scanning method for 2-D lifting-based discrete wavelet
transform, Consumer Electronics. IEEE Transactions. 2009
May; 55(2): 400-07.
Indian Journal of Science and Technology