On the Modeling of Switched Capacitor Converters

with Multiple Outputs

Juli`a Delos
Toni Lopez
Philips Research Netherlands
Eindhoven, The Netherlands
Email: julia.delos@philips.com
Email: toni.lopez@philips.com
Eduard Alarcon Marcel A.M. Hendrix
Technical University of Catalonia Eindhoven University of Technology
Barcelona, Spain Eindhoven, The Netherlands
Email: eduard.alarcon@upc.edu Email: m.a.m.hendrix@tue.nl

AbstractThe internal nodes of switched capacitor converters

can be used to provide multiple pulsed width modulated voltages
that, in combination with lter inductors, can extend the available
dc outputs. Such converter architecture requires models that
accurately predict the behaviour of switched capacitor converters
operated in current output mode. Based on the well-known
output impedance model, a new circuit representation is proposed
for converters with multiple current-loaded outputs. A charac-
terization methodology is developed to determine the parameters
of said model. Predictions of the new model compare favorably
to circuit simulations and experimental measurements.
N OMENCLATURE
Matrices are bold uppercase, and vectors are bold lowercase.
j phase instance
i component instance
x output instance
Aj matrix A corresponding of j th phase
A(x,y) element of the x-th row and y th column of
the matrix A
end last index of the array
: colon operator creates a index vector, i.e. x : y
generates [x, x + 1, , y]
fsw switching frequency
Dj normalized phase period of the j th phase
C capacitor value
Ron switch on-resistance
m column vector with the conversion ratios as-
sociated to the outputs
io column vector with the load currents associ-
ated to the outputs
a charge ow multiplier vector
ac capacitor charge ow multiplier vector
ain voltage supply charge ow multiplier
b capacitor charge pumped multiplier vector
ar switch charge ow multiplier vector
r redistributed charge ow multiplier vector
j
ri,x charge multiplier r corresponding to the j th
phase, ith element and xth output
qij charge ow through capacitor Ci of the j th
phase.
j
qin charge ow through the voltage supply of the
j th phase
qo,x charge ow delivered at the xth output
caps. total number of capacitors of the converter
swts. total number of switches of the converter
phas. total number of phases of the converter
I NTRODUCTION
In the search for high power density, on-chip integrated con-
verters [1], we consider new architectures based on Switched
Capacitor Converters (SCCs), Fig.1a. These converters are
suited for integration, enabling the use of lower voltage
switches when compared to the converters based on inductors.
In [2], it is demonstrated that a Point-of-Load converter based
on a SCC can achieve even superior performance and higher
power density than the classical buck converter. The pro-
posed converter combines an advanced topology with multiple
conversion ratios [3] employing a novel close-loop control
that provides a regulated 1.5V output voltage. The converter
efciency is expected to be higher than 85% even at high
operating currents.
Fig. 1: a) 3:1 Dickson SCC loaded at the dc node; b) 3:1
Dickson H-SCC loaded at the second pwm node

978-1-4799-2325-0/14/$31.00 2014 IEEE 2796

 The benets of the SCCs can be further exploited by taking
advantage of the internal switching nodes in combination with
lter inductors [4], [5], forming the hybrid architecture shown
in Fig.1b. Actually, the internal nodes of these converters pro-
vide multiple outputs with oating Pulsed-Width-Modulated
voltages. In the case of a step-down converter, each internal
node presents a square-wave voltage added to a dc offset
voltage of a fraction of the input voltage. The magnitudes
are related to the SCC topology. Connecting these nodes
with an inductive lter can provide extra dc outputs with a
continuous conversion range and efcient regulation, while at
the same time, relaxing the magnetic requirements compared
to conventional inductive switching solutions.







   


 

 
 



 
  




  







 
Fig. 2: Triple Output Fixed Ratio Converter
Yet another advantage of combining a SCC with inductors
is to enable multiple output voltages with a single power stage.
In et al. [4] is presented a Triple Output Fixed Ratio Converter
(TOFRC) where a 2:1 Ladder converter is combined with two
inductors in order to provide three xed output voltages with
a single SCC stage as shown in Fig.2. The converter provides
three different outputs: Vo1 is supplied from the dc node, and
Vo2 and Vo3 are supplied from the oating pwm nodes in
combination with lter inductors.
This combination of SCCs and inductors, the so called Hy-
brid Switched Capacitor Converter (H-SCC) [5], merges the
benets of both SMPS technologies, providing architectures
not yet fully used in integrated converters. These architectures
can substantially improve the power density of Power Systems
on Chip (PSoC) and Power Systems in Package (PSiP).
Such architectures requires models that accurately predict the
behaviour of switched capacitor converters operated in current
output mode.
This paper proposes a new circuit representation for convert-
ers with multiple current-loaded outputs, based on the well-
known output impedance model. The related characterization
methodology is developed to determine the parameters of said
model using the current-loaded analysis of SCCs [5]. The
rst section reviews the output impedance model and briey
describes the current-loaded analysis of SCCs. The equations
2797
of the model are presented. The second section introduces the
proposed output trans-impedance model for multiple output
SCCs. The third section demonstrates the duality between
the model parameters and the charge ow analysis [6]. The
fourth section describes the methodology used to obtain the
model parameters. The results are presented in the fth section
for a 2:1 Dickson converter. The results are compared with
a circuit simulator and experimental data. Finally, the last
section presents the conclusions.
I. O UTPUT I MPEDANCE M ODEL
The behavior of SSCs is modeled with the well-known
output impedance model [6] that is composed of a controlled
voltage source and equivalent resistance Rscc , as shown in
Fig.3. The output voltage provided by the converter under no-
load conditions is dened as target voltage. It is modeled with
the controlled voltage source, being the value of voltage supply
Vin multiplied by the conversion ratio m. When loaded, the
voltage droop across Rscc accounts for the losses produced
in the SC converter: capacitor charge transfer losses and
conduction losses.

   
Fig. 3: SCC Output Impedance Model
In order to infer the model parameters: k and Rscc , [6]
presents a systematic method for a SCC loaded at the dc
node as shown in the converter of the Fig.1a. This approach is
adapted in [5] to model SCCs when the converter is connected
to current-output loads, as in case of the H-SCC shown in
Fig.1b and Fig.2. The adapted method improves the accuracy
for SCCs loaded at the dc node by including the effects of the
output dc capacitor into the model.
The above methodologies are based on the charge ow
analysis of SCCs [7], where the converters are described using
charge ow multiplier vectors. A set of n charge multiplier
vectors can be derived for any well-posed n-phase SCC [6].
The vectors correspond to a charge ow that occurs in each
converter mode. Each element of the vector is associated to
a specic element of the converter, and represents the charge
ow corresponding to that element normalized with respect to
the total output charge. Therefore the charge multiplier vector
a1 is
a1 = [qin q11 qn1 ]T /qout = [ain a11 a1n ]T (1)
The analysis of current-loaded SCCs [5] extracts, for each
switching phase, three different charge multipliers vectors:
a The charge ow multiplier vector quanties the
amount of net charge owing in the capacitors based
 on the charge conservation per switching period.
The rst element of the vector corresponds to the
charge delivered by the independent voltage source,
ain . The other elements are associated with the
capacitors grouped in the vector ac .
b The capacitor charge pumped multiplier vector
quanties the amount of charge delivered to the
load by the capacitors. Each element of this vector
is associated to a capacitor.
ar The switch charge ow multiplier vector quanties
the amount of charge owing in the switches. Each
element of this vector is associated with a switch.
Using these vectors, the converter is studied in two operating
regimes: the Slow Switching Limit (SSL) and the Fast Switch-
ing Limit (FSL). Two analytical expressions of the output
impedance are obtained for each operation regime, namely,
Rssl and Rf sl .
A. Slow Switching Limit Impedance
When the converter operates in SSL, losses are dominated
by the redistribution of charge between capacitors and the
voltage supply. The redistributed charge can be computed in
a vector multiplier form using vectors a and b as,
j
r = ajc D b .
j j
Using eq. (2), the equivalent impedance is obtained as
2 The proposed model is shown in Fig.4; as it can be seen,
1   (rij )
caps. phas.
Rssl = ,
2Fsw i=1 j=1 Ci
B. Fast Switching Limit Impedance
When the converter operates in FSL, conduction losses
dominate, thus the equivalent output impedance is dened in
[5] as
swts.  Ron,i  j 2
 phas.
Rf sl = ari . (4)
Dj
i=1 j=1
The resulting equivalent resistance is thus dependent on the
charge ow through each individual switch [6].
C. Conversion Ratio
The conversion ratio of the converter can be computed from
the input charge ow multiplier as

phas.
m= ajin ,
j=1
D. Total Output Impedance
The approximation, suggested in [6], in order to obtain the
total output impedance is

Rscc = Rssl2 + R2 . (6)
f sl
This method solves the parameters of the output impedance
model of a single output SCC. This model, shown in Fig.3, is
valid only for converters with a single output. The losses are
directly proportional with the output current, and modeled with
the voltage drop across output resistance Rscc . However, this
approach is not longer applicable for converter with multiple
outputs. The following section presents a new model for such
converters.
II. O UTPUT T RANS - IMPEDANCE M ODEL
When considering a converter with multiple outputs, the
load effects have to be taken into account for all the outputs.
Actually, when the converter is loaded, it produces a voltage
drop throughout outputs of the converter. Therefore, the output
current of one output node has an inuence to the other
outputs. In order to model these effects a new model based on
trans-impedance parameters is proposed .




  


  
 
 
   

   












   

    
 
(2)
Fig. 4: Switched Capacitor Output trans-impedance model
(3) each output is represented using two controlled voltage sources
connected in anti-series. One source provides the target volt-
age associated with the output, taking the value from the input
voltage, Vin , multiplied by the respective conversion ratio
associated to that output, mx .
The other source, produces a voltage droop associated with
the losses in the converter. The current delivered by each
loaded node adds a specic contribution to the converter
losses. Therefore, this voltage source takes the value given
by the linear combination of all the converter output currents
weighted by their associated trans-impedance factor z.
The trans-impedance factor zxy produces a voltage drop at
the output x proportional to the charge (i.e. current) delivered
to the output y. It can be seen that the trans-impedance factor
zxx corresponds to the voltage drop of the same output where
the current is delivered, thus this parameter is the output
impedance for that node. Since all the trans-impedance factors
relate current to voltage, they have Ohms units.
With the proposed model, the converter behavior can be
obtained as
Vo = Z io + m Vin , (7)
(5)
where Z is the Trans-impedance matrix, which is symmetric.
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 III. C ONVERTER P OWER L OSSES M ODEL D UALITY IV. T RANS - IMPEDANCE PARAMETERS M ETHODOLOGY

Using the same trans-impedance matrix Z the losses of the Based on the charge ow analysis for current-loaded SCCs,
converter can be computed. For a two output converter the each converter output has three associated sets of vectors per
losses associated to each output would be switching phase. Thus, for a given converter, the different
vector types can be collected in a matrix, where each column
Ploss,out1 = i21 z11 + i1 i2 z12 (8) corresponds to a converter output and each row corresponds
to a circuit component. Therefore the charge ow multipliers
are collected in a matrix as
Ploss,out2 = i1 i2 z21 + i22 z22 , (9)
out1 out2 outn

and the total converter losses are vin aj1,1 aj1,2 aj1,n
C1 j
a2,1 aj2,2 aj2,n

Ploss = i21 z11 + i22 z22 + 2i1 i2 z12 . (10) Aj = . .. .. .. , (15)
.. . . .
Cp ajp,1 ajp,2 ajp,n
where z12 = z21 since Z is symmetric.
Using the the charge ow analysis described in the previous where the elements of the rst row aj1,x corresponds to the
section, the total losses of a two output converter can be com- charge ow multiplier delivered by the input voltage source
puted as well. In order to make the analysis less cumbersome, associated to the charge ow through the x-th output. The
the phases are eluded and losses are computed in a single remaining elements after the rst row are associated with the
capacitor for the SSL. The results can be extended for any charge ow in the capacitors. Therefore a1,1 is the net charge
converter with any number of phases and capacitors. ow in capacitor C1 due to the charge delivered at the 1st
The losses produced in Ci of a two output converter, can output node of a converter with p capacitors and n outputs.
be obtained from the redistributed charge ow multipliers in Likewise, the charge pumped multipliers are collected in the
the capacitor as following matrix
1
Ploss,Ci = fsw (ri,1 qo,1 + ri,2 qo,2 )2 , (11)
out1 out2 outn

2Ci C1 bj1,1 bj1,2 bj1,n
expanding terms in parentheses and equating yields C2
bj2,1 bj2,2 b2,n
j

Bj = .. .. .. .. , (16)
1 . . . .
Ploss,Ci = (i21 ri,1
2
+ i22 ri,2
2
+ i1 i2 2ri,1 ri,2 ). (12) Cp bjp,1 bjp,2 bjp,n
2fsw Ci
It can be seen that the trans-impedance parameters of eq. (10) where all the elements are associated with the converter
can be directly matched with the charge ow multipliers in capacitors.
eq. (12) as On the other hand, the switch charge ow multipliers lead
to the following matrix
2 
z11 = ri,1 []
2fsw Ci out1 out2 outn
j j j
2  sw1 ar1,1 ar1,2 ar1,n
z22 = ri,2 []
2fsw Ci sw2 j j
j
ar2,1 ar2,2 ar2,n
Ar =
j
. ..
ri,1 ri,2  .. .. . (17)
z12 = [] .. . .
2fsw Ci .
j j
swp arp,1 arp,2 j
arp,n
Therefore the general expression of a trans-impedance pa-
rameter for the SSL is obtained with redistributed charge where all the elements are associated with the converter
multipliers as switches. This matrix can be extended with the Equivalent
Series Resistance (ESR) of the capacitors, but for the sake of
1   ri,x ri,y
caps. phas. j j
clarity they are not included in the present calculations yet.
zssl,xy = . (13) The converter is described with two trans-impedance matrix:
2fsw i=1 j=1 Ci
one for the SSL, Zssl , and another for the FSL, Zfsl .
When the converter operates in FSL, the general expression
using the switch charge ow multipliers is A. Slow Switching Limit Trans-impedance Matrix
The redistributed charge ow multipliers matrix can be
 phas.
swts.  Ron,i j j obtained from the matrices A and B as
zf sl,xy = ari,x ari,y . (14)
Dj
i=1 j=1 Rj = Aj(2:end,1:end) Dj Bj , . (18)

2799
The redistributed charge corresponds to the charge that ows
between capacitors; therefore it is the root cause of losses 


 
associated with the SSL operation regime [6].
The SSL trans-impedance factors can be individually ob-

  
  
tained from the redistributed charge multipliers as described 

in eq. (13). In order to obtain directly the trans-impedance 
 



matrix, the operation in eq. (13) is performed in two steps. 

First, the outer product of each row of Rj is taken with itself

as  



Kji = [Rj(i,1:end) ]T Rj(i,1:end) , (19)
where the matrix Ki contains all the possible products of the
ith row. Since each row in R is associated with a capacitor,
there is a matrix Ki for each capacitor Ci . Second, with the Fig. 5: All the output nodes of the 2:1 Dickson loaded with a
set of K matrices the trans-impedance matrix is obtained as constant current source

1   1 j
phas. caps.
Zssl = K . (20) output Vo3 , the second column to the output Vo2 , and the third
2Fsw j=1 i=1 Ci i
column to the output Vo1 .
B. Fast Switching Limit trans-impedance Matrix The values for the capacitor charge ow multipliers are

For the FSL, the trans-impedance matrix is obtained using 1+D 1 D
the switch charge multipliers contained in matrix Ar. The 1
A 1 = 1 D 1 D , (25)
operation to obtain the trans-impedance matrix as described 2
in eq. (14) is performed in two steps. First, a set of matrices 1 D 1 2D D

are obtained by taking the outer product of each row of Ar 0 0 0
with itself as 1
A 2 = D 1 1 D . (26)
2
Krji = Arj(i,1:end) [Arj(i,1:end) ]T , (21) D 1 2D 1 D
yielding a matrix for each row in Ar associated with a switch The values of the capacitor charge pump multipliers are
on-resistance (Ron ). Second, with the set of matrices Kr the 
FSL trans-impedance matrix is obtained as 1 1 0 C1 C1
B = , (27)
C1 + C2 0 C2 C2
 phas.
swts.  Ron,i 
Zfsl = Krji , (22) C C 0
Dj 1 1 1
i=1 j=1 B2 = . (28)
C1 + C2 C2 C2 0
C. Total Trans-impedance Matrix
The values of the switch charge ow multipliers are
Following the suggested approximation [6] for the total out-

put impedance described in eq. (6), the total trans-impedance D+1 1 D
parameters is assumed to be 1 0 0 0
 Ar1 = , (29)
Z(x,y) = Zssl,(x,y) 2 + Zfsl,(x,y) 2 . (23) 2 D 1 1 D
0 0 0
D. Conversion Ratio Vector
The conversion ratio vector is obtained as 0 0 0
1D 1 1 D

phas.
Ar2 = . (30)
m= [Aj(1,1:end) ]T . (24) 2 0 0 0
j=1 D 1 1 2D 1
V. R ESULTS The resulting conversion ratio vector is
The trans-impedance matrix is determined for the converter
1+D
of Fig. 5. The results of the model parameters are compared 1
with both PLECS1 simulations and experiments. m = 1 . (31)
2
The circuit is solved for matrices A, B and Ar in both 1D
phases. As previously mentioned, each column corresponds
to an output node, where the rst column corresponds to the It can be seen that the conversion ratio of the top Vo3 and the
bottom Vo1 outputs are function of the duty cycle . Note that
1 Behavioral circuit simulator running on Matlab -Simulink the dc node, output Vo2 , has a constant conversion ratio.

2800
 Model PLECS Absolute Error
z11 [] z22 [] z33 []
3 103
1.6 2.5 103
1.5 3 103
1.6

|Error|
|Error|

|Error|
1.5 1.3 1.8 1.5 1.5 1.3

0 1 1 1.5 0 1
z12 [] z23 [] z31 []
3 103
1 3 103
1 5 10
4 1010
2

|Error|

|Error|
|Error|
1.5 0.7 1.5 0.7 5 0.5

0 0.4 0 0.4 5 1
0 50 100 0 50 100 0 50 100
Duty Cycle [%] Duty Cycle [%] Duty Cycle [%]

Fig. 6: SSL comparison between PLECS simulation and the proposed model.

Model PLECS Absolute Error

z11 [] z22 [] z33 []
3 102
4 3 102
5 3 102
4

|Error|
|Error|

|Error|
1.5 1 2 0 1.5 1

0 2 1 5 0 2
z12 [] z23 [] z31 []
3 102
4 3 102
4 2.5 10
1 1012
5
|Error|

|Error|
|Error|

1.5 1 1.5 1 2.5 0

0 2 0 2 2.5 5
0 50 100 0 50 100 0 50 100
Duty Cycle [%] Duty Cycle [%] Duty Cycle [%]

Fig. 7: FSL comparison between PLECS simulation and the proposed model.

The results are shown in Figs. 6 and 7, comparing model in the Table I. In each simulation the duty cycle of the driving
parameters values obtained with the presented methodology signal has been swept from 10% to 90%.
with the results obtained using PLECS. Since the proposed
TABLE I: Simulation proles associated with the different
method has the goal to model the losses produced by the ca-
operation modes.
pacitive charge transfer and parasitic resistances, a behavioral
simulator that only takes into account these two source of Mode fsw C Ron
losses is employed for validation. Other loss mechanisms, such SSL 100 kHz 1 F 1 m
as switching losses, could be added to the model, as described FSL 10 MHz 1 F 500 m
in [6].
The experimental circuit has been simulated for the two In both cases the predicted values compare favorably with
operation modes SSL and FSL. Each operation mode has been the simulation results. The predicted values follow the trend
simulated with different parameters corresponding to the ones of the simulation results with the variations of the duty cycle,

2801
 Model Prototype Absolute Error

z11 [] z12 [] z13 []

1 1
2 10 1.5 2 10 1 1 0

|Error|

|Error|
|Error|
1 1 1 0.5 0 1

0 0.5 0 0 1 2

z21 [] z22 [] z23 []

1 1 101 1
2 10 1.5 2 10 2 10 2
9

|Error|
|Error|

|Error|
1 1 1 8 1 0
7
0 0.5 0 0 2

z31 [] z32 [] z33 []

1 101
5 2 10
1
1 2 10
1
1

|Error|
|Error|

|Error|
0.5 0 1 0 1 0

0 5 0 1 0 1
0 50 100 0 50 100 0 50 100
Duty Cycle [%] Duty Cycle [%] Duty Cycle [%]

Fig. 8: Comparison between measurements of the experimental set-up and the predicted results of the proposed model.

where the error is always less than 4%.
An experimental set-up of the converter in Fig. 1 has
been built. The converter uses four MOSFETs TN0104 from
Supertex with typical on-resistance of 1.5 . Two tantalum
electrolytic capacitors of 10F have been used as ying
capacitors. The circuit was operated at 5kHz and the trans-
impedance parameters are measured at different duty cycles.
The results are compared with the model and presented in Fig.
8, it can be seen that the predictions match the measured values
with less than 10% error. All the trans-impedance values with
the exception of parameters z31 and z13 follow the trend with
the duty cycle predicted by the model. z31 and z13 have a
bigger error since these values are much smaller than the rest
of the converter parameters and, therefore, more sensitive to
the parasitics of the board.
The measured results of the experimental set-up can be
improved mounting the circuit in a PCB with less parasitics
and operated at higher switching frequencies by using ceramic
capacitors instead of the tantalum ones .
VI. C ONCLUSIONS
SCCs have the potential for high power density, fully inte-
grated power converters. Combining them with inductors lead
to new architectures with multiple outputs. A new model that
covers all these new topologies has been presented along with
a characterization methodology. Unlike the previous models,
this method allows to model the behaviour of multiple current
loaded outputs, including their coupling relations. The model
has been veried with simulations and experiments, and for
both cases compares favorably. Since the resulting model
is based on analytical expressions; the computation time is
dramatically faster than any time-domain based simulator.
The presented model is a valuable tool for modeling a broad
range of SCCs, from the classical approach of a single output
converter to the new architectures where SCCs are combined
with inductors. At the same time, it enables a fast exploration
of the design space, enabling a rapid optimization of the
converter parameters.
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