Professional Documents
Culture Documents
1 1
2
Compal confidential 2
Schematics Document
Mobile Dothan uFCPGA with Intel
Alviso_GM+ICH6-M core logic
3
2006-09-15 3
REV:1.0
4 4
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Cover Sheet
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 1 of 43
A B C D E
A B C D E
Compal confidential
File Name : LA-3361P
1 1
FSB
H_A#(3..31) 400/533MHz H_D#(0..63)
LVDS CONN
page 14 One Channel
DDR2 -400/533 DDR2-SO-DIMM0
Intel Alviso GMCH page 12
2 2
USB conn x2
page 28
PCI-E(DMI)
USB conn x2
Option(15.4 Sub board connector)
page 19
socket
CB-1410
page 24
page 23
RJ45/11 CONN LPC BUS IDEBUS IDE HDD IDE ODD
page 22 Connector
page 21
Connector
page 21
Slot 0
page 23
EC KB910L Intel CPU debug conn Page 4
EC debug conn Page 29
RTC CKT. page 29 SW debug conn Page 29
page 18
Switch Button list:
Power Botton Page 30
Int.KBD Lid Switch Page 30
Power On/Off CKT. Touch Pad CONN.
page 31
page 29 LED Function List
page 29 Flash ROM Power LED Page 28
4
Caps Lock LED Page 28
4
33,34,35,36,37,38,39 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Block Diagram Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 2 of 43
A B C D E
5 4 3 2 1
S1 ON ON ON 46144232L01 915GM
46144232L02 910GML W/O WLAN
S3 ON ON OFF
46144232L03 910GML
S5 S4/AC ON OFF OFF
IAT10 15.4"
S5 S4/AC don't exist OFF OFF OFF
46144232L11 910GML
46144232L12 915GM
B 46144232L13 910GML W/O WLAN B
THERMAL
SOURCE INVERTER BATT SERIAL SENSOR SODIMM CLK CHIP MINI PCI LCD
EEPROM (CPU)
ADM1032
SMB_EC_CK1 KB910L
SMB_EC_DA1
SMB_EC_CK2 KB910L
SMB_EC_DA2
ICH_SMBCLK
ICH6-M
ICH_SMBDATA
LCD_DDCCLK Alviso
LCD_DDCDATA GM-GP
I2CC_SCL NV44M
A
I2CC_SDA A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Design Note Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1
ZZZ1
1
R37 H_HITM# K4 CONTROL GROUP AE22 H_D#55
<7> H_HITM# HITM# D55#
1 2 H_IERR# A4 AF23 H_D#56 R258
+VCCP 56_0402_5% H_LOCK# IERR# D56# H_D#57
<7> H_LOCK# J2 LOCK# D57# AD24 1K_0402_5%
H_RESET# B11 AF20 H_D#58
<7> H_RESET# RESET# D58#
1" ~ 6.5" AE21 H_D#59
2
D59#
1
AD21 H_D#60
<7> H_RS#[0..2] D60#
H_RS#0 H1 AF25 H_D#61 R266
H_RS#1 RS0# D61# H_D#62
K1 RS1# D62# AF22 56_0402_5%
H_RS#2 L2 AF26 H_D#63
RS2# D63# PROCHOT# <29>
H_TRDY# M3
<7> H_TRDY#
2
TRDY#
1
R253 C
D25 56_0402_5% 2 Q29
DINV0# H_DINV#0 <7> B
J26 2SC2411K_SOT23
DINV1# H_DINV#1 <7> E
XDP_BPM#0 C8 T24 H_DINV#2 <7>
3
XDP_BPM#1 BPM0# DINV2#
B8 AD20 H_DINV#3 <7>
2
XDP_BPM#2 BPM1# DINV3#
A9 BPM2#
B XDP_BPM#3 B
C9 BPM3# H_DSTBN#[0..3] <7>
C23 H_DSTBN#0 H_PROCHOT#
XDP_DBRESET# DSTBN0# H_DSTBN#1
<19> XDP_DBRESET# A7 DBR# DSTBN1# K24
H_DPRSLP will change to H_DBSY# M2 W25 H_DSTBN#2
<7> H_DBSY# DBSY# DSTBN2#
H_DPSLP# B7 AE24 H_DSTBN#3
H_DPRSTP in future <18> H_DPSLP#
H_DPRSLP# G1
DPSLP# DSTBN3#
C22 H_DSTBP#0
H_DSTBP#[0..3] <7>
<18> H_DPRSLP# DPRSTP# DSTBP0#
collateral version. <7> H_DPWR# C19 DPWR# DSTBP1# L24 H_DSTBP#1
XDP_BPM#4 A10 MISC W24 H_DSTBP#2
XDP_BPM#5 PRDY# DSTBP2# H_DSTBP#3
B10 PREQ# DSTBP3# AE25
H_PROCHOT# B17
H_PWRGOOD_R R2009 2 PROCHOT#
1 1K_0402_5%
<18> H_PWRGOOD E4 PWRGOOD
H_CPUSLP# A6
<7,18> H_CPUSLP# SLP#
XDP_TCK A13
XDP_TDI TCK H_A20M#
C12 TDI A20M# C2 H_A20M# <18>
XDP_TDO A12 D3 H_FERR#
TDO FERR# H_FERR# <18>
TEST1 C5 A3 H_IGNNE#
TEST1 IGNNE# H_IGNNE# <18>
TEST2 F23 B5 H_INIT#
TEST2 INIT# H_INIT# <18>
XDP_TMS C11 D1 H_INTR
TMS LINT0 H_INTR <18>
XDP_TRST# B13 D4 H_NMI
TRST# LINT1 H_NMI <18>
LEGACY CPU
THERMAL
H_THERMDA B18 C6 H_STPCLK#
<13> H_THERMDA
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# <18>
R32
<13> H_THERMDC A18 THERMDC SMI# B4 H_SMI# <18> Add pullups for PWRGOOD and THERMTRIP per INTEL
C17 200_0402_5%
<7,18> H_THERMTRIP# THERMTRIP#
+VCCP 1 2 H_PWRGOOD
TYCO_1612365-1_Dothan
R251
A TEST2 A
1 2
@ 1K_0402_5%
R35
TEST1 1 2
@ 1K_0402_5%
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Dothan Processor(1/2) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
U15C
R181 U15B
@ 54.9_0402_1% F20 T26
VCCSENSE VCC VSS
1 2 AE7 VCCSENSE VSS A2 F22 VCC VSS U2
+1.5VS 1 2 VSSSENSE AF6 A5 G5 U6
R178 VSSSENSE VSS VCC VSS
VSS A8 G21 VCC VSS U22
@ 54.9_0402_1% A11 H6 U24
VSS VCC VSS
F26 VCCA0 VSS A14 H22 VCC VSS V1
B1 VCCA1 VSS A17 J5 VCC VSS V4
D D
N1 VCCA2 VSS A20 J21 VCC VSS V5
AC26 VCCA3 VSS A23 K22 VCC VSS V21
+VCCP VSS A26 U5 VCC VSS V25
P23 VCCQ0 VSS B3 V6 VCC VSS W3
W4 VCCQ1 VSS B6 V22 VCC VSS W6
VSS B9 W5 VCC VSS W22
B12 W21 W23
D10 Dothan VSS
B16 Y6
VCC VSS
W26
C340
1 1
C341
D12
VCCP
VCCP
VSS
VSS B19 Y22
VCC
VCC
Dothan VSS
VSS Y2
D14 VCCP VSS B22 AA5 VCC VSS Y5
0.01U_0402_16V7K 10U_1206_6.3V6M D16 B25 AA7 Y21
2 2 VCCP VSS VCC VSS
E11 VCCP VSS C1 AA9 VCC VSS Y24
E13 VCCP VSS C4 AA11 VCC VSS AA1
E15 C7 AA13 AA4
TYCO_1612365-1_Dothan
Layout Note: TYCO_1612365-1_Dothan
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Dothan Processor(2/2) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 5 of 43
5 4 3 2 1
5 4 3 2 1
+CPU_CORE +CPU_CORE
1 1 1 1 1 1 1 1 1 1
C84 C87 C90 C93 C97 C99 C83 C86 C89 C92
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
2 2 2 2 2 2 2 2 2 2
D D
+CPU_CORE +CPU_CORE
1 1 1 1 1 1 1 1 1 1
C259 C265 C81 C82 C100 C101 C102 C98 C260 C267
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
2 2 2 2 2 2 2 2 2 2
+CPU_CORE +CPU_CORE
1 1 1 1 1 1 1 1 1 1
C274 C280 C293 C301 C273 C279 C292 C300 C257 C256
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
2 2 2 2 2 2 2 2 2 2
+CPU_CORE
1 1 1 1 1
C303 C302 C282 C283 C272
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M
C 2 2 2 2 2 C
1 1 1 1
ESR <= 3m ohm
6/21 + + + +
C94 C286 C95 C285
B 330U_D2E_2.5VM 330U_D2E_2.5VM
Capacitor > 880 uF B
2 330U_D2E_2.5VM
2 2 2
@ 330U_D2E_2.5VM
+VCCP
1
C70 1 1 1 1 1 1 1 1 1 1
+ 150U_D2_6.3VM
C85 C88 C91 C96 C103 C104 C78 C80 C105 C79
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Dothan Bypass Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 6 of 43
5 4 3 2 1
5 4 3 2 1
U5A
<4> H_A#[3..31] H_D#[0..63] <4>
H_A#3 G9 E4 H_D#0
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H_D#1
H_A#5 E9 F4 H_D#2 U5B
H_A#6 HA5# HD2# H_D#3
B7 HA6# HD3# H7
H_A#7 A10 E2 H_D#4 DMI_TXN0 AA31 G16 CFG0
HA7# HD4# <19> DMI_TXN0 DMIRXN0 CFG0
H_A#8 F9 F1 H_D#5 DMI_TXN1 AB35 H13 MCH_CLKSEL1
HA8# HD5# <19> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <16>
H_A#9 D8 E3 H_D#6 DMI_TXN2 AC31 G14 MCH_CLKSEL0
HA9# HD6# <19> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL0 <16>
H_A#10 B10 D3 H_D#7 DMI_TXN3 AD35 F16 T27 PAD
D HA10# HD7# <19> DMI_TXN3 DMIRXN3 CFG3 D
H_A#11 E10 K7 H_D#8 F15 T28 PAD
H_A#12 HA11# HD8# H_D#9 DMI_TXP0 CFG4 CFG5
G10 HA12# HD9# F2 <19> DMI_TXP0 Y31 DMIRXP0 CFG5 G15
H_A#13 D9 J7 H_D#10 DMI_TXP1 AA35 E16 CFG6
HA13# HD10# <19> DMI_TXP1 DMIRXP1 CFG6
H_A#14 E11 J8 H_D#11 DMI_TXP2 AB31 D17 CFG7
HA14# HD11# <19> DMI_TXP2 DMIRXP2 CFG7
H_A#15 F10 H6 H_D#12 DMI_TXP3 AC35 J16
HA15# HD12# <19> DMI_TXP3 DMIRXP3 CFG8
H_A#16 G11 F3 H_D#13 D15 CFG9
H_A#17 HA16# HD13# H_D#14 DMI_RXN0 CFG9
G13 HA17# HD14# K8 <19> DMI_RXN0 AA33 DMITXN0 CFG10 E15 CFG[17:3]: internal pull-up
H_A#18 C10 H5 H_D#15 DMI_RXN1 AB37 D14
<19> DMI_RXN1
DMI
H_A#19 HA18# HD15# H_D#16 DMI_RXN2 DMITXN1 CFG11 CFG12
C11 HA19# HD16# H1 <19> DMI_RXN2 AC33 DMITXN2 CFG12 E14 CFG[19:18]: internal pull-down +VCCP
H_A#20 D11 H2 H_D#17 DMI_RXN3 AD37 H12 CFG13
HA20# HD17# <19> DMI_RXN3 DMITXN3 CFG13
H_A#21 C12 K5 H_D#18 C14
H_A#22 HA21# HD18# H_D#19 DMI_RXP0 CFG14 CFG0 R149 2 1 10K_0402_5%
CFG/RSVD
B13 HA22# HD19# K6 <19> DMI_RXP0 Y33 DMITXP0 CFG15 H15
H_A#23 A12 J4 H_D#20 DMI_RXP1 AA37 J15 CFG16
HA23# HD20# <19> DMI_RXP1 DMITXP1 CFG16
H_A#24 F12 G3 H_D#21 DMI_RXP2 AB33 H14 CFG0 R709 1 2 @ 1K_0402_5%
HA24# HD21# <19> DMI_RXP2 DMITXP2 CFG17
H_A#25 G12 H3 H_D#22 DMI_RXP3 AC37 G22 CFG18
HA25# HD22# <19> DMI_RXP3 DMITXP3 CFG18
H_A#26 E12 J1 H_D#23 G23 CFG19 CFG5 R127 1 2 @ 1K_0402_5%
H_A#27 HA26# HD23# H_D#24 CFG19
C13 HA27# HD24# L5 CFG20 D23
H_A#28 B11 K4 H_D#25 M_CLK_DDR0 AM33 G25 CFG6 R124 1 2 1K_0402_5%
HA28# HD25# <12> M_CLK_DDR0 SM_CK0 RSVD21
H_A#29 D13 J5 H_D#26 M_CLK_DDR1 AL1 G24
HA29# HD26# <12> M_CLK_DDR1 SM_CK1 RSVD22
H_A#30 A13 P7 H_D#27 AE11 J17 CFG7 R117 1 2 @ 1K_0402_5%
H_A#31 HA30# HD27# H_D#28 SM_CK2 RSVD23
F13 HA31# HD28# L7 AJ34 SM_CK3 RSVD24 A31
T29 PAD J3 H_D#29 AF6 A30 CFG9 R119 1 2 @ 1K_0402_5%
TP_H_PCREQ# HD29# H_D#30 SM_CK4 RSVD25
A11 P5 AC10 D26
HOST
<4> H_REQ#[0..4] HPCREQ# HD30# SM_CK5 RSVD26
H_REQ#0 A7 L3 H_D#31 D25 CFG12 R710 1 2 @ 1K_0402_5%
H_REQ#1 HREQ#0 HD31# H_D#32 M_CLK_DDR#0 RSVD27
D7 HREQ#1 HD32# U7 <12> M_CLK_DDR#0 AN33 SM_CK0#
DDR MUXING
H_REQ#2 B8 V6 H_D#33 M_CLK_DDR#1 AK1 CFG13 R711 1 2 @ 1K_0402_5%
HREQ#2 HD33# <12> M_CLK_DDR#1 SM_CK1#
H_REQ#3 C7 R6 H_D#34 AE10
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK2# CFG16 R712 1
A8 HREQ#4 HD35# R5 AJ33 SM_CK3# 2 @ 1K_0402_5%
H_ADSTB#0 B9 P3 H_D#36 AF5 CFG18 R641 1 2 @ 1K_0402_5%
<4> H_ADSTB#0 HADSTB#0 HD36# SM_CK4#
H_ADSTB#1 E13 T8 H_D#37 AD10 CFG19 R642 1 2 @ 1K_0402_5%
<4> H_ADSTB#1 HADSTB#1 HD37# SM_CK5#
R7 H_D#38
HD38# H_D#39 DDR_CKE0_DIMMA
C <16> CLK_MCH_BCLK# AB1
AB2
HCLKN HD39# R8
U8 H_D#40
<12> DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
AP21
AM21
SM_CKE0 6/07 C
<16> CLK_MCH_BCLK HCLKP HD40# <12> DDR_CKE1_DIMMA SM_CKE1
R4 H_D#41 AH21 Chage CFG18 and CFG19 to PU +2.5VS for SI
<4> H_DSTBN#[0..3] HD41# SM_CKE2
H_DSTBN#0 G4 T4 H_D#42 AK21
H_DSTBN#1 HDSTBN#0 HD42# H_D#43 SM_CKE3
K1 HDSTBN#1 HD43# T5 Layout Note: BM_BUSY# J23 PM_BMBUSY# <19>
H_DSTBN#2 R3 R1 H_D#44 DDR_CS0_DIMMA# AN16 J21 PM_EXTTS#0
H_DSTBN#3 V3
HDSTBN#2 HD44#
T3 H_D#45 Rote as short <12> DDR_CS0_DIMMA#
DDR_CS1_DIMMA# AM14
SM_CS0# EXT_TS0#
H22 PM_EXTTS#1
<4> H_DSTBP#[0..3] HDSTBN#3 HD45# <12> DDR_CS1_DIMMA# SM_CS1# EXT_TS1#
H_DSTBP#0 G5 HDSTBP#0 HD46# V8 H_D#46 as possible AH15 SM_CS2# THRMTRIP# F5 H_THERMTRIP# <4,18>
H_DSTBP#1 K2 U6 H_D#47 AG16 AD30
HDSTBP#1 HD47# SM_CS3# PWROK +VCCP_PWRGD <29>
H_DSTBP#2 R2 W6 H_D#48 AE29
CLK PM
HDSTBP#2 HD48# RSTIN# PLTRST_MCH# <17,21,23>
H_DSTBP#3 W4 U3 H_D#49 @ 40.2_0402_1% R136 1 2 M_OCDOCMP0 AF22
HDSTBP#3 HD49# H_D#50 @ 40.2_0402_1% R147 1 M_OCDOCMP1 SM_OCDCOMP0
<4> H_DINV#0 H8 HDINV#0 HD50# V5 2 AF16 SM_OCDCOMP1
K3 W8 H_D#51 M_ODT0 AP14 A24
<4> H_DINV#1 HDINV#1 HD51# +VCCP <12> M_ODT0 SM_ODT0 DREF_CLKN DREFCLK# <16>
T7 W7 H_D#52 M_ODT1 AL15 A23
<4> H_DINV#2 HDINV#2 HD52# <12> M_ODT1 SM_ODT1 DREF_CLKP DREFCLK <16>
U5 U2 H_D#53 AM11 D37
<4> H_DINV#3 HDINV#3 HD53# SM_ODT2 DREF_SSCLKP SSC_DREFCLK <16>
U1 H_D#54 AN10 C37
HD54# SM_ODT3 DREF_SSCLKN SSC_DREFCLK# <16>
Y5 H_D#55 R159 80.6_0402_1%
H_RESET# HD55# H_D#56 SMRCOMPN
<4> H_RESET# H10 HCPURST# HD56# Y2 +1.8V 1 2 AK10 SMRCOMPN
1
1
54.9_0402_1%
54.9_0402_1%
V4 H_D#57 1 2 SMRCOMPP AK11 AP37
H_ADS# HD57# H_D#58 V_DDR_MCH_REF SMRCOMPP NC1
<4> H_ADS# F8 HADS# HD58# Y7 AF37 SMVREF0 NC2 AN37
R163
R164
H_TRDY# B5 W1 H_D#59 R157 80.6_0402_1% AD1 AP36
<4> H_TRDY# HTRDY# HD59# SMVREF1 NC3
G6 W3 H_D#60 AE27 AP2
<4> H_DPWR# HDPWR# HD60# SMXSLEWIN NC4
H_DRDY# F7 Y3 H_D#61 AE28 AP1
<4> H_DRDY#
2
NC
<4> H_LOCK# B3 HLOCK# HXRCOMP C1 NC10 A36
H_BR0# E7 C2 H_XSCOMP A37 10K_0402_5%
<4> H_BR0# HBREQ0# HXSCOMP NC11
H_BNR# A5 T1 H_YRCOMP PM_EXTTS#1 2 1
<4> H_BNR# HBNR# HYRCOMP
H_BPRI# D5 L1 H_YSCOMP
<4> H_BPRI# HBPRI# HYSCOMP
H_DBSY# C6 D1 H_SWNG0 ALVISO_BGA1257
<4> H_DBSY# HDBSY# HXSWING
H_CPUSLP# G8 P1 H_SWNG1
B <4,18> H_CPUSLP# HCPUSLP# HYSWING B
H_RS#0 A4 Refer to sheet 19 for FSB
HRS0#
24.9_0402_1%
24.9_0402_1%
H_RS#1 C5 CFG[2:0]
HRS1#
1
R170
ALVISO_BGA1257
Low = DMI x 2
CFG5
High = DMI x 4
*
2
PM-C0-SA0091501D0(R3)&SA0091501E0(R1)
10/20 mils
Low = DDR-II
GM-B1-SA0091500A0(R3)&SA009150070(R1)
CFG6 *
High = DDR-I
Low = DT/Transportable CPU
CFG7
High = Mobile CPU
*
Low = Reverse Lane
CFG9
High = Normal Operation
*
+VCCP +VCCP +VCCP +1.8V 00 = Reserved
01 = XOR Mode Enabled
CFG[13:12] 10 = All Z Mode Enabled
11 = Normal Operation (Default)
*
1
221_0603_1%
221_0603_1%
1
1
200_0402_1% 100_0402_1%
R174 CFG16
1
R173
R168
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A (VCC Select) A
0.1U_0402_16V4Z
1 1 1 High = 1.5V
1
1
100_0402_1%
100_0402_1%
1 1 R172
C237
R160
R169
R167
C22
C252
C247
High = 1.2V
2
2 2
2
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(1 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 7 of 43
5 4 3 2 1
5 4 3 2 1
D D
U5C U5D
DDR_A_D[0..63] <12>
DDR_A_BS#0 AK15 AG35 DDR_A_D0 AJ15 AE31
<12> DDR_A_BS#0 SA_BS0# SADQ0 SB_BS0# SBDQ0
DDR_A_BS#1 AK16 AH35 DDR_A_D1 AG17 AE32
<12> DDR_A_BS#1 SA_BS1# SADQ1 SB_BS1# SBDQ1
DDR_A_BS#2 AL21 AL35 DDR_A_D2 AG21 AG32
<12> DDR_A_BS#2 SA_BS2# SADQ2 SB_BS2# SBDQ2
AL37 DDR_A_D3 AG36
<12> DDR_A_DM[0..7] SADQ3 SBDQ3
DDR_A_DM0 AJ37 AH36 DDR_A_D4 AF32 AE34
DDR_A_DM1 SA_DM0 SADQ4 DDR_A_D5 SB_DM0 SBDQ4
AP35 SA_DM1 SADQ5 AJ35 AK34 SB_DM1 SBDQ5 AE33
DDR_A_DM2 AL29 AK37 DDR_A_D6 AK27 AF31
DDR_A_DM3 SA_DM2 SADQ6 DDR_A_D7 SB_DM2 SBDQ6
AP24 SA_DM3 SADQ7 AL34 AK24 SB_DM3 SBDQ7 AF30
DDR_A_DM4 AP9 AM36 DDR_A_D8 AJ10 AH33
DDR_A_DM5 SA_DM4 SADQ8 DDR_A_D9 SB_DM4 SBDQ8
AP4 SA_DM5 SADQ9 AN35 AK5 SB_DM5 SBDQ9 AH32
DDR_A_DM6 AJ2 AP32 DDR_A_D10 AE7 AK31
DDR_A_DM7 SA_DM6 SADQ10 DDR_A_D11 SB_DM6 SBDQ10
AD3 SA_DM7 SADQ11 AM31 AB7 SB_DM7 SBDQ11 AG30
AM34 DDR_A_D12 AG34
<12> DDR_A_DQS[0..7] SADQ12 SBDQ12
DDR_A_DQS0 AK36 AM35 DDR_A_D13 This Symbol as same AF34 AG33
DDR_A_DQS1 AP33 SA_DQS0 SADQ13 DDR_A_D14 SB_DQS0 SBDQ13
SA_DQS1 SADQ14 AL32 as Intel CRB AK32 SB_DQS1 SBDQ14 AH31
DDR_A_DQS2 AN29 AM32 DDR_A_D15 AJ28 AJ31
DDR_A_DQS3 AP23 SA_DQS2 SADQ15
AN31 DDR_A_D16 schematic, So Layout AK23
SB_DQS2 SBDQ15
AK30
DDR_A_DQS4 AM8 SA_DQS3 SADQ16 DDR_A_D17 Guide will show these SB_DQS3 SBDQ16
SA_DQS4 SADQ17 AP31 AM10 SB_DQS4 SBDQ17 AJ30
DDR_A_DQS5 AM4 AN28 DDR_A_D18 signals routed AH6 AH29
DDR_A_DQS6 SA_DQS5 SADQ18 DDR_A_D19 SB_DQS5 SBDQ18
AJ1 SA_DQS6 SADQ19 AP28 differentially. AF8 SB_DQS6 SBDQ19 AH28
DDR_A_DQS7 AE5 AL30 DDR_A_D20 AB4 AK29
SA_DQS7 SADQ20 DDR_A_D21 SB_DQS7 SBDQ20
<12> DDR_A_DQS#[0..7] SADQ21 AM30 SBDQ21 AH30
DDR_A_DQS#0 AK35 AM28 DDR_A_D22 AF35 AH27
ALVISO_BGA1257 ALVISO_BGA1257
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(2 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 8 of 43
5 4 3 2 1
5 4 3 2 1
D D
+1.5VS_PCIE
R125
U5G 24.9_0402_1%
R5 1 2 @ 0_0402_5% H24 D36 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H25 SDVOCTRL_CLK EXP_ICOMPO D34
T46 PAD AB29
MISC
<16> CLK_MCH_3GPLL# GCLKN
<16> CLK_MCH_3GPLL AC29 GCLKP EXP_RXN0/SDVO_TVCLKIN# E30
EXP_RXN1/SDVO_INT# F34
EXP_RXN2/SDVO_FLDSTALL# G30
1 2 COMPS A15 H34
150_0402_1% R334 1 LUMA TVDAC_A EXP_RXN3
2 C16 TVDAC_B EXP_RXN4 J30
150_0402_1% R335 1 2 CRMA A17 K34
150_0402_1% R336 TVDAC_C EXP_RXN5
J18 TV_REFSET EXP_RXN6 L30
4.99K_0603_1%
B15 TV_IRTNA EXP_RXN7 M34
1
B16 TV_IRTNB EXP_RXN8 N30
B17 P34
TV
TV_IRTNC EXP_RXN9
R392
EXP_RXN10 R30
EXP_RXN11 T34
C C
TV Enable: R334,R335,R336 :75 ohm U30
2
EXP_RXN12
EXP_RXN13 V34
TV Disable: R334,R335,R336 :150 ohm EXP_RXN14 W30
CRT_SMBCLK E24 Y34
<15> CRT_SMBCLK DDCCLK EXP_RXN15
CRT_SMBDAT E23
<15> CRT_SMBDAT DDCDATA
<15> CRT_BLU E21 BLUE EXP_RXP0/SDVO_TVCLKIN D30
D21 BLUE# EXP_RXP1/SDVO_INT E34
<15> CRT_GRN C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
B20 GREEN# EXP_RXP3 G34
<15> CRT_RED A19 RED EXP_RXP4 H30
B19 RED# EXP_RXP5 J34
H21 K30
VGA
<15> VSYNC VSYNC EXP_RXP6
<15> HSYNC G21 HSYNC EXP_RXP7 L34
ALVISO_BGA1257
A A
08/09 Add B channel
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(3 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 9 of 43
5 4 3 2 1
5 4 3 2 1
U5F
10U_0805_6.3V6M
0.1U_0402_16V4Z
R11 AN26 V2.5_DDR_CAP1 M29 C18
P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26
V2.5_DDR_CAP2
V2.5_DDR_CAP5 1 1
K29
J29
VCC3
VCC4
VCC5
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
F18
E18
C212
C202
M11 VTT10 VCCSM10 AK26 1 1 1 V28 VCC6
D D
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L11 AJ26 U28 H18
VTT11 VCCSM11 VCC7
POWER VCCA_TVBG
C192
C23
C24
K11 VTT12 VCCSM12 AH26 T28 VCC8 VSSA_TVBG G18
2 2 +2.5VS +2.5VS
W10 VTT13 VCCSM13 AG26 R28 VCC9
2 2 2
V10 VTT14 VCCSM14 AF26 P28 VCC10 VCCD_TVDAC D19
+VCCP U10 AE26 N28 H17
VTT15 VCCSM15 VCC11 VCCDQ_TVDAC +1.5VS
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
T10 VTT16 VCCSM16 AP25 M28 VCC12
10U_0805_6.3V6M
10U_0805_6.3V6M
R10 VTT17 VCCSM17 AN25 L28 VCC13 VCCD_LVDS0 B26 +1.5VS
P10 VTT18 VCCSM18 AM25 K28 VCC14 VCCD_LVDS1 B25
0.1U_0402_16V4Z
N10 VTT19 VCCSM19 AL25 J28 VCC15 VCCD_LVDS2 A25 1 1 1 1 1 1
C182
C185
C38
C40
4.7U_0805_10V4Z
2.2U_0603_6.3V4Z
C249
K10 VTT21 VCCSM21 AJ25 G28 VCC17 VCCA_LVDS A35 +2.5VS
C206
1 1 J10 VTT22 VCCSM22 AH25 Note : All VCCSM pin V27 VCC18 2 2 2 2 2 2
C217
C232
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L9 AE20 V1.8_DDR_CAP3 K27 BLM18PG600SN1_0603
VTT30 VCCSM30 VCC26
J9 VTT31 VCCSM31 AE19 1 1 1 J27 VCC27 VCCA_SM0 AF20 2 1
C248
C246
C239
0.1U_0402_16V4Z
N8 VTT32 VCCSM32 AE18 H27 VCC28 VCCA_SM1 AP19
+1.5VS_PCIE +1.5VS
100U_D2_6.3VM
0.1U_0402_16V4Z
M8 AE17 K26 AF19 1 L1
VTT33 VCCSM33 VCC29 VCCA_SM2 BLM18PG600SN1_0603
N7 VTT34 VCCSM34 AE16 H26 VCC30 VCCA_SM3 AF18 1 1
2 2 2
C222
M7 AE15 K25 + 2 1
VTT35 VCCSM35 VCC31
C44
C243
0.47U_0603_16V7K
0.1U_0402_16V4Z
N6 VTT36 VCCSM36 AE14 J25 VCC32 VCC3G0 AE37
+1.5VS_3GPLL +1.5VS
10U_0805_6.3V6M
10U_0805_6.3V6M
0.22U_0603_10V7K
M6 AP13 K24 W37 R13 L3
VTT37 VCCSM37 VCC33 VCC3G1 2 2 2
220U_D2_4VM
A6 AN13 K23 U37 1 0.5_0805_1% BLM18PG600SN1_0603 1
VTT38 VCCSM38 VCC34 VCC3G2
N5 VTT39 VCCSM39 AM13 Note: Place near chip. K22 VCC35 VCC3G3 R37 1 1 1 1 23GRLL_R2 1
10U_0805_6.3V6M
+
C547
C16
C17
C18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 M5 VTT40 VCCSM40 AL13 K21 VCC36 VCC3G4 N37
C65
C28
M4 VTT42 VCCSM42 AJ13 U20 VCC38 VCC3G6 J37 1 1 1
2 2 2 2
C21
C C
N3 VTT43 VCCSM43 AH13 T20 VCC39
2
C193
C194
M3 VTT44 VCCSM44 AG13 K20 VCC40
N2 VTT45 VCCSM45 AF13 V19 VCC41 2 2 2
10U_0805_6.3V6M
10U_0805_6.3V6M
C236
C35
N1 AM12 + V18 L2
VTT49 VCCSM49 VCC45 CHB1608U301_0603
M1 VTT50 VCCSM50 AL12 T18 VCC46
G1 VTT51 VCCSM51 AK12 K18 VCC47 VCCA_3GBG F37 2 1
2 2 2
VCCSM52 AJ12 K17 VCC48 VSSA_3GBG G37 1 1
1 1 1 VCCSM53 AH12
C245
C244
C254
0.47U_0603_16V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.1U_0402_16V4Z
VCCSM58 AC11 +1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19
VCCSM59 AB11 +1.5VS_MPLL AA2 VCCA_MPLL C220 2
VCCSM60 AB10
VCCSM61 AB9 1 1 0.022U_0402_16V7K
+2.5VS
C221
AP8 V1.8_DDR_CAP6 ALVISO_BGA1257
VCCSM62 V1.8_DDR_CAP4
VCCSM63 AM1
V1.8_DDR_CAP3
Route VSSA3GBG gnd from GMCH to
VCCSM64 AE1
2 2 decoupling cap ground lead and
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_6.3V6M
ALVISO_BGA1257
then connect to the gnd plane.
@ 1 1 1
C216
C214
C215
+1.8V CRTDAC: Route caps within
L6 +1.5VS_DPLLA 250mil of Alviso. Route FB 2 2 2
CHB1608U301_0603
+VCCP within 3" of Alviso.
+1.5VS 1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
B B
0.1U_0402_16V4Z
C211
C235
C234
C199
C198
1
C209
C205 +
470U_D2_2.5VM 2 2 2 2 2 2 C542 C543 C544 C545 C546
connect to the gnd plane.
2 2 2 2 2
2 2
10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10U_0805_6.3V6M 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1
1 1 1 R714
C186
C250
+ + +
C242
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(4 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 10 of 43
5 4 3 2 1
5 4 3 2 1
D D
L12 VTT_NCTF17 VCCSM_NCTF31 AB12
M12 VTT_NCTF16 VCCSM_NCTF30 AC12
N12 VTT_NCTF15 VCCSM_NCTF29 AD12
P12 VTT_NCTF14 VCCSM_NCTF28 AB13
R12 VTT_NCTF13 VCCSM_NCTF27 AC13
T12 VTT_NCTF12 VCCSM_NCTF26 AD13
U12 VTT_NCTF11 VCCSM_NCTF25 AC14
V12 VTT_NCTF10 VCCSM_NCTF24 AD14
W12 VTT_NCTF9 VCCSM_NCTF23 AC15
L13 AD15 U5I U5J
VTT_NCTF8 VCCSM_NCTF22
M13 VTT_NCTF7 VCCSM_NCTF21 AC16
N13 VTT_NCTF6 VCCSM_NCTF20 AD16 Y1 VSS271 AL24 VSS267
P13 VTT_NCTF5 VCCSM_NCTF19 AC17 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
R13 VTT_NCTF4 VCCSM_NCTF18 AD17 G2 VSS269 A26 VSS265 VSS66 AD32
T13 VTT_NCTF3 VCCSM_NCTF17 AC18 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
U13 VTT_NCTF2 VCCSM_NCTF16 AD18 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33
VCCSM_NCTF13 AC20 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
VCCSM_NCTF12 AD20 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
AA12
Y13
AA13
L14
M14
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
AD21
AC22
AD22
AC23
AD23
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VSS_NCTF63 VCCSM_NCTF6 VSS250 VSS184 VSS122 VSS54
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
C C
W14 VSS_NCTF56 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
Y14 VSS_NCTF55 VCC_NCTF78 L17 +VCCP P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
AA14 VSS_NCTF54 VCC_NCTF77 M17 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
AB14 VSS_NCTF53 VCC_NCTF76 N17 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
L15 VSS_NCTF52 VCC_NCTF75 P17 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
M15 T17 AN4 K16 G29 AB34
NCTF
ALVISO_BGA1257
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Alviso(5 of 5) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 11 of 43
5 4 3 2 1
A B C D E
+1.8V +1.8V
+1.8V +1.8V DDR_A_D[0..63]
V_DDR_MCH_REF <8> DDR_A_D[0..63]
V_DDR_MCH_REF <7> DDR_A_DM[0..7]
<8> DDR_A_DM[0..7]
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1 1 JP44
C562 1 2 DDR_A_DQS[0..7]
C563 VREF VSS DDR_A_D4 <8> DDR_A_DQS[0..7]
3 VSS DQ4 4 1 1
1 220P_0402_50V7K 220P_0402_50V7K DDR_A_D0 5 6 DDR_A_D5 DDR_A_MA[0..13] 1
2 2 DQ0 DQ5 <8> DDR_A_MA[0..13]
C564
C565
DDR_A_D1 7 8
DQ1 VSS DDR_A_DM0 DDR_A_DQS#[0..7]
9 VSS DM0 10 <8> DDR_A_DQS#[0..7]
DDR_A_DQS#0 2 2
11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6 Layout Note:
DQS0 DQ6 DDR_A_D7
15 16
DDR_A_D2 17
VSS DQ7
18 +1.8V Place near DIMM
+1.8V +1.8V DDR_A_D3 DQ2 VSS DDR_A_D12
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
1 1 DDR_A_D9 25 26 DDR_A_DM1
C566 DQ9 DM1
27 VSS VSS 28 1 1 1 1 1
C567 DDR_A_DQS#1 29 30 M_CLK_DDR0 C568 C569 C570 C571 C572
DQS1# CK0 M_CLK_DDR0 <7>
220P_0402_50V7K 220P_0402_50V7K DDR_A_DQS1 31 32 M_CLK_DDR#0
2 2 DQS1 CK0# M_CLK_DDR#0 <7>
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
33 VSS VSS 34
DDR_A_D10 DDR_A_D14 2 2 2 2 2
35 DQ10 DQ14 36
DDR_A_D11 37 38 DDR_A_D15 +1.8V
DQ11 DQ15
39 VSS VSS 40
@ 10U_0805_10V4Z @ 10U_0805_10V4Z @ 10U_0805_10V4Z
+1.8V
1 1 1 1 1 1 1
41 42 C573 C574 C575 C576 C577 C578 C579
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 DDR_A_D17 45 46 DDR_A_D21
C580 DQ17 DQ21 2 2 2 2 2 2 2
47 VSS VSS 48 1 1 1 1
C581
C582
C583
C584
DDR_A_DQS#2 49 50 @ 10U_0805_10V4Z @ 10U_0805_10V4Z @ 10U_0805_10V4Z @ 10U_0805_10V4Z
220P_0402_50V7K DDR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52
2
53 VSS VSS 54
DDR_A_D18 DDR_A_D22 2 2 2 2
55 DQ18 DQ22 56
DDR_A_D19 57 58 DDR_A_D23
DQ19 DQ23
59 VSS VSS 60
DDR_A_D24 61 62 DDR_A_D28
DDR_A_D25 DQ24 DQ28 DDR_A_D29 +1.8V
63 64
2 0304 EMI DDR_A_DM3
65
DQ25
VSS
DQ29
VSS 66
DDR_A_DQS#3
2
67 DM3 DQS3# 68
69 70 DDR_A_DQS3 1 1
NC DQS3
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D30 + +
DDR_A_D27 DQ26 DQ30 DDR_A_D31 C585 C586
75 DQ27 DQ31 76
77 78 150U_D2_6.3VM 150U_D2_6.3VM
DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA 2 2
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7 +1.8V
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4 1 1 1 1 1 1 1 1 1
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0 C587 C588 C589 C590 C591 C592 C593 C594 C595
A1 A0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
103 VDD VDD 104
DDR_A_MA10 DDR_A_BS#1 2 2 2 2 2 2 2 2 2
105 A10/AP BA1 106 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA# 0.1U_0402_16V4Z
<8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120 +0.9VS
<7> M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
127 VSS VSS 128
3 DDR_A_DQS#4 DDR_A_DM4 3
129 DQS4# DM4 130
DDR_A_DQS4 131 132 1 1 1 1 1 1 1 1 1 1 1 1 1
DQS4 VSS DDR_A_D38
133 VSS DQ38 134
DDR_A_D34 135 136 DDR_A_D39
DDR_A_D35 DQ34 DQ39
137 DQ35 VSS 138
DDR_A_D44 2 2 2 2 2 2 2 2 2 2 2 2 2
139 VSS DQ44 140
C596
C597
C598
C599
C600
C601
C602
C603
C604
C605
C606
C607
C608
DDR_A_D40 141 142 DDR_A_D45
DDR_A_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150 Layout Note:
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 153
DQ42 DQ46
154 DDR_A_D47 Place one cap close to every 2 pullup
DQ43 DQ47
155 VSS VSS 156 resistors terminated to +0.9VS
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 162 +0.9VS
VSS VSS M_CLK_DDR1
163 NC,TEST CK1 164 M_CLK_DDR1 <7>
165 166 M_CLK_DDR#1 R645 1 2 56_0402_5% DDR_A_MA0 Layout Note:
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168 R646 1 2 56_0402_5% DDR_A_MA1 Place these resistor
DDR_A_DQS6 DQS6# VSS DDR_A_DM6 DDR_A_MA2 R647 1
169 DQS6 DM6 170 2 56_0402_5% closely DIMM0,all
171 172 DDR_A_MA4 R648 1 2 56_0402_5% R649 1 2 56_0402_5% DDR_A_MA3
DDR_A_D50 VSS VSS DDR_A_D54 R650 1 trace length<750 mil
173 DQ50 DQ54 174 2 56_0402_5% DDR_A_MA6
DDR_A_D51 175 176 DDR_A_D55 DDR_A_MA5 R651 1 2 56_0402_5%
DQ51 DQ55 DDR_A_MA8 R652 1
177 VSS VSS 178 2 56_0402_5% R653 1 2 56_0402_5% DDR_A_MA7
DDR_A_D56 179 180 DDR_A_D60 R654 1 2 56_0402_5% DDR_A_MA9
DDR_A_D57 DQ56 DQ60 DDR_A_D61 DDR_A_MA10 R655 1
181 DQ57 DQ61 182 2 56_0402_5%
183 184 DDR_A_MA11 R656 1 2 56_0402_5% R657 1 2 56_0402_5% DDR_A_MA12
DDR_A_DM7 VSS VSS DDR_A_DQS#7 R658 1 DDR_A_MA13
185 DM7 DQS7# 186 2 56_0402_5%
187 188 DDR_A_DQS7 DDR_A_BS#0 R659 1 2 56_0402_5% Layout Note:
DDR_A_D58 VSS DQS7 DDR_A_BS#2 R660 1
189 DQ58 VSS 190 2 56_0402_5% R661 1 2 56_0402_5% DDR_A_BS#1 Place these resistor
DDR_A_D59 191 192 DDR_A_D62 R662 1 2 56_0402_5% DDR_A_WE#
4 DQ59 DQ62 DDR_A_D63 DDR_A_RAS# R663 1
closely DIMM0,all 4
193 VSS DQ63 194 2 56_0402_5%
CK_SDATA 195 196 DDR_CKE0_DIMMA R664 1 2 56_0402_5% R665 1 2 56_0402_5% DDR_A_CAS# trace length
<16> CK_SDATA SDA VSS Max=1.3"
CK_SCLK 197 198 R666 1 2 10K_0402_5% R667 1 2 56_0402_5% DDR_CS0_DIMMA#
<16> CK_SCLK SCL SAO
+3VS 199 200 R668 1 2 10K_0402_5% DDR_CKE1_DIMMA R669 1 2 56_0402_5%
VDDSPD SA1 M_ODT1 R670 1 DDR_CS1_DIMMA#
2 56_0402_5% R671 1 2 56_0402_5%
1 2 R672 1 2 56_0402_5% M_ODT0
C609 FOX_ASOA426-M4R-TR
0.1U_0402_16V4Z CONN@ Compal Electronics, Inc.
Title
DDR2-SODIMM SLOT0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3361P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 12 of 43
A B C D E
5 4 3 2 1
C 1
B E 2 3
2222 SYMBOL(SOT23-NEW)
D D
+3VS
2
C1449
0.1U_0402_16V4Z
1
U40
H_THERMDA 1 8 SMB_EC_CK2
<4> H_THERMDA VDD SCLK
1
2 7 SMB_EC_DA2
C1450 D+ SDATA
H_THERMDC 2200P_0402_50V7K 3 6
<4> H_THERMDC 2 D- ALERT#
THERM# 4 5
THERM# GND
C R1919 C
+3VS 1 2 ADM1032AR_SOP8
10K_0402_5%
JP50
1
1 1 1
1
B D38 C1451 C1452 B
2
R2011 RB751V_SOD323 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200
@ 10K_0402_5% 2 2 CONN@
2
2
+3VS FAN
1
2
5
6
1
5
2
INA
G
TC7SH00FU_SSOP5
3
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Thermal sensor and Fan Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 13 of 43
5 4 3 2 1
5 4 3 2 1
+LCDVDD
1 1
C12 C13
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
D D
LVDS connector
JP3
C1534
C1535
LVDSB1+ DISPLAYOFF#
<9> LVDSB1+ 29 30
LVDSB1- DAC_BRIG
<9> LVDSB1- 31 32 DAC_BRIG <29>
LCDP_CLK +LCDVDD
LVDSB2+ 33 34 LCDP_DAT +LCDVDD +3VS
<9> LVDSB2+ 35 36
LVDSB2- +5VALW
<9> LVDSB2- 37 38
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
39 40
1 8/18
1
1
ACES_88107-4000G
S
1 3
D
C CONN@ R102 C
2
Q1
2
2
2 100_0402_5% R8 SI2301BDS_SOT23
G
2
C1536
C1537
47K_0402_5%
2
0809 Change pin define
1
1
D
0711 EMI request Q3 2
0711 EMI request 2N7002_SOT23 G
1
S
3
1 1
R2016 C2
1 2 2 C1532 C31
<9> EN_LCDVDD
4.7U_0805_10V4Z 4.7U_0805_10V4Z
0_0402_5% 0.047U_0402_16V7K 2 2
B+ INVPWR_B+ Q2
C1551 DTC124EK_SC59
3
L34 1 2 0_0805_5% 8/18
8/18 @ 0.01U_0402_16V7K
@ L35
1 2
FBMA-L11-201209-221LMA30T_0805
B B
+3VS
1
R14 R10
2.2K_0402_5% 2.2K_0402_5%
2006/08/09 +3VS
Q5
2
BSS138_SOT23 R1
2
+3VALW C117 @ 1 2
R9 <29> INVT_PWM
S
+2.5VS U13A
G
2
1
100K_0402_5%
5
LCD EEPROM 1 U1
P
<9,29> BK_EN A
3 DISPLAYOFF# R2
P
O
2
G
2 1 2 2 4 INVTPWM
<29> BKOFF# B <9> BIA A Y
G
G
3 1 LCDP_DAT @ SN74LVC08APW_TSSOP14 0_0402_5%
<9> LCD_DAT
7
@ NC7SZ14M5X_SOT23-5
S
3
2 1
BSS138_SOT23 R22 @ 100K_0402_5%
Q6 R2014
1 2
0_0402_5%
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
LVDS connector Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 14 of 43
5 4 3 2 1
5 4 3 2 1
1
D D21 D22 D23 D
DAN217_SC59DAN217_SC59DAN217_SC59
3
CRT_VCC
@ @ @
JP45
MSEN# SUYIN_070112FR015S222XU
<29> MSEN#
6
11
CRT_RED L26 1 2 BK2125LL121_0805 CRTL_R 1
<9> CRT_RED
7
SMBDAT 12 16
CRT_GRN L27 1 2 BK2125LL121_0805 CRTL_G 2 17
<9> CRT_GRN
8
13
CRT_BLU L28 1 2 BK2125LL121_0805 CRTL_B 3
<9> CRT_BLU
9
1
1 1 1 1 1 1 14
+5VS C610 C611 C612 C613 C614 C615 4
R673 R674 R675 10
75_0402_1% 75_0402_1% 75_0402_1% SMBCLK 15
2 2 2 2 2 2
5
2
5
OE#
C 74AHCT1G125GW_SOT353-5 L30 C
3
C616 +5VS
0.1U_0402_16V4Z
2
1 1 1
5
2
U36 C617 C618 C619
D24 D25
P
OE#
1
+2.5VS
B +5VS R_CRT_VCC CRT_VCC B
D26 F1
2 1 1 2
1
RB411D_SOT23 1A_6VDC_MINISMDC110
1 R676 R677
R679
C620 2.2K_0402_5% 2.2K_0402_5%
0.1U_0402_16V4Z R680 4.7K_0402_5%
2
2 Q44
2N7002_SOT23
4.7K_0402_5%
SMBDAT CRT_SMBDAT
S
1 3 CRT_SMBDAT <9>
Q45
G
2
2N7002_SOT23
SMBCLK CRT_SMBCLK
S
1 3 CRT_SMBCLK <9>
G
2
1 1
C621 C622
220P_0402_25V8K 220P_0402_25V8K
2 2
A A
+3VS
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
CRT Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3361P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 15 of 43
5 4 3 2 1
5 4 3 2 1
+3VS +CK_VDD_MAIN
L31
+3VS
0.1U_0402_16V4Z
1 2
10K_0402_5%
10K_0402_5%
KC FBM-L11-201209-221LMAT_0805 2 1 1 1 1 CLK_MCH_BCLK 2 1
1
1 C483 C478 R332 49.9_0402_1%
C432 C473 C435 0.047U_0402_16V4Z CLK_MCH_BCLK# 2 1
R330
R349
C474
0713 EMI Request 10U_0805_10V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z R333 49.9_0402_1%
1 2 2 2 2 CLK_CPU_BCLK 2 1
2 R321 49.9_0402_1%
2
CLK_CPU_BCLK# 2 1
ICH_SMBDATA CK_SDATA R322 49.9_0402_1%
S
<19> ICH_SMBDATA 1 3 CK_SDATA <12>
Q36 CLK_ITP 2 1
2N7002_SOT23 R319 49.9_0402_1%
CLK_ITP# 2 1
Place near each pin
G
2
R320 49.9_0402_1%
D D
+3VS
L32
+CK_VDD_MAIN2 W>40 mil
2
G
1 2
Q38 KC FBM-L11-201209-221LMAT_0805 CLK_PCIE_ICH 1 2
<19> ICH_SMBCLK
ICH_SMBCLK 1 3 2N7002_SOT23 CK_SCLK
CK_SCLK <12>
2
C469
1 1
Place near ICS954226 R420 49.9_0402_1%
C429 C477 CLK_PCIE_ICH# 1 2
S
0713 EMI Request 10U_0805_10V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z R421 49.9_0402_1%
1 2 2 CLK_MCH_3GPLL 1 2
0.047U_0402_16V4Z
D R367 R345 49.9_0402_1%
CK_VDD_A CK_VDD_48 CK_VDD_REF 2.2_0603_5% CLK_MCH_3GPLL# 1 2
0.047U_0402_16V4Z
1 1 1 1 1 1 1 2 CK_VDD_A R346 49.9_0402_1%
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.047U_0402_16V4Z
U28
G 2 3 S
C444
C434
C460
21 VDDPCIEX_0
2 2 2 2 2 R390 49.9_0402_1%
28 VDDPCIEX_1 VDDA 37
C475
C433
34 SSC_DREFCLK 1 2
2N7002 VDDPCIEX_2
GNDA 38 R391 49.9_0402_1%
1 SSC_DREFCLK# 1 2
VDDPCI_0
7 VDDPCI_1
55 H_STP_PCI# DREFCLK R418
1 2 49.9_0402_1%
PCI/SRC_STOP# H_STP_PCI# <19>
0 0 1 for Dothan-B 533Mhz Place crystal within 54 H_STP_CPU# DREFCLK# 1 2
CPU_STOP# H_STP_CPU# <19,37>
R419 49.9_0402_1%
1 0 1 for Dothan-B 400Mhz C428
500 mils of CKGEN
42 VDDCPU
33P_0402_50V8J 1 2CK_VDD_REF
48 VDDREF
2 1 CK_XTAL_IN R338
1_0603_5% 41 CK_CPU1 1 2 CLK_MCH_BCLK
FSC FSB FSA CPU SRC PCI CPUCLKT1 CLK_MCH_BCLK <7>
1
X1 14.318MHZ_20P_1BX14318BE1A 1 2CK_VDD_4811 R356 33_0402_5%
R368 VDD48 CK_CPU1# CLK_MCH_BCLK#
CLKSEL0 CLKSEL1 CLKSEL2 MHz MHz MHz CPUCLKC1 40 1 2 CLK_MCH_BCLK# <7>
2.2_0603_5% R357 33_0402_5%
C431 50
2
C 33P_0402_50V8J X1 C
0 0 0 266 100 33.3 CK_XTAL_OUT CK_CPU0 CLK_CPU_BCLK
2 1 49 X2 CPUCLKT0 44 1 2 CLK_CPU_BCLK <4>
R341 33_0402_5%
0 0 1 133 100 33.3 43 CK_CPU0# 1 2 CLK_CPU_BCLK#
* <19> CLK_48M_ICH
CLK_48M_ICH
CLKSEL0
R415 2 1 33_0402_5% CLKSEL2 12
53
FS_A/USB_48MHz
REF1/FSLC/TEST_SEL
CPUCLKC0 R342 33_0402_5%
CLK_CPU_BCLK# <4>
0 1 0 200 100 33.3 PS: When CB714 unpop, R415 12 Ohm change to 33 Ohm
CLKSEL1 16 36 CK_CPU2 1 2 CLK_ITP
FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6 CLK_ITP <4>
0 1 1 166 100 33.3 R343 @ 33_0402_5%
35 CK_CPU2# 1 2 CLK_ITP#
CPUCLKC2_ITP/PCIEXC6 CLK_ITP# <4>
R344 @ 33_0402_5%
1 0 0 333 100 33.3 CLK_33M_CBS 2 1 PCICLK5 5
<23> CLK_33M_CBS PCICLK5
R375 33_0402_5%
4 PCICLK4 PEREQ1#/PCIEXT5 33
1 0 1 100 100 33.3 CLK_33M_MPCI PCICLK3
<24> CLK_33M_MPCI 2 1 3 PCICLK3 PEREQ2#/PCIEXC5 32
R377 33_0402_5%
1 1 0 400 100 33.3 56 PCICLK2/REQ_SEL
PCIEXT4 31
CLK_33M_ICH 2 1 PCICLKF1 9
<17> CLK_33M_ICH SELPCIEX_LCDCLK#/PCICLK_F1
1 1 0 RESERVED R379 33_0402_5% 30
CLK_33M_LPCEC PCIEXC4
<29> CLK_33M_LPCEC 2 1
Table : ICS 954226 R376 33_0402_5%
+3VS 1 2 PCICLKF0 8 26
R385 10K_0402_5% ITP_EN/PCICLK_F0 SATACLKT
CK_SCLK 46 27
SCLK SATACLKC
19 SRC1 1 2 CLK_PCIE_ICH
4.7K_0402_5% 1K_0402_5% PCIEXT1 CLK_PCIE_ICH <19>
R410 33_0402_5%
1 2 20 SRC1# 1 2 CLK_PCIE_ICH#
<5> CPU_BSEL0 PCIEXC1 CLK_PCIE_ICH# <19>
13 R411 33_0402_5%
GND_0
2
R339 +3VS
0_0402_5% R340 29 17 SRC0 1 2 SSC_DREFCLK
GND_1 LCDCLK_SS/PCIEX0T SSC_DREFCLK <7>
R382 33_0402_5%
2
1
R416 R398
2
@ 10K_0402_5% 10K_0402_5%
<19,37> VGATE
R401
1
2
10K_0402_5% 10
VTT_PWRGD#/PD
R400
1
1
CLKREF CLK_14M_ICH D
REF0 52 1 2 CLK_14M_ICH <19>
CLKSEL1 2 1 R355 33_0402_5% 2
MCH_CLKSEL1 <7>
1 2 CLK_14M_SIO Q42 G
CLK_14M_SIO <29>
ICS954226AGT_TSSOP56 R2010 33_0402_5% 2N7002_SOT23 S
3
A 1K_0402_5% A
<5> CPU_BSEL1 1 2 Table : ICS 954226
R394
2
0_0402_5%
R395
@ 10K_0402_5%
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
Clock Generator Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 16 of 43
5 4 3 2 1
5 4 3 2 1
14
F3 AD[4] REQ[2]# M5 PCI_REQ2# <23>
D PCI_AD5 PCI_GNT2# U13D D
E9 AD[5] GNT[2]# F1 PCI_GNT2# <23>
PCI_AD6 F2 B8 PCI_REQ3# 12
P
PCI_AD7 AD[6] REQ[3]# A
D6 AD[7] GNT[3]# C8 O 11
RP43 PCI_AD8 E6 F7 PCI_REQ4# 13
AD[8] REQ[4]#/GPI[40] B
G
PCI_AD9 D3 E7
+3VS PCI_PERR# PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQ5# @ SN74LVC08APW_TSSOP14
1 8 A2 E8
7
PCI_DEVSEL# PCI_AD11 AD[10] REQ[5]#/GPI[1]
2 7 D2 AD[11] GNT[5]#/GPO[17] F6
3 6 PCI_PLOCK# PCI_AD12 D5 B7 EC_SCI#
AD[12] REQ[6]#/GPI[0] EC_SCI# <29>
4 5 PCI_IRDY# PCI_AD13 H3 D8
PCI_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14]
8.2K_0804_8P4R_5% PCI_AD15 J5 J6 PCI_C_BE0#
AD[15] C/BE[0]# PCI_C_BE0# <23,24> +3VALW
RP44 PCI_AD16 K2 H6 PCI_C_BE1#
AD[16] C/BE[1]# PCI_C_BE1# <23,24>
PCI_AD17 PCI_C_BE2#
14
K5 AD[17] C/BE[2]# G4 PCI_C_BE2# <23,24>
+3VS 1 8 PCI_PIRQC# PCI_AD18 D4 G2 PCI_C_BE3# U13B
AD[18] C/BE[3]# PCI_C_BE3# <23,24>
2 7 PCI_PIRQH# PCI_AD19 L6 PLTRST# 4 R63 33_0402_5%
P
PCI_PIRQD# PCI_AD20 AD[19] PCI_IRDY# A PCIRSTB2#
3 6 G3 AD[20] IRDY# A3 PCI_IRDY# <23,24> O 6 1 2 PLTRST_MCH# <7,21,23>
4 5 PCI_PIRQB# PCI_AD21 H4 E1 PCI_PAR 5
AD[21] PAR PCI_PAR <23,24> B
G
PCI_AD22 H2 R2 PCI_PCIRST#
8.2K_0804_8P4R_5% PCI_AD23 AD[22] PCIRST# PCI_DEVSEL#
H5 C3 PCI_DEVSEL# <23,24>
7
PCI_AD24 AD[23] DEVSEL# PCI_PERR# @ SN74LVC08APW_TSSOP14
B3 AD[24] PERR# E3 PCI_PERR# <23,24>
PCI_AD25 M6 C5 PCI_PLOCK#
PCI_AD26 AD[25] PLOCK# PCI_SERR#
B2 AD[26] SERR# G5 PCI_SERR# <23,24>
RP47 PCI_AD27 K6 J1 PCI_STOP# R48 2 1 0_0402_5%
AD[27] STOP# PCI_STOP# <23,24>
PCI_AD28 K3 J2 PCI_TRDY#
AD[28] TRDY# PCI_TRDY# <23,24>
1 8 PCI_PIRQA# PCI_AD29 A5
PCI_REQ4# PCI_AD30 AD[29] +3VALW
2 7 L1 AD[30]
3 6 PCI_PIRQG# PCI_AD31 K4
PCI_REQ1# AD[31] PLTRST#
14
4 5 PLTRST# R5
G6 CLK_33M_ICH U13C R61
PCICLK CLK_33M_ICH <16>
8.2K_0804_8P4R_5% PCI_FRAME# J3 P6 ICH_PME# PCI_PCIRST# 9 33_0402_5%
P
<23,24> PCI_FRAME# FRAME# PME# ICH_PME# <24,29> A
O 8PCIRSTB3# 1 2 PCIRST# <23,24,29>
RP48 Interrupt I/F 10 B
G
C PCI_PIRQA# PCI_PIRQE# C
N2 PIRQ[A]# PIRQ[E]#/GPI[2] D9 PCI_PIRQE# <24>
+3VS 1 8 PCI_REQ0# PCI_PIRQB# L2 C7 PCI_PIRQF#
PCI_PIRQF# <24>
7
PCI_PIRQF# PCI_PIRQC# PIRQ[B]# PIRQ[F]#/GPI[3] PCI_PIRQG# @ SN74LVC08APW_TSSOP14
2 7 <23> PCI_PIRQC# M1 PIRQ[C]# PIRQ[G]#GPI[4] C6
3 6 PCI_PIRQE# PCI_PIRQD# L3 M3 PCI_PIRQH# Change to DAU00 IRQ Setting
PCI_REQ3# PIRQ[D]# PIRQ[H]#/GPI[5]
4 5
RESERVED PCI_PIRQC# for Cardbus
8.2K_0804_8P4R_5% AC5 R49 2 1 0_0402_5%
8.2K_0402_5% SATA[1]RXN/RSVD[1]
1 2 R276 PCI_REQ2# AD5 SATA[1]RXP/RSVD[2] PCI_PIRQEF# for Mini PCI
AF4 SATA[1]TXN/RSVD[3]
AG4 SATA[1]TXP/RSVD[4]
AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
+3VS 8.2K_0402_5% 1 2 R244 PCI_REQ5# AF8
8.2K_0402_5% EC_SCI# SATA[3]TXN/RSVD[7]
1 2 R261 AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
+3VALW 1 2 ICH_PME#
R254 @ 10K_0402_1% ICH6_BGA609
CLK_33M_ICH
PME# signal has an integrated pull-up of 18 k to 42 k SA8280108G0 S IC 030 FW82801FBM B2 BGA 609P ICH6-M ->
SA8280108E0(R3)/SA8280108D0(R1) S IC 030 FW82801FBM QS ICH6-M BGA 609P
2
R264
@ 10_0402_5%
1
1
C348
@ 8.2P_0402_50V
2
B B
A A
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
ICH6(1/4) Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
Custom LA-3361P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 17 of 43
5 4 3 2 1
5 4 3 2 1
C115
15P_0402_50V8J
+RTCVCC 2 1 ICH_RTCX1
Y2
10M_0402_5%
1
2 NC IN 1
1
R65
R69 3 4
D NC OUT U9A D
LPC_LAD[0..3] <29>
1M_0402_5% 32.768KHZ_12.5P_1TJS125DJ2A073 C113
2
15P_0402_50V8J Y1 P2 LPC_LAD0 H_FERR# close as ICH6 0.5"+VCCP
2
RTCX1 LAD[0]/FWH[0]
RTC
INTRUDER# 2 1 ICH_RTCX2 Y2 N3 LPC_LAD1
RTCX2 LAD[1]/FWH[1] LPC_LAD2 R203
LAD[2]/FWH[2] N5
1 2 ICH_RTCRST# AA2 N4 LPC_LAD3 56_0402_5%
LPC
+RTCVCC +RTCVCC RTCRST# LAD[3]/FWH[3]
R67 H_FERR# 2 1
20K_0402_5% INTRUDER# AA3 N6 LPC_LDRQ0#
+3VALW INTRUDER# LDRQ[0]# LPC_LDRQ0# <29>
6/21 INTVRMEN AA5 P4 R202
JOPEN1 INTVRMEN LDRQ[1]#/GPI[41] @ 56_0402_5%
1
LAN
0.1U_0402_16V4Z AT93C46-10SI-2.7_SO8 LAN_JCLK CPUSLP# R45 1 @ 0_0402_5% H_CPUSLP#
CPU
<22> LAN_JCLK F12 LAN_CLK CPUSLP# AE27 2 H_CPUSLP# <4,7>
1
2
R50 LAN_RSTSYNC B11 AE24 H_DPRSLP#
<22> LAN_RSTSYNC LAN_RSTSYNC DPRSLP#/TP[4] H_DPRSLP# <4>
0_0402_5% AD27 H_DPSLP#
DPSLP#/TP[2] H_DPSLP# <4>
<22> LAN_RXD0 LAN_RXD0 E12
LAN_RXD1 LANRXD[0] H_FERR#
<22> LAN_RXD1 E11 AF24 H_FERR# <4> MAINPWON <34,38>
2
1
LAN_TXD0 C12 @ 330_0402_5% C
<22> LAN_TXD0 LANTXD[0]
LAN_TXD1 C11 AG26 H_IGNNE# 1 2 2 Q21
<22> LAN_TXD1 LANTXD[1] IGNNE# H_IGNNE# <4> +VCCP B
LAN_TXD2 E13 AE22 @ 2SC2411K_SOT23
<22> LAN_TXD2 LANTXD[2] INIT3_3V#
AF27 H_INIT# 1 2 E
EMI H_INIT# <4>
3
C623 2 INIT#
1 1 R697 210_0402_5% INTR AG24 H_INTR
H_INTR <4>
@ C264
EEP_SK <25> AC97_BITCLK @ 10P_0402_25V8K AC97_BITCLK C10 @ 1U_0603_10V4Z
ACZ_BIT_CLK
AC-97/AZALIA
<25> AC97_SYNC AC97_SYNC B9 AD23 KBRST# 1 2 H_THERMTRIP#
ACZ_SYNC RCIN# KBRST# <29> +VCCP
1
C R194 C
R80 33_0402_5% 2 R703 1 AC97RST#A10 AF25 H_NMI 75_0402_5%
<25> AC97_RST# ACZ_RST# NMI H_NMI <4>
AG27 H_SMI#
SMI# H_SMI# <4>
20K_0402_5% AC97_SDIN0 F11
<25> AC97_SDIN0 ACZ_SDIN[0] <4,7> H_THERMTRIP#
F10 AE26 H_STPCLK#
H_STPCLK# <4>
2
ACZ_SDIN[1] STPCLK#
B10 ACZ_SDIN[2]
AE23 THRMTRIP_ICH# 1 2 R201 H_THERMTRIP#
AC97_SDOUT THRMTRIP# 56_0402_5%
<25> AC97_CODEC_SDOUT 1 2 C9 ACZ_SDO
R6 33_0402_5% R201 place within 2" from ICH
AC16 IDE_HDA0
Check list rev1.701 DA[0] IDE_HDA1
IDE_HDA0 <21> R194 place within 2" from R201
AC19 SATALED# DA[1] AB17 IDE_HDA1 <21>
AC17 IDE_HDA2
DA[2] IDE_HDA2 <21>
LAN_TXD0 AE3 AD16 IDE_HDCS1#
SATA[0]RXN DCS1# IDE_HDCS1# <21>
LAN_TXD1 AD3 AE17 IDE_HDCS3#
SATA[0]RXP DCS3# IDE_HDCS3# <21>
LAN_TXD2 AG2 SATA[0]TXN
33_0402_5%
R2025 2
33_0402_5%
33_0402_5%
AD14 IDE_HDD0
DD[0]
SATA
AD7 AF15 IDE_HDD1
SATA[2]RXN DD[1]
PIDE
R2023
1R2024
33P_0402_50V8J
C1555
33P_0402_50V8J
C1556
33P_0402_50V8J
2 2 2 IDE_HDD9
AG11 SATARBIAS# DD[9] AF13
R187 R190 AF11 AB12 IDE_HDD10
@ 4.7K_0402_5% @ 8.2K_0402_5% SATARBIAS DD[10] IDE_HDD11
DD[11] AB13
AC13 IDE_HDD12
DD[12] IDE_HDD13
AE15
2
DD[13] IDE_HDD14
DD[14] AG15
B IDE_HIORDY IDE_HIRQ IDE_HIORDY IDE_HDD15 B
<21> IDE_HIORDY AF16 IORDY DD[15] AD13
IDE_HIRQ AB16
<21> IDE_HIRQ IDEIRQ
IDE_HDACK# AB15
<21> IDE_HDACK# DDACK#
IDE_HDIOW# AC14 AB14 IDE_HDREQ
<21> IDE_HDIOW# DIOW# DDREQ IDE_HDREQ <21>
IDE_HDIOR# AE16
<21> IDE_HDIOR# DIOR#
ICH6_BGA609
9/05
+3VLP
+RTCVCC
JP55
D42
1
2
R1923
BATT1.1
+ - BATT1
3 1 2 1 + - 2
W=20mils
2 DAN202U_SC70 1K_0402_5%
A A
+3VALW +3VALW
+3VALW
2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
+3VS
10K_0402_5%
1
RP2
R291
R289
R292
R290
1 8
R272
Reserve 2 7
1
3 6
1
Inform BIOS team 4 5
2
D U9C D
ICH_SMBDATA @ 10K_1206_8P4R_5% ICH_RI# T2 H25
<16> ICH_SMBDATA RI# PERn[1] PAD T31
ICH_SMBCLK RP1 H24
<16> ICH_SMBCLK PERp[1] PAD T33
ICH_SMLINK0 1 8 AF17 G27
SATA[0]GP/GPI[26] PETn[1] PAD T32
ICH_SMLINK1 2 7 AE18 G26
SATA[1]GP/GPI[29] PETp[1] PAD T34
3 6 AF18 SATA[2]GP/GPI[30]
+3VS 4 5 AG18 K25
SATA[3]GP/GPI[31] PERn[2]
PERp[2] K24
100_1206_8P4R_5%ICH_SMBCLK Y4 J27
SMBCLK PETn[2]
1
ICH_SMBDATA W5 J26
PCI-EXPRESS
LINKALERT# SMBDATA PETp[2]
Y5 LINKALERT#
R209 ICH_SMLINK0 W4 M25
SMLINK[0] PERn[3]
GPIO
8.2K_0402_5% ICH_SMLINK1 U6 M24
MCH_SYNC# SMLINK[1] PERp[3]
AG21 L27
2
R6 U27 DMI_TXN1
<29> LID_SWOUT# GPI[13] DMI[1]TXN DMI_TXN1 <7>
2
U26 DMI_TXP1
DMI[1]TXP DMI_TXP1 <7>
R238 R186 H_STP_PCI# AC21
<16> H_STP_PCI# STP_PCI#/GPO[18]
Y25 DMI_RXN2
C DMI[2]RXN DMI_RXN2 <7> C
@ 10_0402_5% @ 10_0402_5% SB_INT_FLASH_SEL# AB21 Y24 DMI_RXP2
<30> SB_INT_FLASH_SEL# DMI_RXP2 <7>
1
CLOCK
A27 CLK48 USBP[0]N C21 USBP0- <28>
T35 D21 USBP0+
USBP[0]P USBP0+ <28>
PAD ICH_SUSCLK V6 A20 USBP1-
SUSCLK USBP[1]N USBP1- <28> +3VALW
B20 USBP1+
USBP[1]P USBP1+ <28>
SLP_S3# T4 D19 USBP2-
B <29> SLP_S3# SLP_S3# USBP[2]N B
SLP_S4# T5 C19 USBP2+ RP46
<29> SLP_S4# SLP_S4# USBP[2]P
USB
SLP_S5# T6 A18 USBP3- OVCUR#0 4 5
<29> SLP_S5# SLP_S5# USBP[3]N
B18 USBP3+ OVCUR#3 3 6
ICH_PWRGD USBP[3]P OVCUR#1
<29> ICH_PWRGD AA1 PWROK USBP[4]N E17 2 7
POWER MGT
D17 08/10 OVCUR#4 1 8
PM_DPRSLPVR USBP[4]P
<37> PM_DPRSLPVR AE20 DPRSLPVR/TP[1] USBP[5]N B16
A16 10K_1206_8P4R_5%
Support wake on LAN R70 @ ICH_BATLOW# USBP[5]P
V2 BATLOW#/TP[0] USBP[6]N C15
Support wake on LAN R71 0 ohm
R271 PWRBTN_OUT# U1
USBP[6]P D15
A14
06/23 change R to RP
<29> PWRBTN_OUT# PWRBTN# USBP[7]N
10K_0402_5% B14
LINKALERT# USBP[7]P
+3VALW 1 2 <23,29> RSMRST# 1 2 V5 LAN_RST#
R70 0_0402_5% A22 USBRBIAS 1 2
R66 RSMRST# USBRBIAS#
Y3 RSMRST# USBRBIAS B22 USBPN/USBPP impedance 45 Ohm
10K_0402_5% 1 2 R51
<29> EC_LANRST#
+3VALW 1 2 XDP_DBRESET# @ R71 0_0402_5% ICH6_BGA609 22.6_0402_1%
1
10K_0402_5%
10K_0402_5%
JP59
1
2
2
1
R284
R278
R64 PM_DPRSLPVR USBP3+ 2
8.2K_0402_5% USBP3- 2
3 3
+3VALW 1 2 ICH_BATLOW# +5VALW 4 4
1
5 5
R267 R208 USBP2- 6
680_0402_5% USBP2+ 6
7 7
+3VALW 1 2 ICH_PCIE_WAKE# 100K_0402_5% 8
SYSON# 8
<28,31> SYSON# 9 11
2
OVCUR#2 9 G11
1 2 10 10 G12 12
R2017 @ 0_0402_5%
OVCUR#3 1 2 ACES_87212-10G0
A R2018 @ 0_0402_5% 08/14 A
CONN@
Signal has integrated pull-down in ICH
May need pulldown for DPRSLPVR in case
R205 08/10 Add two USB port to subboard
10K_0402_5% the ICH6m does not set this value in time
+3VS 1 2 MCH_SYNC# for boot.
R211
10K_0402_5% Compal Electronics, Inc.
+3VS 1 2 SIRQ Title
ICH6(3/4)
8.2 k pull-up to Vcc3_3(CRB uses 10 k) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 19 of 43
5 4 3 2 1
5 4 3 2 1
+1.5VS
C322
@ 0.1U_0402_16V4Z
Near PIN F27(C968), +1.5VS
1 2
CORE
D15 VCC1_5[11] VCC1_5[88] 0.1U_0402_16V4Z VSS[162] VSS[76]
G23 VCC1_5[12] VCC1_5[87] M11 V27 VSS[161] VSS[75] D20
2
PCIE
C310 C309 L21 1 2 T27 C18
1U_0603_10V4Z 0.1U_0402_16V4Z C312 VCC1_5[21] VSS[152] VSS[66]
L22 VCC1_5[22] T26 VSS[151] VSS[65] C14
@0.1U_0402_16V4Z M21 AA10 +3VS C346 T23 B25
1 1 1 VCC1_5[23] VCC3_3[21] VSS[150] VSS[64]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M22 AG19 0.1U_0402_16V4Z T16 B24
VCC1_5[24] VCC3_3[20] VSS[149] VSS[63]
N21 VCC1_5[25] VCC3_3[19] AG16 2 2 1 2 T15 VSS[148] VSS[62] B23
C317
C323
N22 VCC1_5[26] VCC3_3[18] AG13 T14 VSS[147] VSS[61] B21
N23 AD17 C296 T13 B19
VCC1_5[27] VCC3_3[17] 0.1U_0402_16V4Z VSS[146] VSS[60]
N24 VCC1_5[28] VCC3_3[16] AC15
1 1 Near PIN T12 VSS[145] VSS[59] B15
N25 AA17 1 2 T1 B13
IDE
P21
VCC1_5[29] VCC3_3[15]
AA15 AG13, AG16 R4
VSS[144] VSS[58]
AG7
+5VALW +3VALW VCC1_5[30] VCC3_3[14] C305 VSS[143] VSS[57]
P25 VCC1_5[31] VCC3_3[13] AA14 R25 VSS[142] VSS[56] AG3
P26 AA12 0.1U_0402_16V4Z R24 AG22
D14 VCC1_5[32] VCC3_3[12] VSS[141] VSS[55]
P27 VCC1_5[33] 1 2 R23 VSS[140] VSS[54] AG20
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10_0402_5% T21 M7 2 2 2 0.01U_0402_16V7K R15 AG12
VCC1_5[36] VCC3_3[10] VSS[137] VSS[51]
C343
RB751V_SOD323 T22 VCC1_5[37] VCC3_3[9] L7 1 2 R14 VSS[136] VSS[50] AG1
C360
C354
U21 L4 R13 AF7
1
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P22 VSS[132] VSS[46] AF12
1U_0603_10V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
GROUND
W21 VCC1_5[42] VCC3_3[4] E4 P16 VSS[131] VSS[45] AF10
1 1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN 1 2 P15 VSS[130] VSS[44] AF1
Y21 A6 P14 AE7
Y22
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 Near PIN AA19 P13
VSS[129] VSS[43]
AE6
VCC1_5[45] VSS[128] VSS[42]
VCCSUS1_5[3] U7 P12 VSS[127] VSS[41] AE25
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 +1.5VALW N7 VSS[126] VSS[40] AE21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AB4 VCC1_5[47] N17 VSS[125] VSS[39] AE2
0.1U_0402_16V4Z
USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 +1.5VALW N15 VSS[123] VSS[37] AE11
0.1U_0402_16V4Z
AC4 VCC1_5[50] N14 VSS[122] VSS[36] AE10
+3VALW +1.5VALW
C333
C338
C342
AD4 VCC1_5[51] VCC1_5[78] G20 1 N13 VSS[121] VSS[35] AD6
1 2
AE4 VCC1_5[52] VCC1_5[77] F20 N12 VSS[120] VSS[34] AD24
U18 APL5301-15DC_3P 1
Near PIN AG5 AE5 VCC1_5[53] VCC1_5[76] E24 N11 VSS[119] VSS[33] AD2
SATA
AF5 VCC1_5[54] VCC1_5[75] E23 N1 VSS[118] VSS[32] AD18
2
C308
USB CORE
2 3 AG5 E22 M4 AD15
GND
0.1U_0402_16V4Z
L15 VSS[105] VSS[19] AB7
ICH6_VCCPLL AC27 AA18 ICH_V5REF_RUN 1 L13 AB2
VCCDMIPLL V5REF[2] VSS[104] VSS[18]
+3VS E26 VCC3_3[1] V5REF[1] A8 K7 VSS[103] VSS[17] AB19
B B
K27 VSS[102] VSS[16] AB10
0.1U_0402_16V4Z
C311
2 +3VS AG10 VCC3_3[22] K23 VSS[100] VSS[14] AA4
C278
0.1U_0402_16V4Z
Y7 +3VALW G12 A12
VCCSUS3_3[6] C320 VSS[88] VSS[2]
VCCSUS3_3[19] G16 1 G1 VSS[87] VSS[1] A1
A17 G15 @ 0.1U_0402_16V4Z
+3VALW VCCSUS3_3[7] VCCSUS3_3[18]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C316
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L11
Near PIN A17 C287
R184 1 1
CHB1608U301_0603 C331 0.1U_0402_16V4Z
1 2 1 2 ICH6_VCCPLL 1 2 1 2
+1.5VS
0.01U_0402_16V7K
2 2
C356
C353
0.1U_0402_16V4Z
C271
AC27 ICH6(4/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 20 of 43
5 4 3 2 1
A B C D E F G H
JP12
PLTRST_MCH# 44 43
<7,17,23> PLTRST_MCH# 44 43
IDE_HDD7 42 41 IDE_HDD8
IDE_HDD6 42 41 IDE_HDD9 JP21
40 40 39 39
1 IDE_HDD5 IDE_HDD10 1
38 38 37 37 1 2
IDE_HDD4 36 35 IDE_HDD11
IDE_HDD3 36 35 IDE_HDD12 PLTRST_MCH# 3 4 IDE_HDD8
34 34 33 33 5 6
IDE_HDD2 32 31 IDE_HDD13 IDE_HDD7 IDE_HDD9
IDE_HDD1 32 31 IDE_HDD14 IDE_HDD6 7 8 IDE_HDD10
30 30 29 29 9 10
IDE_HDD0 28 27 IDE_HDD15 IDE_HDD5 IDE_HDD11
28 27 IDE_HDD4 11 12 IDE_HDD12
26 26 25 25 13 14
IDE_HDREQ 24 23 IDE_HDD3 IDE_HDD13
<18> IDE_HDREQ 24 23 15 16
IDE_HDIOW# 22 21 IDE_HDD2 IDE_HDD14
<18> IDE_HDIOW# 22 21 +5VS 17 18
IDE_HDIOR# 20 19 IDE_HDD1 IDE_HDD15
<18> IDE_HDIOR# 20 19 19 20
IDE_HIORDY 18 17 R77 1 2 470_0402_5% Pull down set primary IDE_HDD0 IDE_HDREQ
<18> IDE_HIORDY 18 17 21 22
IDE_HDACK# 16 15 IDE_HDIOR#
<18> IDE_HDACK# 16 15 23 24
IDE_HIRQ 14 13 R78 1 2 @ 10K_0402_5% IDE_HDIOW#
IDE_HDA1 14 13 PDIAG# IDE_HIORDY 25 26 IDE_HDACK#
<18> IDE_HDA1 12 12 11 11 27 28
IDE_HDA0 10 9 IDE_HDA2 IDE_HIRQ
<18> IDE_HDA0 10 9 IDE_HDA2 <18> <18> IDE_HIRQ 29 30
IDE_HDCS1# 8 7 IDE_HDCS3# IDE_HDA1 PDIAG#
<18> IDE_HDCS1# 8 7 IDE_HDCS3# <18> 31 32
2
IDE_ACT# 6 5 IDE_HDA0 IDE_HDA2
6 5 IDE_HDCS1# 33 34 IDE_HDCS3#
+5VS 4 4 3 3 +5VS 35 36
2
2 1 IDE_ACT#
46
45
2 1 37 38 +5VS
R79 R216 +5VS 39 40 +5VS
OCTEK_HDD-22EG1_ REVERS @ 10K_0402_5% +5VS +5VS
46
45
1
4.7K_0402_5% 41 42
43 44
1
Pull high set slave SEC_CSEL 45 46
GND
GND
47 48
49 50
OCTEK_CDR-50TA1
53
54
2 +5VS 2
+5VS 06/23 R27
IDE_ACT# 1 2
Placea caps. near HDD CONN. +5VS
10K_0402_5%
Placea caps. near ODD CONN.
0.1U_0402_16V4Z
1U_0603_10V4Z
10U_0805_10V4Z
1 1 1 1
C123
C121
C124
0.1U_0402_16V4Z
1U_0603_10V4Z
10U_0805_10V4Z
C541
10U_0805_10V4Z 1 1 1 1
2 2 2 2
C1459
C1460
C1461
C1462
Pls close HDD connector 10U_0805_10V4Z
2 2 2 2
3 3
4 4
close to U21
close to U25chip(Intel rule) close to U25chip(Intel rule) RJ45
RDP
C1463
RDP TDP
2
2 1
2
R1982
R1978 R1975 110_0402_1%
@ 110_0402_1% 68P_0402_50V8K
110_0402_1%
1
RDN JP49
1
D LAN_RXD0 RDN TDN @ R1972 ACTLED# D
12 Amber LED-
LAN_RXD1 300_0603_5%
LAN_RXD2 1 2 11
+3VALW Amber LED+
2 SHLD4 16
2
33P_0402_50V8J 33_0402_5%
33_0402_5%
R2019 8
R2028 300_0603_5% PR4-
SHLD3 15
R2026
R2027
33_0402_5% +3VS 1 2 7 PR4+
0915
MDO1- 6
1
1
PR2-
1 1 1
33P_0402_50V8J
8/23 5 PR3-
C1557
C1558
2
22P_0402_50V8J +3VS 1 2 MDO0+ 1
15 mil PR1+
Colse to LAN chipset 1 2 2 1 SHLD1 13
Y3 L36 @ R1976 LINK_LED100# 10
25MHZ_20P_1BG25000CK1A NO SHORT PADS BLM11A121SPT_0603 300_0603_5% Green LED-
1
LAN1_XI 1 2 +3VS CONN@ SUYIN_100073FR012S100ZL
C1464
J2
22P_0402_50V8J 1 2
0718 Intel checklist recommend 1 2
68P_0402_50V8K
H5
H6
R2013 NO SHORT PADS
33_0402_5% U27
LAN_JCLK 1 2 E2 J9
XTAL2-X2
XTAL1-X1
C
<18> LAN_JCLK JKCLK-JCLK VSSA[17]-NC +3VLAN C
VSSA[16]-NC J8
<18> LAN_RSTSYNC LAN_RSTSYNC E3 J5
JRSTSYNC VSSA[15]-VSSA2
VSSA[14]-VSS J3
2
<18> LAN_TXD0 LAN_TXD0 D1 J1
JTXD0 VSSA[13]-NC
LCI
1
LAN_RXD1 JRXD0 VSSA[09]-VSS TDN MDO0- R1979 C1509
<18> LAN_RXD1 D2 JRXD1 VSSA[08]-VSS E9 8 TD- TX- 9
<18> LAN_RXD2 LAN_RXD2 C1 D6 TDP 7 10 MDO0+ 75_0402_5%
JRXD2 VSSA[07]-VSS TD+ TX+ MCT0 RJ45_GND
VSSA[06]-VSS C9 6 CT CT 11 2 1 2 1
VSSA[05]-VSS C8
H2 C7 1000P_1206_2KV7K
GLAN_TXP-NC VSSA[04]-VSS MCT1
J2 GLAN_TXN-NC VSSA[03]-VSSR C6 3 CT CT 14 2 1
A9 RDN 2 15 MDO1- R1980
VSSA[02]-NC RD- RX-
GLCI
0.1U_0402_16V4Z
0.1U_0402_16V4Z
H4 GLAN_RXN-NC VSS[04]-VSS F4 1 1
VSS[03]-VSSP E1
C1516
C1517
R1984 1 2 649_0402_1% G7 C4 NS0013_16P
R1983 KBIAS_P-RBIAS100 VSS[02]-VSS +3VLAN
1 2 619_0402_1% H7 KBIAS_N-RBIAS10 VSS[01]-NC A1
@ 2 2
LINK_LED100# A4 F7
ACTLED# LED0-LINK_UP_N VDD1P0[03]-VCCA
B4 LED1-ACT_LED_N VDD1P0[02]-VCCT E8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_6.3V4Z
A5 LED2-SPEED_LED_N VDD1P0[01]-VCCR D7 1 1 1 1 1 1
C1515
C1511
C1512
C1513
C1514
C1510
TDP B8 E5
TDN MDI_PLUS[0]-TDP VCCF1P0-VCC 2 2 2 2 2 2
B9 MDI_MINUS[0]-TDN
MDI
VCC1P0-VCCA2 G4 0_0603_5%
+3VLAN
RING 2
1
2 RJ11
<BOM Structure>
0.1U_0402_16V4Z
10U_0805_6.3V4Z
1 1 1 C1552 1 C1553 3
470P_1808_3KV 470P_1808_3KV GND1
J6 RSVD_J6-NC VCC[02] E4 4 GND2
C1519
C1520
RBIAS_P-NC
JTAG_TCK-ISOL_TCK
E6 RBIAS_N-NC
C3
JTAG_TDI-ISOL_TI
CTRL_10-NC
JTAG_TDO-TOUT
CTRL_18-NC B2
B5 RSVD_B5-NC
A6 RSVD_A6-ADV10/LAN_DIS_N
C5 RSVD_C5-NC THERM_D_P-NC A2 8/18 for EMI
1 2 B6 TEST_EN THERM_D_N-NC A3
R1985 200_0402_5%
JP57
RING
TIP 1
2
A ACES_85205-0200 A
T1 T3 RJ11 CABLE
45@
T2 T4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
82562EZ LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3361P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 22 of 43
5 4 3 2 1
A B C D E
S1_VCC
1
U37
13 C629
VCC 4.7U_0805_10V4Z
VCC 12
2
6/02 9 12V VCC 11
S1_VPP S1_VCC
+3V_CB S1_VPP
+5V_CB
4.7U_0805_10V4Z
0.1U_0402_16V7K
1 1 1
1
10 +3V_CB 1
VPP 1 1
1 C630 C631 C632
5 0.1U_0402_16V7K 0.1U_0402_16V7K C636 C637
5V 2 2 2
680P_0402_50V7K
C634
C633 4.7U_1206_25VFZ 0.1U_0402_16V4Z
0.1U_0402_16V7K
6/02 6 5V
1 1 L37 2 2
1
2 VCCD0#
VCCD0 1 1 2 +3VS
2 VCCD1# C635
+3V_CB VCCD1 VPPD0 0_0805_5%
15
2
VPPD0 2 2
C1538
14 VPPD1
VPPD1 0.1U_0402_16V7K 0711 EMI request 0711 EMI request S1_VCC
3 3.3V 0711 EMI request
1 4 8 +3V_CB
3.3V OC C641
SHDN
VPPD0 +5V_CB
GND
C640 VPPD1 1 2 1 1
0.1U_0402_16V7K VCCD0#
1
16
126
138
122
102
74
73
72
71
44
18
90
86
50
30
14
63
U38 L38
2
PCI_AD[0..31] 1 2
VCCD1#
VCCD0#
VPPD1
VPPD0
VCCP0
VCCP1
VCCSK0
VCCSK1
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCCI
<17,24> PCI_AD[0..31] +5VS
0_0805_5%
S1_VCC
0711 EMI request
PCI_AD31 3 144 S1_D10 1 2 S1_A23
PCI_AD30 AD31 CAD31/D10 S1_D9 R716 22K_0402
4 AD30 CAD30/D9 142
PCI_AD29 5 141 S1_D1 1 2 S1_WP
PCI_AD28 AD29 CAD29/D1 S1_D8 R717 22K_0402
7 AD28 CAD28/D8 140
PCI_AD27 8 139 S1_D0
PCI_AD26 AD27 CAD27/D0 S1_A0
9 AD26 CAD26/A0 129
PCI_AD25 10 128 S1_A1
2 PCI_AD24 AD25 CAD25/A1 S1_A2 2
11 AD24 CAD24/A2 127
PCI_AD23 15 124 S1_A3 S1_VCC
PCI_AD22 AD23 CAD23/A3 S1_A4
16 AD22 CAD22/A4 121
PCI_AD21 17 120 S1_A5
PCI_AD20 AD21 CAD21/A5 S1_A6
19 AD20 CAD20/A6 118
1
PCI_AD19 23 116 S1_A25
PCI_AD18 AD19 CAD19/A25 S1_A7
24 AD18 CAD18/A7 115
PCI_AD17 25 113 S1_A24 R715
PCI_AD16 AD17 CAD17/A24 S1_A17 47K_0402_5%
26 AD16 CAD16/A17 98
PCI_AD15 38 96 S1_IOWR#
2
PCI_AD14 AD15 CAD15/IOWR# S1_A9 JP54
39 AD14 CAD14/A9 97
PCI_AD13 40 93 S1_IORD#
PCI_AD12 AD13 CAD13/IORD# S1_A11
41 AD12 CAD12/A11 95 1 GND GND 35
PCI_AD11 43 92 S1_OE# S1_D3 2 36 S1_CD1#
PCI_AD10 AD11 CAD11/OE# S1_CE2# S1_D4 S1_D3 S1_CD1# S1_D11
45 AD10 CAD10/CE2# 91 3 S1_D4 S1_D11 37
PCI_AD9 46 89 S1_A10 S1_D5 4 38 S1_D12
PCI_AD8 AD9 CAD9/A10 S1_D15 S1_D6 S1_D5 S1_D12 S1_D13
47 AD8 CAD8/D15 87 5 S1_D6 S1_D13 39
PCI_AD7 49 85 S1_D7 S1_D7 6 40 S1_D14
PCI_AD6 AD7 CAD7/D7 S1_D13 S1_CE1# S1_D7 S1_D14 S1_D15
51 AD6 CAD6/D13 82 7 S1_CE1# S1_D15 41
PCI_AD5 52 83 S1_D6 S1_A10 8 42 S1_CE2#
PCI_AD4 AD5 CAD5/D6 S1_D12 S1_OE# S1_A10 S1_CE2# S1_VS1
53 AD4 CAD4/D12 80 9 S1_OE# S1_VS1 43
PCI_AD3 54 81 S1_D5 S1_A11 10 44 S1_IORD#
PCI_AD2 AD3 CAD3/D5 S1_D11 S1_A9 S1_A11 S1_IORD# S1_IOWR#
55 AD2 CAD2/D11 77 11 S1_A9 S1_IOWR# 45
PCI_AD1 S1_D4 S1_A8 S1_A17
PCI_AD0
56
57
AD1 PQFP 144 CAD1/D4 79
76 S1_D3 S1_A13
12
13
S1_A8 S1_A17 46
47 S1_A18
AD0 CAD0/D3 S1_A13 S1_A18
PCI_C_BE3# 12
22.2 X 22.2 X 1.60 125 S1_REG#
S1_A14
S1_WE#
14
15
S1_A14 S1_A19 48
49
S1_A19
S1_A20
<17,24> PCI_C_BE3# C/BE3# CC/BE3#/REG# S1_WE# S1_A20
PCI_C_BE2# 27 112 S1_A12 S1_RDY# 16 50 S1_A21
<17,24> PCI_C_BE2# C/BE2# CC/BE2#/A12 S1_RDY# S1_A21
PCI_C_BE1# 37 99 S1_A8 17 51 S1_VCC
<17,24> PCI_C_BE1# C/BE1# CC/BE1#/A8 S1_VCC S1_VCC S1_VCC
PCI_C_BE0# 48 88 S1_CE1# 18 52
<17,24> PCI_C_BE0# C/BE0# CC/BE0#/CE1# S1_VPP S1_VPP S1_VPP S1_VPP
S1_A16 19 53 S1_A22
S1_RST S1_A15 S1_A16 S1_A22 S1_A23
<17,24,29> PCIRST# 20 RST# CRST#/RESET 119 20 S1_A15 S1_A23 54
3 S1_A23 S1_A12 S1_A24 3
<17,24> PCI_FRAME# 28 FRAME# CFRAME#/A23 111 21 S1_A12 S1_A24 55
<17,24> PCI_IRDY# 29 110 S1_A15 S1_A7 22 56 S1_A25
IRDY# CIRDY#/A15 S1_A22 S1_A6 S1_A7 S1_A25 S1_VS2
<17,24> PCI_TRDY# 31 TRDY# CTRDY#/A22 109 23 S1_A6 S1_VS2 57
32 107 S1_A21 S1_A5 24 58 S1_RST
<17,24> PCI_DEVSEL# DEVSEL# CDEVSEL#/A21 S1_A5 S1_RST
33 105 S1_A20 S1_A4 25 59 S1_WAIT#
<17,24> PCI_STOP# STOP# CSTOP#/A20 S1_A4 S1_WAIT#
34 104 S1_A14 S1_A3 26 60 S1_INPACK#
<17,24> PCI_PERR# PERR# CPERR#/A14 S1_A3 S1_INPACK#
35 133 S1_WAIT# S1_A2 27 61 S1_REG#
<17,24> PCI_SERR# SERR# CSERR#/WAIT# S1_A2 S1_REG#
<17,24> PCI_PAR 36 101 S1_A13 S1_A1 28 62 S1_BVD2
PAR CPAR/A13 S1_INPACK# S1_A0 S1_A1 S1_BVD2 S1_BVD1
<17> PCI_REQ2# 1 REQ# CREQ#/INPACK# 123 29 S1_A0 S1_BVD1 63
2 106 S1_WE# S1_D0 30 64 S1_D8
<17> PCI_GNT2# GNT# CGNT#/WE# S1_D0 S1_D8
CLK_33M_CBS 21 108 1 2 S1_A16 S1_D1 31 65 S1_D9
<16> CLK_33M_CBS PCLK CCLK/A16 S1_D1 S1_D9
R718 33_0402_5% S1_D2 32 66 S1_D10
S1_BVD1 S1_WP S1_D2 S1_D10 S1_CD2#
59 RI_OUT#/PME# CSTSCHG/BVD1 135 33 S1_WP S1_CD2# 67
+3V_CB 70 136 S1_WP 34 68
R722 43K_0402_5% SUSPEND# CCLKRUN#/WP GND GND
Change to DAU00 PCI Devices ID 69 GND GND 70
PCI_AD22 1 2 13 103 S1_A19 71 72
R720 100_0402_5% IDSEL CBLOCK#/A19 GND GND
Cardbus ---->AD22 73 GND GND 74
60 132 S1_RDY# 75 76
<17> PCI_PIRQC# MFUNC0 CINT#/READY GND GND
61 MFUNC1 77 GND GND 78
64 MFUNC2 SPKOUT 62 CBS_SPK# <25> 79 GND GND 80
65 134 S1_BVD2 81 82
<19,29> SIRQ MFUNC3 CAUDIO/BVD2 GND GND
CLK_33M_CBS 67 83 84
MFUNC4 S1_CD2# GND GND
68 MFUNC5 CCD2#/CD2# 137
1
RSVD/D14
S1_CD1#
RSVD/A18
69 75
RSVD/D2
1 PLTRST_MCH# 1 2 CB1410_LQFP144
6
22
42
58
78
94
114
130
84
100
143
1000P_0402_50V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CardBus CTRL CB714
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 23 of 43
A B C D E
5 4 3 2 1
PCI_AD[0..31]
PCI_AD[0..31] <17,23>
+3VALW
R1913
+3VS +3VS
1 2 XMIT#
@ 10K_0402_5%
D D
6/23 JP23
1 1 2 2
1
R73
@ 10_0402_5%
1
2
C118
@4.7P_0402_50V8C
1
+3VS
A A
1 2 2 2 2 2 2 2 2
C371 C367 C111 C402 C112 C404 C368 C403
WLAN@ C548 WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@
10U_0805_10V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z
2 1 1 1 1 1 1 1 1
Compal Electronics, Inc.
Title
MINIPCI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 24 of 43
5 4 3 2 1
A B C D E
+VDDA_CODEC
U29
W=40Mil 10K_0402_5% 4 5
+VDDA_CODEC +5VS VIN VOUT
1
1 1 2 DELAY SENSE or ADJ 6 1 R1926 2 1 1
08/17 Delete L39 C1465 C1467
1
C1466 R1927 7 1 10K_0603_1% C1468
R1928 4.7U_0805_10V4Z ERROR CNOISE 4.7U_0805_10V4Z
2 2 1 2 2
8 3 C1469 R1929
2
10K_0402_1% SD GND
SI9182DH-AD_MSOP8 5.9K_0603_1%
C1470
2
0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
2 1
1 0.01U_0402_16V7K 1
1
R1930 1U_0603_10V4Z
10K_0402_1%
C1471
2
MONO_IN 1 2 MONO_IN1 2 1 MONO_INR
R1931 20K_0402_5%
R1932
1U_0603_10V4Z
C1472 1 2
1
R1933 C Q50
<23> CBS_SPK# 2 1 1 2 2 10K_0402_5%
B
1
560_0402_5% E 2SC2411K_SOT23
SI phase fine tune the best one
3
C1473 1U_0603_10V4Z
2
6/21
1 2
R1934 @ 0_0402_5%
@ 0.1U_0402_16V4Z
1 2
R1935 0_0402_5%
C1474
R1937 1 2
<19> SPKR 2 1 1 2 R1936 @ 0_0402_5%
560_0402_5% 1 2
1U_0603_10V4Z 6/21 R1938 @ 0_0402_5%
1
D44
R1939 1 2
R1940 @ 0_0402_5%
2 @ 10K_0402_5% RB751V_SOD323 2
1 2
2
R1941 @ 0_1206_5%
1 2
R1942 @ 0_1206_5%
1 2
R1943 @ 0_1206_5%
1 2
R1944 @ 0_1206_5%
For Layout:
GNDA <27>
Place decoupling caps near the
power pins of SmartAMC +3VAMP_CODEC
0711 EMI request
0711 EMI request device. L40 GND GNDA
L41 2 1 +VDDA_CODEC
+3VALW 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW_CODEC FBMA-L10-160808-301LMT_0603
FBMA-L10-160808-301LMT_0603
2 1 1
1 1 1 1 1 C1475 C1477
1
C1476 10U_0805_10V4Z
C1478 C1479 C1480 C1481 C1482 R1947 1U_0603_10V4Z
1 2 2
2 2 2 2 2 249K_0402_1% +CODEC_REF
18
10
23
33
44
2
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDD_CLK
VDD5
VDDC18
VDDC10
AVDD33
AVDD44
R1986
3K_0402_5%
3 3
1 RCOSC1
2
1 2 3 C1483 1U_0603_10V4Z
<26> DIB_DATAN DIB_DATAN
AMOM@ R1948 0_0402_5% 29 2 1
MIC_IN MIC <27>
<26> DIB_DATAP 1 2 4 DIB_DATAP
AMOM@ R1949 0_0402_5% 32
CD_IN_R
<26> PWRCLKP 1 2 7 PWRCLKP CD_IN_GND 31
AMOM@ R1950 0_0402_5% 30
CD_IN_L
<26> PWRCLKN 1 2 8 PWRCLKN
AMOM@ R1951 0_0402_5% 27 0.1U_0402_10V6K 1 2C1523
LINE_IN_L 0.1U_0402_10V6K 1
1 1 <18> AC97_CODEC_SDOUT 15 SDATA_OUT LINE_IN_R 28 2
C1484 C1485 R7 1 2 33_0402_5% 16 C1524
<18> AC97_SYNC SYNC
<18> AC97_RST# 17 AC_RESET# LINE_OUT_L 39 LINE_OUTL <27>
@ 150P_0402_50V8J @ 150P_0402_50V8J 40
2 2 LINE_OUT_R LINE_OUTR <27>
0713 Disable AMOM 1 R2012 2 20 AC_ONLY HP_OUT_L 42 HP_L <27>
DISAMOM@ 0_0402_5% 43
HP_OUT_R HP_R <27>
<18> AC97_SDIN0 1 2 21 SDATA_IN0
R1952 33_0402_5% 38
REF_FLT
<18> AC97_BITCLK 1 2 22 BIT_CLK VC_SCA 37
R1953 33_0402_5% 36 2 1
VREF_SCA C1486 C1487
11 ID0# 1 1
34 +CODEC_REF 09/15 C1488 C1489
MBIAS/AVDD 1U_0603_10V4Z
12 ID1# 1 2
S_PDIF 46
14 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z
EAPD R1954 1
GPIO_4 47 2 0_0402_5% MIC_SENSE <27>
0.1U_0402_16V4Z
MONO_INR 45 PC_BEEP R1992 1
GPIO_5 48 2 0_0402_5% HP_SENSE <27>
13 33_0402_5%
DSPKOUT
AVSS_CLK
XTLO 24 1 2 1 2
GNDC19
AGND35
AGND41
GNDC9
XTLI 25
1
GND8
4 4
X2 24.576MHZ_16P_XSL024576FG1H
CX20468-31_TQFP48
2
6
9
19
26
35
41
1 2
C1491 15P_0402_50V8J
1
MTP52
1
VDD MTP59
MTP26 BR908_CC C1553,C1552 replace MC906 and MC908 NI 09/20
0.1U_0402_10V6K
1
1
MBR908A 2 1
6
BAV99DW-7_SOT363 MTP29 MC928
MC930 VDD MC978 MC906 and MC908 must be Y3 type
MTP22 2.2U_0805_10V6K 0.1U_0402_10V6K Capacitors for Nordic Countries
1 2 1 1
1
1 2 MTP36 MTP37 only
1
1 1
1
1
15K_0402_5% 10P_0402_50V8J DGND_LSD RING_2 MOD_RING
24
1 1 2 1
2
MT902 5 2 1CLK2 1 2 CLK MU902 MR902 MTP39 MMZ1608D301BT_0603 MTP41
4
1 4BR908_AC1 1M_0805_5% MC902
AVdd
DVdd
<25> PWRCLKN
1 MFB906 21 RAC1 1 2 RAC1/RING 1 2 0.033U_1206_100V7K 1 @ MC906
RAC1
1
MTP23 1 2 MC904 470P_1808_3KV
MC962 1 MMZ1608D301BT_0603 26 20 TAC1 1 2 TAC1/TIP 1 2 0.033U_1206_100V7K MBR904
CLK TAC1
1
TB3100M-13-01_SMB
2 MBR908B MC970 MTP30 MTP34 MR904 TIP_2 2 MJ2
3
1 MTP40 1
2
1
<25> PWRCLKP 2 3 PCLK BAV99DW-7_SOT363 0.1U_0402_10V6K
RAC2 19 2
2
MTP24 PRI SEC TRDC MR906 1 2 6.8M_0805_5%
MRV902
2
3
2
S X'FORM_ 835-00252 PWR+ 1
7 PWR+ TAC2 18 1
MTP27
1
MTP60 MTP33 E&T_3800-02
1
2
1
1
1 1 0_0402_5% 1 EIC 1 MTP32
TRDC 12 1 2 0.1U_0603_16V7K
MC922 1 2 10P_1808_3KV DIB_P1 1 2 DIB_P2 27 0.015U_0603_25V7K 2 MBR906 @MC908
<25> DIB_DATAP DIB_P
11 MR910 MMBD3004S_SOT23 470P_1808_3KV
EIC 237K_0805_1% 2
AGND_LSD
MC924 1 2 10P_1808_3KV DIB_N1 1 2 DIB_N2 28 9 RXI 1 2 RXI-1
<25> DIB_DATAN
1
0_0402_5% DIB_N RXI 1 MTP71 MFB904
MTP25 MTP73 MTP62
MR924 1 TIP_2 1 2 MOD_TIP
MT922 GPIO1 1 MTP70 1
AGND_LSD MMZ1608D301BT_0603 MTP42
1 1 1
1
MJ1 1 4 MTP61 5 RBias 1 2
RBias MR954 59K_0402_1%
1 1 1 2 MC966
2 Vc_LSD 3 MTP69 MC910 0.01U_0805_100V7M
2 Vc VZ 1 BRIDGE_CC
3 3 VZ 10 1 2 1 2
4 Vref_LSD 4 MR908 348K_0805_1% 0.047U_1206_100V7K AGND_LSD
4 VRef
1
5 MTP68 MTP67 C
5 MTP63 EIO 1 1 MQ902
6 6 2 3 EIO 17 2
PRI SEC B PMBTA42_SOT23
7 1 1 2 1 8 Use 59K_0402_1% for MR954
1
7 NC1
2
4
8 @ S X'FORM_ 835-00252 MC940 22 16 EIF E
3
8 MC974 MC944 MC976 NC2 EIF MQ904
25 NC3
1
@ HEADER8 @ 0.001U_0402_50V7M 1U_0603_6.3V6M 14 C 1
2 2 1 2 TXO TXO MQ906
MJ1B 2
0.001U_0402_50V7M B PMBTA42_SOT23 FZT458TA_SOT223
1 1 0.1U_0402_10V6K
29 PADDLE TXF 13
E MTP66
2 2
DC_GND
2 3
TXF 1
3 3 AGND_LSD 1
DGnd
AGnd
MTP64
4 4
5 5
1
CX20493-58_QFN28 MR928
6 6
1
1 MTP65 MR938 27_0805_5%
7 7
6
15
23
110_0603_5%
8 8
1
MTP31
@ HEADER8 1 MTP49
2
GND AGND_LSD
JP53
SPKL+
SPKR+ 1
2
47P_0402_50V8J
47P_0402_50V8J
ACES_85205-0200
2
1 1 C0NN@
@ D45
C1492
C1493
PSOT24C_SOT23
2 2
1
1 1
0711 EMI request 0711 EMI request
+3VALW
0915
1
+5VAMP R1958 +5VS
0.1U_0402_16V4Z 0_1206_5% R2029
0819 1 2 20K_0402_5%
1 1 1 1
2
C1494 MIC_SENSE JOPEN3
<25> MIC_SENSE
C1495 C1496 C1497 SHORT PADS
C503 R425 1U_0603_16V4Z 1 1 2 For EMI
LINE_C_OUTR 1 2 10U_0805_10V4Z 2 2 2 0.1U_0402_16V4Z
<25> LINE_OUTR 1 2 2
C1560
0.1U_0603_50V4Z 20K_0603_1% 0.1U_0402_16V4Z
2
6
C502 R424 U30
7
8
1 2 LINE_C_OUTL 1 2 LINE_OUT 3 JP52
VDD
<25> LINE_OUTL IN+
5
0.1U_0603_50V4Z 20K_0603_1% 5 SPKR+
LINE_OUT# 4 VO+
IN- 0818 4
C504 R429
1 2 1 2 3
10K_0603_1% 1 SHUTDOWN VO- 8 SPKL+ L42 6 MIC IN
2 0.22U_0603_10V7K MIC 2 1 2 2
GND
<25> MIC
2 FBMA-L11-160808-700LMT_0603 1
BYPASS
1
1 TPA6211A1DGNR_PMSOP8 FOX_JA6033L-5S1-TR
7
0711 EMI request C1500 CONN@
<29> EC_MUTE#
C1499 47P_0402_50V8J
0.22U_0402_16V4Z 2
2
+3VALW
1
R28
R1991
LINE_OUT#1 2 SPKR+ 20K_0402_5%
6/21
2
0_0402_5%
@ HP_SENSE
0809 <25> HP_SENSE
1
C1526
0.1U_0402_16V4Z
2
3
0711 EMI request 3
C1501
7
8
R1962 L43
HP_R 2INTSPK_CR+ PR
+
<25> HP_R 1 2 1 2 1 5
FBMA-L11-160808-700LMT_0603
30_0805_5% 4
100U_6.3V_M
3
C1502
R1963 L44 6 HP OUT
HP_L 2INTSPK_CL+ PL
+
<25> HP_L 1 2 1 2 1 2
FBMA-L11-160808-700LMT_0603 1
30_0805_5%
100U_6.3V_M JP14 FOX_JA6033L-5S1-TR
C1503 C1504 CONN@
2
47P_0402_50V8J 47P_0402_50V8J
R1964 R1965
1K_0402_5% 1K_0402_5%
1
4 4
+USB_VCCA
+5VALW USB Port
1
1 1
+USB_VCCA
100U_6.3V_M
+ C392 C386
C377
U26
1 8 1000P_0402_50V7K
C446 0.1U_0402_16V4Z GND OUT 2 2 2
2 IN OUT 7
2 1 3 IN OUT 6
<19,31> SYSON# 4 5 0.1U_0402_16V4Z
EN# FLG USB_OC# <19> @
G528_SO8 JP26
1 1
1 VCC
<19> USBP1- 2 D-
<19> USBP1+ 3 D+
1 1 4 GND
2
D20 C405 C412 5
@ PSOT24C_SOT23 @ 10P_0402_50V8J @10P_0402_50V8J GND1
6 GND2
2 2
1
For ESD SUYIN_020173MR004G552ZR
+USB_VCCA CAP LED
+3VS
1
1 1
100U_6.3V_M
+ C349 C355
C357
D35 R738
1000P_0402_50V7K
2 2 2 CAP_LED# +3VS
<29> CAP_LED# 1 2 1 2
0.1U_0402_16V4Z 17-21SYGC/S530-E1/TR8_GRN
200_0402_5%
JP22
1
GREEN
VCC
<19> USBP0- 2 D-
<19> USBP0+ 3 D+
1 1 4 GND
2
D19 C358 C361 5
@ PSOT24C_SOT23 @ 10P_0402_50V8J @10P_0402_50V8J6 GND1
2
Charge LED 2 2 GND2
2
1
SUYIN_020173MR004G552ZR
+3VALW
+3VALW
1
R1993 R1994
200_0402_5% 200_0402_5%
2
+3VALW
2
D10
Battery LED
POWER LED
1
19-22UYSYGC/S530-A2/TR8_ G/Y
R696
AMBER GREEN 200_0402_5%
1
14@
2
AMBER_BATLED#
<29> AMBER_BATLED#
2
GREEN_BATLED#
<29> GREEN_BATLED#
3 17-21SYGC/S530-E1/TR8_GRN
GREEN 3
14@ D39
1
ON/OFFBTN_LED#
08/18 <29,30> ON/OFFBTN_LED#
08/22 for EMI
PSDAT3
PSCLK3
WL ON/OFF Wireless LED
2
+3VS
D47
08/18 @ PSOT24C_SOT23
T/P Board
2
+3VS 14@
R1915
1
27_0402_5% +5VALW
1
1
WL_LED 0711 EMI request
14@ R735
<24> WL_LED 2
G Q47
20mil
SW1 1
2
10K_0402_5% S 2N7002_SOT23 C1539
3
1
1
4
FV:2.8V PSCLK3 <29>
5
6
14@ D32 3
1 2
@ SF10402ML080C_0402
TVS1 1
4 @ SF10402ML080C_0402 4
2 ACES_87151-06051 1 1 EMI
WL_LED_S CONN@ C3 C4
<30> WL_LED_S 2 100P_0603_50V8J 100P_0603_50V8J
2 2
<>
+3VALW
+3VALW
1
@
+3VALW C291 C106 C336 C345 C366 R1995 R1996
1.65V(R1995=2K,R1997=2K) --->SI 2K_0402_5% 1K_0402_5%
08/09 2 2 2 2 2
2.2V(R1996=1K,R1997=2K) --->PV
0.1U_0402_16V4Z 1000P_0402_50V7K M/B_ID
1 2
High (3.3V) --->MV
1
1
+3VS @ R1997
R196 D46 +3VALW +EC_AVCC 2K_0402_5%
47K_0402_5% RB751V_SOD323 R252 2006/09/15
1 @ 10K_0402_5% 1
2
2
ECRST# 1 2
105
127
141
1
0.01U_0402_16V7K
11
26
37
75
C290 JOPEN2 U20
0.1U_0402_16V4Z SHORT PADS GATEA20 1 71 BATT_TEMP CP3
EMI Add
VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC
EC_AVCC / AVCC
BATT_TEMP <38>
2
116 KBA5
R273 R263 KBA5/A5
117 KBA6 @ 100P_1206_8P4C_50V8
10K_0402_5% 10K_0402_5% SMB_EC_DA2 Address KBA6/A6 KBA7
<13> SMB_EC_DA2 88 EC SMD2/ GPIO47/SDA2 KBA7/A7 118
SMB_EC_CK2 87 BUS 119 KBA8
<13> SMB_EC_CK2 EC SMC2/GPIO46/SCL2 SM BUS KBA8/A8
SMB_EC_DA1 86 120 KBA9
<30,38> SMB_EC_DA1
1
1
2 URX 4 135 FRD# R1925
2 <19,23> RSMRST# EC_RSMRST#/ GPIO02 FRD#/RD# FRD# <30>
3 UTX 7 136 FWR# 10K_0402_5%
3 <14> BKOFF# BKOFF#/GPIO03 FWR#/WR# FWR# <30>
1
2
100K_0402_5% <19> SLP_S5# EC_SMI# PM SLP S05#/ GPIO07 EC ON/ GPIO1B
<19> EC_SMI# 18 EC SMI#/GPIO08 AC IN/ GPIO1C 43 2 1 ACIN <33,34>
<19> EC_LANRST# EC_LANRST# 19 29 THERM_SCI#
THERM_SCI# <19>
2
EC SWI#/GPIO09 ECTHERM#/GPIO11
<30> LID_SW# 20 LID SW#/ GPIO0A ONOFF/GPIO18 36 ON/OFF <30>
<30,31,36> SUSP# 21 SUSP#/GPIO0B PCMRST#/GPIO1E 45 OVP_OV# <19>
22 46 ICH_PWRGD
<19> PWRBTN_OUT# PBTN_OUT#/GPIO0C WL OFF#/GPIO1F ICH_PWRGD <19>
ICH_PME# 23
<17,24> ICH_PME# EC PME#/GPIO0D MSEN#
ALI/MH#/GPIO40 81 MSEN# <15>
FSTCHG/GPIO41 82 FSTCHG <33>
VR ON/ GPIO42 83
137 SLP_S4#
VR_ON <37> WL/BT ON deletefollow DAU00 use SB GPIO control
FOR LPC SIO DEBUG PORT 1 2 CRY2 140 XCLKO
GPIO57/GPIO57
GPIO58/GPIO58 142 SPI_CLK
SLP_S4# <19>
SPI_CLK <30>
AGND
138 143
GND
GND
GND
GND
GND
GND
+5VS C362
3 4 KB910L_LQFP144
139
129
103
13
28
39
77
2
3 Y1 32.768KHZ_12.5P_1TJS125DJ2A073
3 CRY1 +3VALW
4 4 1 2
5 5
6 CLK_SIO_14M_ 1 2 10P_0402_50V8J
6 CLK_14M_SIO <16>
1
11
12 12 1 2LPC_LDRQ0# LPC_LDRQ0# <18>
13 PCIRST# R26 0_0402_5% L13
13 CLKRUN#
14 14 1 2 1 2
15 R270 1 2 CLK_33M_LPCEC C315 0_0603_5%
15 SIRQ 22_0402_5% 0.1U_0402_16V4Z
16
16
17 17 Compal Electronics, Inc.
18 Title
18
19 19 KBD EC CTRL-KB910L
20 20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
6/06 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
@ ACES_85201-2005 LA-3361P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 29 of 43
A B C D E
A B C D E
2 C109 1 2
1
@ 0.1U_0402_16V4Z
+3VALW R60 INT_FLASH_EN#
2 @ 10K_0402_5% C108 @ 0.1U_0402_16V4Z
1
2 1
5
D33 SPPB530600_4P U11
R59
2
1
SF10402ML080C_0402
P
OE#
@ R55 3 1 LID_SW#_R INT_FSEL# 1 2 4 2 FSEL# FSEL# <29>
SW2 14@ 100K_0402_5% O I
G
1 1BT002-01210_4P 1 @ 22_0402_5% 1
4 2
3 1 @ 74LVC1G125GW_SOT3535
3
D5 SW3 14@
4 2 3 ON/OFF ON/OFF <29>
ON/OFFBTN# 1
2 51ON# 51ON# <32,34> R58
5
6
+3VALW 1 2
DAN202U_SC70 Q9
0_0402_5%
1
DTC124EK_SC59
1
1
R53 D4
4.7K_0402_5% +3VALW
RLZ20A_LL34 +3VALW
2 C107
2
1
EC_ON 2 1000P_0402_50V7K R54 C540 +3VALW
<29> EC_ON
@ 100K_0402_5% SUSP# <29,31,36> 0.1U_0402_16V4Z
1 2
2
SB_INT_FLASH_SEL#
G
SB_INT_FLASH_SEL# <19>
5
Q8
5
2 1 3 U33
P
I0 EC_FLASH# <19>
FWR# 4
P
OE#
O @ 2N7002_SOT23 INT_FLASH_SEL SUS_STAT#
I1 1 4 O I 2 SUS_STAT# <19>
G
U10
3
@ TC7SH32FU_SSOP5 74LVC1G125GW_SOT3535
3
FWR# <29>
2 2
+3VALW
U39
20mils 8 4 SPI@SST25LF080A_SO8-200mil
VCC VSS
1 1
+3VALW +3VALW C1447 WP# 3
1MB ROM SOCKET W C1446
SPI@ 0.1U_0402_16V4Z HOLD# 7 0.1U_0402_16V8K
HOLD
1
2 2 SPI@
1
C324 FSEL# 1
R226 JP8 S
0.1U_0402_16V4Z 100K_0402_5% KBA16 KBA17 SPI_CLK 6
2 1 2 <29> SPI_CLK C
U19 KBA15
2
INT_FLASH_EN# 0_0402_5%
R228 INT_FLASH_SEL 21 22
100K_0402_5% KBA18 23 24 ADB3
KBA7 25 26 ADB2
KBA6 27 28 ADB1
2
4 KBA5 29 30 ADB0 4
KBA4 31 32 FRD#
KBA3 33 34
KBA2 35 36 FSEL#
KBA1 37 38 KBA0
39 40
SUYIN_80065AR-040G2T
1
22U_1206_10V4Z 10U_0805_10V4Z D Q49
2 SYSON#
G
RUNON S 2N7002_SOT23
3
+5VS +3VS +2.5VS +1.5VS +0.9VS +VCCP
Q39
8 D S 1
C481 7 2 C450 Q14 Q13 Q12 Q11 Q10
D S
1
B+ 10U_0805_10V4Z 0.1U_0402_16V4Z D Q15 D D D D D
6 D S 3
C480 5 D G 4 1 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP
10U_0805_10V4Z G G G G G G
1
3
R92 22U_1206_10V4Z
100K_0402_5% 2
2
RUNON
R99
1M_0402_5%
1
D
SUSP 2 Q19 C136
G 2N7002_SOT23 0.01U_0402_16V7K
S
3
+3VS 1 2 +1.5VS
C5 @ 0.1U_0402_16V4Z
+5VALW
+3VS 1 2 +3VALW
1
C6 @ 0.1U_0402_16V4Z
R280
47K_0402_5%
+5VALW 1 2 +3VALW
2
C7 @ 0.1U_0402_16V4Z SYSON#
<19,28> SYSON#
1 2
1
C8 @ 0.1U_0402_16V4Z D
2 Q31
<29,35> SYSON
G 2N7002_SOT23
S
3
B B
+5VALW 1 2 +5VS
CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CF10
C10 @ 0.1U_0402_16V4Z
1
FM1 FM2 FM3 FM4 FM5 FM6 CF12 CF11 +1.8V C1540 1 2 1000P_0402_50V7K +3VS +5VALW
1 1 1 1 1 1
1
R285
H1 H2 H3 H4 H5 H6 H7 H8 H9 +1.8V C1542 1 2 1000P_0402_50V7K +3VS 10K_0402_5%
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
2
+1.8V C1543 1 2 1000P_0402_50V7K +3VS
SUSP
<35> SUSP
1
1
D
SUSP# 2 Q32
<29,30,36> SUSP#
H14 H15 H16 H17 H18 H19 H20 G 2N7002_SOT23
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 7/11 EMI request S
3
1
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.047U_0402_16V4Z
0.047U_0402_16V4Z
H21 H23 H24 H25 H26 1 2
A HOLEA HOLEA HOLEA HOLEA HOLEA A
2 1
C1545
C1546
C1547
C1548
C1549
C1550
1
1 1
PD1
2
VIN VS 1 2 VMB 2
RB751V_SOD323
PL1 PQ1
5
SMB3025500YA_2P TP0610K-T1-E3_SOT23
3 1 PD2
3 1 ADPIN 1 2 1 2 2 1 1 3
PR1
0.22U_1206_25V7K
100K_0402_5%
47_1206_5% RLS4148_LLDS2
1
4 2
1
1000P_0402_50V7K
PC1
PR2
1
4 2
100P_0402_50V8J
1
1
PC5
PR3
2
PC4
2
SINGATRON_2DC_S736I201 PC3 0.1U_0603_50V4Z
2
2
1000P_0402_50V7K 2 1
2
51ON# <30,34>
PR4
22K_0402_5%
PC2
100P_0402_50V8J
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
DC CONN Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom <Doc>
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 32 of 43
A B C D
A B C D
B+ PQ2
SI4835BDY-T1-E3_SO8
BATT
3 8
2 7
P2
1 6
VIN P4
5
PQ3 PQ4
SI4835BDY-T1-E3_SO8 SI4835BDY-T1-E3_SO8 PR6
4
8 3 3 8 1 2 VIN
7 2 2 7 47K_0402_5%
6 1 1 6
2
5 5
PR5
PR8
0.1U_0603_16V7K
1 47K_0402_5% 1
4
2 1 10K_0402_5%
1
47P_0402_50V8J
1
2
1
PC8
PR7 PR9 PL2
47K
PC7
2
47K
1
PQ5 PQ7
RHU002N06_SOT323
2
PR153 DTC115EUA_SC70
1
CHG_B+ 100K_0402_5% D
PR10
47K_0402_1% +3VLP 2 1 2
10U_1206_25V6M
4.7U_1206_25V6K
1 2 2 G
1
PR11 PR12 PR13 S
3
1
1
RHU002N06_SOT323 PQ8 D 0_0402_5% D
100_0402_1% 100_0402_1% 2 ACOFF <29>
PQ32
PC10
PC9
2 2 1 PACIN 2
G PR14 G
3
1U_0805_25V4Z
S DTC115EUA_SC70 150K_0402_5% S
3
3
1
PQ6 1 2 PQ31
3
PC12
RHU002N06_SOT323
1
PC11 PD3
2
1U_0603_6.3V6M RLZ16B_LL34
2
RHU002N06_SOT323
1
2
3
PU1
1
D SE_ConPWR- 8
PR15 ACN ACDRV# 25
PACIN 1 2 2 SE_ConPWR+ 9 22
G PACIN ACP VCC DH_CHG
3K_0402_5% 26 ACDET PWM# 21 4
S 16 SE_CHG+
3
SRP
2 PR16 1 5 15 SE_CHG-
PQ10
5
6
7
8
ACSET VS
+3VLP 2 PR18 1 27 ACPRES VHSP 20 0.015_2512_1%
100K_0402_5% 13 LX_CHG 1 2 1 2
BQ24703VREF IBAT
100K_0402_1%
0.1U_0603_25V7K
4 6 PL3
VREF BATSET
100K_0402_1%
10U_1206_25V6M
4.7U_1206_25V6K
1 16UH_SIL104R-160PF_3.6A_30%
BATDEP
1
PC13
PR20
7 COMP GND 17
3K_0402_1%
3K_0402_1%
PR21
PC14
PC15
10 NC1 NC4 23
1
11 14
2
NC2 NC3
PR22
PR23
1
BQ24703_QFN28 PD5
4.7U_0805_6.3V6K
2
EC31QS04
2
1
PC18
2
PC17
32.4K_0402_1%
1
1 2
2
1
PC19
PR24
1U_0603_6.3V6M
0.1U_0402_16V7K
1
PR25 CV=16.8V (4/8 CELLS LI-ION)
150_0402_1% =12.6V (6 CELLS LI-ION)
4.7U_0805_10V6K
PR26 PC20 CC=1.54A (4 CELLS LI-ION)
1 2
1 2 150P_0402_50V8J
2
1M_0402_5% +3VLP BATT =3A (6/8 CELLS LI-ION)
PC21
2
VS VIN
1
3
VIN 3
100K_0402_5%
PR27
1
604K_0603_0.1%
133K_0603_1%
PR28
1
1 2
1
1
PR30
PC107 PR29
PR31
2
0.1U_0603_25V7K 10K_0402_1% 1 2 PR32
ACIN <29,34>
2
+3VALW
1K_0402_5% 10K_0603_0.1%
2
PR33
2
2.15K_0402_1% PU2A
2
1 2 3 3.2V
P
+
0.047U_0402_16V7K
1 PACIN
O
1
1
PACIN <34>
12.4K_0603_0.1%
2 PR37
-
1
1
PC22
PR34
47K_0603_0.1% PR155
1
2
1
470P_0402_50V7K
@100P_0402_50V8J
2
RLZ4.3B_LL34 RHU002N06_SOT323
2
PQ33
2
1
1
D
2 Batt_Det <38>
PC23
PC24
PR39 G
1
PR156 D
S
"Lo": 4/8 CELLS LI-ION
3
P2 @15K_0402_1% 17.4K_0603_0.1% 2
2
G
S
"Hi": 6 CELLS LI-ION
PR38
3
1 2 PQ34
0.022U_0402_16V7K
4 RHU002N06_SOT323 4
75K_0402_1%
1
PC25
PU3
1.24VREF
2
4 REF CATHODE 3
NC 2
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date Deciphered Date
5 1
ANODE NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
LMV431ACM5X_SOT23-5 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 33 of 43
A B C D
A B C D E
PC26 PC27
PL4 0.1U_0603_50V4Z 0.1U_0603_50V4Z
B++
1 1 2 BST_5V_B BST_3.3V_B 1 2 1
FBM-L11-322513-151LMAT_1210
2
B+ 2 1
2200P_0402_50V7K
10U_1206_25V6M
PD7
PR40 CHP202UPT_SOT323-3
PQ11
1
0_0402_5% VL B++
1 8DH_5V_B 1 2
1
D2 G2
PC28
PQ12
PC29
2 7
2
D2 D1/S2/K
2200P_0402_50V7K
3 G1 D1/S2/K 6 1 D2 G2 8
4.7U_1206_25V6K
4 S1/A D1/S2/K 5 2 D2 D1/S2/K 7
47_0402_5%
B++ 3 6
G1 D1/S2/K
1
AO4916_SO8 4 S1/A D1/S2/K 5
PR41
PC31
PC32
PC30
PR42 0.1U_0603_16V7K AO4916_SO8
0.1U_0603_50V4Z
2
0_0402_5%
2
PR43
1
0_0402_5%
VL 2VREF_1999
DH_3.3V_B
4.7U_0805_10V4Z
1
1
2
1U_0805_16V7K
1
1
0_0402_5%
PC33
PC34
1
PR45
2
PR44
PC35
PL5
2
10U_LF919AS-100M-P3_4.5A_20% 0_0402_5%
1
2
0_0402_5%
2
@499K_0402_1%
@499K_0402_1%
18
20
13
17
2
2
PU4
PR46
2 BST_5V 14 2
PR47
V+
LD05
TON
VCC
BST5
PR48
ILIM3 5
DH_5V 16
1
DH5
1
+5VALWP
1
LX_5V 15
DL_5V LX5
19 DL5 ILIM5 11
@10.2K_0402_1%
21 PL6
OUT5 BST_3.3V 10U_LF919AS-100M-P3_4.5A_20%
9 FB5 BST3 28
2
1 26 DH_3.3V
2
B++ PR50 N.C. DH3
PR49
2VREF_1999 1 2 24 DL_3.3V
0_0402_5% DL3 LX_3.3V
6 SHDN# LX3 27
PC36 1 PR51 4 22
ON5 OUT3
1
47K_0402_5%
1 2 3
1
+ ON3
150U_D2_6.3VM
@0_0402_5% FB3 7
PR52
0_0402_5%
PR53
2
PRO#
@3.57K_0402_1%
PR54
LDO3
10K_0402_5% 8
GND
2
REF
2
2VREF_1999
PR55
0.1U_0603_25V7K
MAX8734AEEI+_QSOP28
1
23
25
10
1
VL
0.22U_0603_10V7K
+3VLP 1
MAINPWON
4.7U_0805_10V4Z
MAINPWON <18,38>
1
1
+
PC37
PC39
1
2
2
PC38
PR56
2
PC40
2 1 PR57 150U_D2_6.3VM
2
0_0402_5% 2
499K_0603_1% 2
0_0402_5%
PR58
1
1
3 PC41 3
2
0.047U_0603_16V7K
VL
1
PR59
100K_0402_5%
1
D
2
2
G PQ30
S TP0610K-T1-E3_SOT23
3
1
D D
PQ13
RHU002N06_SOT323 2 PACIN <33> 2 1 3 +3VLP
G G
2
S PQ14 S PQ15
3
3
RHU002N06_SOT323 RHU002N06_SOT323
PR61
100K_0402_5%
2
<30,32> 51ON#
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP / 5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 34 of 43
A B C D E
A B C D
PL15
FBMA-L11-322513-151LMA50T_1210
B+ 2 1 1.8V_B+
+1.8VP
2200P_0402_50V7K
10U_1206_25V6M
+6269_VCC
220U_V_4VM_R25M
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1
1
+
PC43
PC42
PC45
PC46
PR62
1
PC44
1 2 1 2
2
1 PC116 PR63 0_0603_5% 1
2
2
680P_0402_50V7K 10K_0402_5% PC47 2
BST_1.8V
0.22U_0603_16V7K
DH_1.8V
LX_1.8V
5
6
7
8
+5VALW
D
D
D
D
1
PR64
0_0402_5%
17
16
15
14
13
G
S
S
S
PU5 PR65 PQ16
1 2 SI4800BDY-T1-E3_SO8
PHASE
BOOT
UG
GND
PGOOD
+6269_VCC
4
3
2
1
2.2_0603_5%
2 11 DL_1.8V PL7
VCC LG 3.3UH_PCMC063T-3R3MN_6A_20%
1
PC49 1 2
2.2U_0603_6.3V6K PR66
1 2 3 10
2
FCCM PGND
0_0402_5%
1
PR152
PR68 4.7_1206_5%
1 2 4 9 SE_1.8V 1 2
<29,31> SYSON EN ISEN
5
6
7
8
PR67 15.4K_0402_1% (500mA,40mils ,Via NO.= 1)
COMP
PU6
FSET
D
D
D
D
0_0402_5%
2
APL5508_SOT89 +2.5VSP
VO
FB
1
+3VS
2
2
ISL6269ACRZ-T_QFN16 PQ17 2 3 2
5
8
IN OUT
G
S
S
S
PC113 AO4702_SO8
4.7U_0805_6.3V6K
2
PC114
1U_0603_10V6K
@2200P_0402_25V7K
4
3
2
1
1
680P_0603_50V7K GND
FB_1.8V
PC50
PC51
1
2
90.9K_0402_1%
0.01U_0402_16V7K
1
1
57.6K_0402_1%
PR69
PR70
PC52
22P_0402_50V8J
2
1
PC53
6800P_0603_50V7K
2
2
2
1
PC54
2
PR71
1 2
4.12K_0402_1%
1
PR72
2.05K_0603_1%
2
+1.8V
3 3
PU7
1 VIN VCNTL 6 +5VALW
10U_0805_10V4Z
2 GND NC 5
PC56
1
PC55 3 7
VREF NC
1
10U_0805_10V4Z
2
PR73 PC57
4 VOUT NC 8
1.07K_0402_1% 1U_0603_16V6K
2
9
2
PJP1 PJP2 TP
1 2 +5VALW (4.5A,180mils ,Via NO.= 9) 1 2 +2.5VS (500mA,40mils ,Via NO.= 1) G2992F1U_SO8
+5VALWP +2.5VSP
PAD-OPEN 3x3m
PAD-OPEN 4x4m
0.1U_0402_16V7K
+0.9VSP
1
PJP3
1
RHU002N06_SOT323 D
PAD-OPEN 4x4m 1K_0402_1%
1 2 2 PC59
<31> SUSP
2
PJP4
PC58
PR75 G 22U_1206_6.3V6M
2
+1.8VP 1 2 +1.8V (6A,240mils ,Via NO.= 12) 0_0402_5% S
3
1
PAD-OPEN 4x4m
PC60
2
PJP5 @0.1U_0402_16V7K
+1.05V_VCCP 1 2 +VCCP (4A,160mils ,Via NO.= 8)
4 PAD-OPEN 4x4m 4
PJP6
+1.5VSP 1 2 +1.5VS (4A,160mils ,Via NO.=8)
PAD-OPEN 4x4m
PJP7 Security Classification Compal Secret Data Compal Electronics, Inc.
+0.9VSP 1 2 +0.9VS (2A,80mils ,Via NO.= 4) Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title
PAD-OPEN 3x3m THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP/0.9VSP/2.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS <Doc> 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 35 of 43
A B C D
5 4 3 2 1
D D
PL8 B+++
FBMA-L11-322513-151LMA50T_1210
B+ 1 2 @2200P_0402_50V7K
10U_1206_25V6M
@2200P_0402_50V7K
+5VALWP
1
1
1
1
PC61
PC63
PC64
PR76
PC62
PC68 4.7U_1206_25V6K
0_0402_5%
2
2
4.7U_1206_25V6K
2
PD8
CHP202UPT_SOT323-3
2
2
1
BST_1.5V_B PR77
BST_1.05V_B
PC65 20_0603_5%
1U_0805_50V4Z
1
C C
0.1U_0603_25V7K
PQ20 PQ19
1
1 8 VCC_MAX8743 8 1
D2 G2 G2 D2
1
PC76
2 D2 D1/S2/K 7 7 D1/S2/K D2 2
3 6 PR78 6 3
2
G1 D1/S2/K PC69 PC66 PC70 D1/S2/K G1
4 5 0_0603_5% PR79 5 4
2
S1/A D1/S2/K 1U_0805_16V7K D1/S2/K S1/A
2 1 1 2 1 2BST_1.5V_B 2 1
AO4916_SO8 0_0603_5% AO4916_SO8 +1.5VSP
+1.05V_VCCP PL9 0.1U_0603_25V7K 0.1U_0603_25V7K PL10
22
4
9
3.3UH_PCMC063T-3R3MN_6A_20% PU8 3.3UH_PCMC063T-3R3MN_6A_20%
2 1 BST_1.05V 25 21 1 2
UVP
V+
VCC
BST1 VDD
5.1K_0402_1%
PR80 PR81
220U_V_4VM_R25M
5.1K_0402_1%
0_0402_5% DH2
1
1
1 LX_1.05V 27 17 LX_1.5V
LX1 LX2
PR85
PR84
DL_1.05V 24 20 DL_1.5V 1
DL1 DL2
1
+
PC71
220U_B2_2.5VM
CS2 16
2
+
PC73
PC72 28
4.7U_0805_6.3V6K CS1 PC74
1 15
2
2
2 OUT1 OUT2 4.7U_0805_6.3V6K
14
1
FB2 2
2 FB1 ON2 12
PD12 PR87
PGOOD 7 2 1
1
@1SS355_SOD323 5 0_0402_5%
TON
1
1 2 11 PR91
ON1 10K_0402_1%
ILIM2 13
B PR88 B
3
SKIP
GND
OVP
REF
100K_0402_1% PR89 ILIM1
2
0_0402_5%
2
2 1 MAX8743EEI+T_QSOP28
<29,30,31> SUSP#
8
23
10
PR82
0_0402_5%
PD13
1
PC79 2 1
@1000P_0402_50V7K 2 1
2VREF PR83
0_0402_5%
2
2 1 @1SS355_SOD323
1
VCC_MAX8743 1 2
PR151 PR92 1 2 SUSP#
1
PR93
@0_0402_5% 100K_0402_1% 100K_0402_1% 0_0402_5%
PR90
1
PR86
2
2
0_0402_5% PC67
0.22U_0603_16V7K PC80
2
2
@1000P_0402_50V7K
A A
B+
CPU_B+
+5VS
PL11
HCB4532KF-800T90_1812
+3VS
1 2
2200P_0402_50V7K
10U_1206_25V6M
10U_1206_25V6M
0.01U_0402_50V4Z
1
@100U_25V_M
1
1
PC83
PC84
PC85
1
+
PR94
PC81
PC82
10_0402_5%
2
2
D PC86 PC115 D
2
1
2 1000P_0402_50V7K
2.2U_0603_6.3V4Z
1
PR95
1U_0603_10V6K
10K_0402_5%
0.01U_0402_50V4Z
2
2
BST_CPU1_B
5
6
7
8
PC88
PU9
0.22U_0603_16V7K
PQ21
PC87
D
D
D
D
1
1
IRF7413Z_SO8
PC89
VCC_CPU
10 30
PR96 0_0402_5% VCC VDD
G
S
S
S
<5> CPU_VID0 2 1 24 D0 V+ 36
PR99 PR97 0_0402_5%
4
3
2
1
@0_0402_5% 2 1 23 26 BST_CPU1 1 PR98 2 PR101
<5> CPU_VID1 D1 BSTM
VCC_CPU 1 2 PR100 0_0402_5% 0_0402_5% 2.2_0402_5% +CPU_CORE
2 1 22 28 DH_CPU1 1 2DH_CPU1_B PL12
<5> CPU_VID2 PR103 0_0402_5% D2 DHM 0.56UH_ETQP4LR56WFC_21A_20% PR104
REF_CPU 1 2 2 1 21 27 LX_CPU1 1 2 1 2
<5> CPU_VID3 D3 LXM
1
PR102 PR105 0_0402_5%
PR106
FDS6676AS_SO8
@0_0402_5% 2 1 20 29 DL_CPU1 0.001_2512_5%
<5> CPU_VID4 D4 DLM
5
6
7
8
1 2 PR108 0_0402_5% 4.7_1206_5%
2 1 19 31 CPU VCC SENSE
D
D
D
D
PR107 <5> CPU_VID5 PR109 0_0402_5% D5 PGND
2 2
1
0_0402_5% 1 2 25 37 SE_CPU1+
<16,19> VGATE VROK CMP
499_0402_1%
499_0402_1%
PQ22
3K_0402_1%
PR110
1
S
S
S
4 38 SE_CPU1- 820_0402_5%
S0 CMN
@1000P_0402_50V7K
PR113 PC90
4
3
2
1
2
VCC_CPU 1 2 5 17 OAIN+ 680P_0603_50V7K PC92
2
S1 OAIN+
PC91
C 0_0402_5% C
1 2 6 16 OAIN- 1 2
1
SHDN OAIN-
PR115 PR116 PR117 30.1K_0402_1%
PR111
PR112
PR114
9> VR_ON 0_0402_5% 1 2 2 1 1 15 FB_CPU
1
@100K_0402_5% TIME FB 0.47U_0603_16V7K
1 2 PC93 12 CCV CCI 14 1 2 PR118 820_0402_5%
PR119 PC94 470P_0402_50V8J 1 2
270P_0402_50V7K
1 2 2 35 BST_CPU2
TON BSTS
200K_0402_1%
PR121 1 2 REF_CPU 8 33 DH_CPU2 PR120
71.5K_0402_1% REF DHS
1 2
1 2 PC95 0.22U_0603_16V7K 9 34 LX_CPU2
ILIM LXS 3K_0402_1%
+5VS
FB_CPU 1 2 7 32 DL_CPU2
OFS DLS PD9
10.7K_0402_1%
100P_0402_50V8J
1
PC96
PR123
18 39 SE_CPU2- BST_CPU2_B 3
PR124 SKIP CSN CPU_B+
2
1
2
D
0_0402_5%
27P_0402_50V8J
PR125
1 2 2 PQ24
1
PC97
G 2 41
16,19> H_STP_CPU# S G TP
3
2200P_0402_50V7K
10U_1206_25V6M
10U_1206_25V6M
0.01U_0402_50V4Z
S
3
1
PR126
5
6
7
8
PC101
+3VS 1 2 RHU002N06_SOT323
PC98
PR127 RHU002N06_SOT323 MAX1532AETL+T_TQFN40
D
D
D
D
PC99
PC100
100K_0402_5% 0_0402_5%
2
0.22U_0603_16V7K
1 2 PQ25
<19> PM_DPRSLPVR
1
B IRF7413Z_SO8 B
G
S
S
S
PC102
PR128
+3VS 2 1 PR129
4
3
2
1
2.2_0402_5%
10K_0402_1% 1 2 PL13
1
2
PR130 0.56UH_ETQP4LR56WFC_21A_20%
PR131 10K_0402_1% 1 2
100K_0402_1%
1
FDS6676AS_SO8
2
5
6
7
8
2
PR132
1
4.7_1206_5% PR133
D
D
D
D
1
D PQ27 820_0402_5%
2 RHU002N06_SOT323
2 2
PQ26
G
1
G
S
S
S
S
3
PR134
4
3
2
1
1
0_0402_5% PC103 1 2
1
2 1 2 680P_0603_50V7K
<5> PSI# PC104
PQ28 0.47U_0603_16V7K
3
PMBT2222A_SOT23-3
PR135
1 2
820_0402_5%
A A
OVP voltage :
LI-MH 4 CELL(4S1P)/ 8 CELL (4S2P)
BATT+ : 18.0V--> BATT_OVP : 2.0V BATT
LI-MH 6 CELL(3S2P)
VMB PL14 BATT
PCN2
BATT+ : 13.5V--> BATT_OVP : 1.5V
HCB4532KF-800T90_1812
(BATT_OVP voltage = 0.1109*BATT+)
1
BATT+ 6 1 2
1 PR149 1
EC_SMD VS 340K_0402_1%
SMD 5 Batt_Det <33>
4 EC_SMC
SMC PR136
3 2 1
2
RES
1
TS 2 @1K_0402_5%
1
1 PC105 PC106
2
GND
1
3 PD10 @SM05_SOT23 1000P_0402_50V7K 0.01U_0402_50V4Z PC111
TYCO_C-1746706_6P 1 0.1U_0603_25V7K PR150
2
2 499K_0402_1%
PR137 PD11
2
6.49K_0402_1% @SM24_SOT23
8
1 2 +3VALW PU10A
1
<29> BATT_OVP 3
P
+
0.01U_0402_50V4Z
1 0
1
PR138 2
-
1
1K_0402_5%
2.2K_0402_5%
@0.1U_0402_16V7K
1
1
PR148
PC112
PR139 LM358ADR_SO8
2
4
PR140
PC110
100_0402_5% 100_0402_5%
2
BATT_TEMP <29>
2
2
SMB_EC_DA1 SMB_EC_DA1 <29,30> PR147
2
105K_0603_0.5%
SMB_EC_CK1 SMB_EC_CK1 <29,30>
2 2
8
PU10B
5
P
+
7 0
- 6
G
LM358ADR_SO8
4
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C
PR141
+5VS 47K_0402_1%
1 2
+5VS
3 3
CPU
1
2
PR146
PH1 10K_0402_5%
2
10K_TH11-3H103FT_0603_1%
1
MAINPWON <18,34>
PR142
8
15K_0603_1% PU2B
1
D
1 2 5
P
+ PQ29
O 7 2
+5VS 1 2 6 G RHU002N06_SOT323
-
G
PR143 S
3
150K_0402_1% LM393DG_SO8
4
1
PR144
1
2.55K_0603_1%
PC108 PC109
0.22U_0603_10V7K PR145 1000P_0402_50V7K
2
150K_0402_1%
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom <Doc>
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 43 of 38
A B C D
5 4 3 2 1
2 Change U31 to LF parts 0.2 25 Change U31 from SA204680000 to SA204680010 Debug DB
D D
3 LID switch material error 0.2 30 Change SW3 from SN511000300 to SN111000207 Debug DB
4 CardBus controller material error 0.2 23 Change U38 from SA014100310 to SA014100130 Debug DB
5 Un-install some bridge between AGND and DGND 0.2 25 Un-install R1934,R1936,R1938,R1940 Debug DB
6 Let XMIT# match SW's GPIO definition 0.2 24 Delete Q46,R1913,R1914 Debug DB
11 DB phase loss 0.2 23 JP54(PCMCIA connector) pin 71pin72 connect to GND Debug DB
12 XMIT# Reserved pull high 0.2 24 Reserve R1913 pull high +3VALW
13 DB phase error 0.2 17 Change RP43RP44RP45 package SIZE from 0804 to1206
17 Reserver a resistor for 2nd source Amp 0.2 27 Add R28 for 2nd source Amp
B
18 Avoid DISPLAYOFF# error status to high 0.2 14 Change R120 to 47K and R9 to 4.7K B
20 EMI Request 0.2 23 Change C641 from 0.1u to 680PAdd C1538(680p) for +3V_CB
25 EMI Request 0.2 25 Change R1946R1945 to Bead L40L41 and Add L39 For codec requlator
A A
28 PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3361P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 39 of 43
5 4 3 2 1
5 4 3 2 1
8 Place JKCLK series resistor with 2 inches of the 825660.2 22 Add R2013 The 33 ohm series resistor is required for signal integrity
9 Add B channel from compatible with Others 0.3 9 Connect NB LVDS B Channel to LVDS connector
14 Change LVDS CONN pin assignment for compatible 0.3 14 Add LVDS Channel B from NB and change pin assignment
20 WL ON/OFF & Wireless LED pull high voltage 0.3 28 Change pull high voltage form +5VS to +3VS;R1915 from 200 ohm to 27ohm
22 Change amplifier gain 0.3 27 Change R425,R424 from 34.8k to 20k; R429 from 16.2k to 10k
23 Change value of RTC capacitor 0.3 18 Change C115,C113 from 18P to 15P
2 WLAN LED work wrong Add two resister to select WL_LED and XMIT# 1.0 24 Add R2021,R2022 ; R2022 NI ,R2021 0 ohm
D D
3 increase RTC battery life 1.0 18 D42 pin2 change power form +3VALW to +3VLP
4 EMITest fail from LAN Follow intel reference design 1.0 22 C1517 change form 0.01u to 0.1U and C1516 NI
5 EMITest fail from LAN Add parallel damping test is PASS but marging 1.0 1822
6 MIC always on have noise Add MIC_Sense pin to detect MIC plug in 1.0 25 R1954 change from 10k to 0 ohm
MIC always on have noise Add MIC_Sense pin to detect MIC plug in 1.0 27 Add Rand C, MIC connector pin 3pin 5 connect to AGND
7
9 reduce S3 power consumption Disable wake on LAN function 1.0 19 20 22 Change R16,R11R70 to NI;R15,R12,R71 0 hom
C 10 AMON capacitor duplication C1533,C1552 replace with MC906,MC908 1.0 26 Change MC906,MC908 NI C
11
12
13
14
15
16
17
18
B B
19
20
21
22
23
24
25
26
A A
27
28 PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3361P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, September 21, 2006 Sheet 41 of 43
5 4 3 2 1
5 4 3 2 1
Change PR68
D Fine tune the 1.8V OCP set-point as 7.5A (minimum 2006/05/26 Before DB D
1 35 From SD034182280 (S RES 1/16W 18.2K +-1% 0402)
continue load)
To SD034154280 (S RES 1/16W 15.4K +-1% 0402)
2
Change PR20
Fine tune the charge current as 3A (maximum)
33 From SD034137380 (S RES 1/16W 137K +-1% 0402) 2006/05/30 Before DB
To SD034100380 (S RES 1/16W 100K +-1% 0402)
3
Change PR26
Fine tune the AC detector set-point
33 From SD034681380 (S RES 1/16W 681K +-1% 0402) 2006/05/30 Before DB
To SD028100480 (S RES 1/16W 1M +-5% 0402)
Change PR82
From SD034274180 (S RES 1/16W 2.74K +-1% 0402)
Fine tune the 1.05V OCP set-point as 8.125A To SD000009480 (S RES 1/16W 1.47K +-1% 0402)
4 36 2006/05/30 Before DB
(minimum continue load) Change PR92
From SD034909280 (S RES 1/16W 90.9K +-1% 0402)
C To SD034499280 (S RES 1/16W 49.9K +-1% 0402) C
Change PR83
From SD034274180 (S RES 1/16W 2.74K +-1% 0402)
Fine tune the 1.5V OCP set-point as 5A To SD000009480 (S RES 1/16W 1.47K +-1% 0402)
5 36 2006/05/30 Before DB
(minimum continue load) Change PR93
From SD034909280 (S RES 1/16W 90.9K +-1% 0402)
To SD034715280 (S RES 1/16W 71.5K +-1% 0402)
13 Modify the sequence of 1.8V for S3 can't Change connection of PR64.1 from +5VS to
35 2006/08/02 SI
resume issue +5VALW
For 4 series/ 3 series battery selection,
A 14 add circuit for changing charge voltage 33 Add PQ33, PQ34, PR154, PR155 and PR156 2006/08/10 SI A
17 For EMI's requirement 35 Add PR152 (4.7ohm) and PC114 (680pf) 2006/08/16 SI
C C
B B
A A