الدوائر المنطقية - د. محمد العدوي

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57357
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98eladawy@gmail.com
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Encoders Decoders
Multiplexer Demultiplexer
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RAM
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AND
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encoder multiplexer
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98eladawy@gmail.cpm
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48 4 NAND 7400
48 4 NAND 7401
51 4 NOR 7402
48 4 NAND 7403
45 6 Inverter 7404
45 6 7405
46 6 Current driver 7406
46 6 7407
47 4 AND 7408
47 4 AND 7409
49 3 NAND 7410
47 3 AND 7411
49 3 NAND 7412
47 3 AND 7415
46 6 7416
46 6 7417
49 2 NAND 7420
48 2 AND 7421
51 2 NOR Strobe 7425
48 4 NAND 7426
51 3 NOR 7427
51 4 NOR 7428
50 NAND 7430
48 4 OR 7432
51 4 NOR 7433
48 4 NAND 7437
48 4 NAND 7438
49 4 NAND 7439
49 2 NAND 7440
.
..
77 BCD 7442
77 BCD 7445
78 BCD 7446
Common
anode
78 BCD 7447
Common
anode
78 BCD 7448
Common
cathode
78 BCD 7449
Common
cathode
126 2 JK 7473
124 2 D 7474
120 4 Latch 7475
124 2 JK 7476
107 4 Full adder 7483
111 4 Comparator 7485
52 4 XOR 7486
144 10 7490
163 4 7491
145 12 7492
146 4 Ripple 7493
164 4 7494
164 4 7495
165 5 7496
126 2 JK 74107
127 2 JK 74109
128 2 JK 74112
128 2 JK 74113
.
..
128 2 4 Transparent 74116

216 4 74125
217 4 74126
50 NAND 13 74133
50 NAND 12 74134
82 Decoder 1 Demultiplexer 8 74137

83 1 8 74138
84 2 1 4 74139
85 BCD 74145
88 10 4 74147
90 8 3 74148
93 16 Multiplexer 74150
94 8 Multiplexer 74151
94 2 4 74153
86 Decoder 1 16 74154
86 2 2 4 74155
87 2 2 4 74156
95 4 MUX 74157
95 4 MUX 74158
147 74160
147 74161
147 74162
147 74163
167 8 74164
167 8 74165
167 8 74166
148 4 74168
148 4 74169
129 2 D 74173
129 6 D 74174
130 4 D 74175
.
..
149 74190
149 74191
150 74192
150 74193
167 4 74194
168 4 74195
151 4 74197
169 8 74199
217 8 74240
218 8 74241
218 4 74242
218 4 74243
218 8 74244
219 8 74245
96 8 MUX 74251
97 2 4 74253
97 4 2 74258
52 4 XNOR 74266
130 8 D 74273
118 4 RS 74279
107 Full adder 74283
151 74290
152 4 74293
130 8 D 74373
130 8 D 74374
153 2 74390
153 2 74393
112 8 74682
112 8 74684
112 8 74688
198 555
207 556
.
..
209 558
209 559
205 2240
211 ZN1034
188 1 RAM 4 2114
190 2 ROM 2716
191 4 ROM 2732
191 8 ROM 2764
188 2 RAM 6116
188 8 RAM 6264
191 32 ROM 27256
189 32 RAM 62256
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1 :
2 1-1
2 2-1
8 3-1
9 4-1
13 5-1 Analog and digital signals
14 6-1
17 7-1
19 : Numbering systems
20 1-2
20 2-2 Decimal system
21 3-2 Binary system
26 4-2 Ones and twos complement
27 5-2
27 - Sign magnitude
27 -
28 -
29 6-2
29 - :
30 - Over flow error
31 - :
31 7-2 Octal system
33 8-2 Hexadecimal system
34 9-2 Binary Coded Decimal Numbers, BCD
36 10-2
.
..
38 : Logic gates
39 1-3
39 2-3 Not gate
40 3-3 AND gate
41 4-3 OR gate
42 5-3 NAND gate
43 6-3 NOR gate
44 7-3 XOR gate
44 8-3 XNOR gate
45 9-3 Inverter chips
46 10-3 AND gate chips
48 11-3 OR gate chips
48 12-3 NAND gate chips
51 13-3 NOR gate chips
52 14-3 XOR and XNOR gate chips
52 15-3
54 :
55 1-4
55 2-4
56 3-4
58 4-4 Demorgans theorems
59 5-4
59 6-4
59 7-4
61 8-4
63 9-4
64 10-4
65 11-4 NAND
66 12-4 NOR
68 13-4 ( )
.
..
71 14-4
73 : Decoders And Encoders

74 1-5 Decoders
77 2-5 7442
77 3-5 7445
78 4-5 7446 7447 7448 7449
82 5-5 74137
83 6-5 74138
84 7-5 74139
85 8-5 74145
86 9-5 74154
86 10-5 74155
87 11-5 74156
87 12-5 Encoders
88 13-5 74147
90 14-5 74148
91 15-5 Multiplexer
93 16-5 74150
93 17-5 74151
94 18-5 74153
95 19-5 74157 74158
96 20-5 74251
97 21-5 74253
97 22-5 74258
98 23-5 Demultiplexer
99 24-5
101 : Arithmetic circuits

102 1-6
102 2-6
104 3-6 Half adder
.
..
104 4-6 Full adder

105 5-6
107 6-6 7483
107 7-6 74283
108 8-6
109 9-6
111 10-6 7485
112 11-6 74682 74684 74688
113 12-6
115 : Latches and flip flops

116 1-7
116 2-7 R-S
117 1-2-7 RS
118 3-7 74279 RS
118 4-7 RS Clock
119 5-7 D
120 6-7 7475 D
120 7-7 Flip Flops
122 8-7 trigger
122 9-7 JK
123 10-7 Asynchronous Inputs
124 11-7 T
124 12-7 74ls74 D
124 13-7 74ls76 JK
125 14-7 Master Slave Flip Flop
126 15-7 7473 JK
126 16-7 74107 JK
127 17-7 74109 JK
128 18-7 74112 JK
128 19-7 74113 JK
128 20-7 74116 4
.
..
129 21-7 74173 D

129 22-7 74174 D
130 23-7 74175 D
130 24-7 74273 D
130 25-7 74373 74374 D
131 26-7
131 1-26-7 Propagation delay time
132 2-26-7 Set up time
132 3-26-7 Hold time
132 4-26-7
132 27-7
133 28-7
135 : Digital Counters

136 1 -8
136 2 -8
137 3 -8
139 4-8
142 5-8
143 6-8
144 7-8 7490
145 8-8 7492 12
146 9-8 7493 4
147 10-8 74160 74162
147 11-8 74161 74163 4
148 12-8 74LS168 74LS169 /
149 13-8 74190 74191 /
150 14-8 74192 74193 /
151 15-8 74LS197 4
151 16-8 74LS290
152 17-8 74LS293 4
153 18-8 74LS390
.
..
153 19-8 74LS393 4

154 20-8
157 21-8
159 : Shift Registers

160 1 -9
160 2 -9
160 3 -9
161 4 -9
162 5 -9
162 6-9
162 7-9
163 8-9 7491 8
163 9-9 7494 4
164 10-9 7495 4
165 11-9 7496 5
166 12-9 74164 8
167 13-9 74165 8
167 14-9 74166 8
167 15-9 74194 4
168 16-9 74195 4
169 17-9 74199 8
170 18-9
171 19-9
174 20-9
175 :
176 1-10
.
..
176 2-10 ( )
177 3-10
180 4-10
183 5-10
185 6-10
188 7-10 2114 1 4
188 8-10 6116 2
188 9-10 6264 8
189 10-10 62256 32
190 11-10 2716 2 EPROM
191 12-10 2732 4 EPROM
13-10 2764 8 EPROM 27256
191 32 EPROM
192 14-10
194 : Timers
195 1-11
195 2-11
196 3-11 Comparator
196 4-11 Flip Flop
198 5-11 NE555
199 6-11
202 7-11
204 8-11 Timer Counters
205 9-11 XR2240 Timer Counter
207 10-11 XR 556
209 11-11 XR 558/559
211 12-11 ZN1034
212 13-11
214 : Tristate logic gates

215 1 -12
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215 2-12
216 3-12 74125
217 4-12 74126
217 5-12 74240
218 6-12 74241
218 7-12 74242 74243
218 8-12 74244
219 9-12 74245
221
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1
General Principles
. .
1-1

.
.
.
.
Resistances 2 -1
:

.

.

.

( )1-1
200 .

. (-1
)1

.
( 2-1 3-1 4-1 -1
)5
( )2 -1 .

2.
. .
. 01 150
.
( )3 -1
.
.
( )3 -1 ( )4 -1

( )5 -1
3.
. .

(-1
.)1 4 ( .)6 -1
( .)6 -1
6
.5 .65
.
6500 6,5 .
.%5
6500 %5
%20 (.)6 -1
( )6 -1
. reliability
. ( ) 7 -1
4.
. .
1000 . %0,01
1000 %0,01 10000
1000 . 4
( )7 -1 .

.

.
:
Potentiometer

( )7 -1
.
.

( .)8 -1
( )8 -1
.

.
.
. ( )9 -1
. ( )10 -1 .
.
5.
. .
( )9 -1
( )10 -1
6.
. .
: Resistor Network
( )11 -1

. ()12 -1

. (12 -1)

. (12 -1)
.
( )12 -1
( )11 -1
.
.

.LED
( )13 -1
() .
( )12 -1
7.
. .
( )13 -1
Capacitors 3 -1

.

. ( )14 -1

. 5
5
A, B, C, D, E
( .)14 -1 A

( )14 -1 . B

. C
8.
. .
. D . E .
.PF
( .)6 -1
. ( )15 -1
. 3
.
( )16 -1 .
( )15 -1

Integrated Circuits, ICs 4 -1

.

reliable .

.
9.
. .
( )16 -1

( )17 -1
. ( )17 -1 .
10.
. .
.

.

.

Dual In line Package,
DIP (.)18 -1

( )18 -1 DIP
.
.
.Small Outline IC, SOIC ( )19 -1 .
Plastic Leaded Chip Carrier,
PLCC
J
(20 -1) .

Leadless
Ceramic Chip Carrier, LCCC
(20 -1)

(.)20 -1
( )19 -1
SOIC

.1

( .)21 -1 1
.1
( )20 -1 (20 -1) 1
.
11.
. .
( )20 -1
17

32 16 .

. :
1 -1 Small
( )21 -1 Scale Integration, SSI

100
.
-2 Medium Scale Integration, MSI
1000 10000 .
-3 Large Scale Integration, LSI 10000
100000 .
12.
. .
-4 Very Large Scale Integration, VLSI

100000 .
-5 Ultra Large Scale Integration, ULSI
. 50 .
5 -1
Analog and digital signals

( ) .

.

( 20 ) ( 35 ) .
( )22 -1
20 35
20,001 22,00001

33,5505 .

. ( )22 -1
.

( )23 -1
.

.
. 20 221 259 334 .
. ( )23 -1 .
( )23 -1
. (
)
.
.
13.
. .
.
.
( )
. ( .)24 -1

positive logic
negative logic ( .)25 -1 .
1
0

1 0 1 0 0 1 0 1 0 0
0
( )24 -1
( )25 -1

( .)26 -1

.
( )26 -1

6 -1

.
() Oscilloscope
.
( ) .
14.
. .
.

.

.
( )27 -1
.
( )27 -1Oscilloscope

.
Logic analyzer

.

:
( )28 -1 Logic analyzer -1

4 .
-2 16 32 .
.
.
.
15.
. .
-3
.
-4
. ( )28 -1 .
Logic probe

. (29- 1 )
.

.
Pulse injector

(( )29 -1) () ( )

. (29 -1) .

Multimeter

.

.
. (-1
( )30 -1
Multimeter
16.
. .
)30 . .
Function generator

TTL . (-1
)31 .
Power supply

.

5
. ( )32 -1
( )31 -1 Function
generator .

.
( )32 -1 Power supply
7 -1
. -2
-3
.
. -4
1 2 3 . -5
17.
. .
. -6
. -7
. -8
-9
.
18.
2
Numbering Systems
.
1-2
.

... ! : decimal
system
! .
binary system
( !)octal system hexadecimal system
15 .
.

.
2-2 Decimal system

.
.
.
51
.
. 51
:
51=5 x10+1x1

. 499 :
499=4x102+9x101+9x100
20.
.
87535 :
87535=8x104+7x103+5x102+3x101+5x100

10 :
535.25=5x102+3x101+5x100+2x10-1+5x10-2

. decimal binary
.
3-2 Binary system

0 .1

.
0 0 0 0 0
1 0 0 0 1

2 0 0 1 0 2 10
3 0 0 1 1 . :
4 0 1 0 0 10=1x21+0x20=2 )(1 -2
5 0 1 0 1 101=1x22+0x21+1x20= 5 )(2 -2
6 0 1 1 0 101011=1x25+0x24+1x23+0x22+1x21+1x20=43 ( -2
7 0 1 1 1
)3
8 1 0 0 0

9 1 0 0 1
.2
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1 ...12 11 10 19
14 1 1 1 0 ...22 21 20 99
15 1 1 1 1 () 101 100
1-2 ...102 999 .
21.
.
1 0 11 10 101 100
111 . 1-2 15
. 15
. :
( )2n-1 n
. n=4 15 n=5
31 n=6 63.
1-3-2
( )1 -2 (-2
)2 ( )3 -2 :
110112=1x24+1x23+0x22+1x21+1x20=2710
2
10 .
. Least Significant Bit,
LSB .Most significant bit, MSB

11011.1101
:
11011.1101=1x24+1x23+0x22+1x21+1x20+1x21+1x22+0x23+1x 24
=16+8+2+1+0.5+0.25+0.0625
= 27.7135

.
2-3-2

2 20 21 22 .
9 8+1
23 20 9 :
22.
.
23 22 21 20
1 0 0 1
:
12=8+4=23+22=1100
25=16+8+1=24+23+20=11001
58=32+16+8+2=25+24+23+21=111010
82=64+16+2= 26+24+21=1010010

0
2

0
. 2
1 .

1

1 1 0 0
2 .
( )1 -2
( )1 -2 .
2
12 2
6
2
0. 0 1 0 1
3
0.3125 x 2 = 0.625 0
3 2
0.625 x 2 = 1.25 1

0.25 x 2 = 0.5 0
0.5 x 2 = 1.0 1 1 2
( )2-2
2 4 .

2
23.
.
2 .
.2 2

. ( )2-2 .
0.3125 2
0.625
1 1
=0+0 0 0 0 1 1
.
=0+1 1 0 +0 1 1
=1+0 1 0 1 1 0 0.625
=1+1 0 1 ( )4 -2 2 1.25
( )3 -2

0.25 2 0.5
0.5 2 1.0
. .0.0101
3-3-2

.
:
1 1 1 1
1 0 1 0 (-2
1 1 0 0 .)3
11 10 10 01 1+1

( )5 -2 .

( )4 -2 011 011
24.
.
. 11
. ( )4 -2
. 1+1+1
1+0+0
.
(.)5 -2

=0-0 0 0 10
:
=1-1 0 0 1 0 1
=1-0 1 0 - 0 1 1
=0-1 1 1 0 1 0 (.)6 -2
( )7 -2
( )6 -2

borrow .

=0x0 0
=0x1 0 ( ).
=1x0 0 ( )7 -2 011 101
=1x1 1 .010
( )8 -2 .

( )10
.
1011 010 .
x 1001
1011
0000 :
0000 ( )8 -2 .
1011 .
1100011

( )9 -2

25.
.
( )9 -2 1011 1001
.1100011
:
111 .
10 1110 ( )10 -2 1110
10
011 10 .111
10
010
10 4-2
00
( )10 -2 Ones and twos complement

.
:
1101001
0010110

:
1101001
0010110
1 1 +
0010111
:
-1
.
-2 .
:10111000
-1 3 .1000 :
26.
.
-2 01001000
.
:011
-1 .
-3 101
.
5-2

. ( )-9( + )-3
. ( )+ ( )-
.
.
:
1-5-2 : Sign magnitude

.
0101 0 101 5
.+5 1101 101 5
1101 ( )-5 -5 +5
.
.
2-5-2 :
0101 ) (+5
1010 ).(-5
27.
.
3-5-2 :
. 0101 ( )+5
1011 ( . )-5
.

11000 01011
: 11000
1* 23 = 8 ( )-8 01011
( +11 ).
: 11000
00111 11000 ) .(-7
01011 ( +11 ).
: 11000
01000 ( .)-8 01011 ( +11
).
11000 :
11000 = -1 * 24 + 1 * 23
= -16 + 8 = -8
01011 :
01011 = -0 *24 + 1 * 23 + 1 * 21 + 1 * 20 = 11

.
.
) (0000 ) (1111 ) (+0 (-
) .0 ) (0000 ).(0000
28.
.

0 .24-1=15 ) -(2n-1 ) (2n-1-1
( )-23 = -8 ( . )23-1=7
8- .7+ 8 255
128- 127 .
6-2

.
1-6-2
8 (1) .
:
-1 .
-2 .
-3 .
-4 .
.
:
00001001 9
00000101+ 5+
00001110 14
.
:
00001001 9
( 1 1 1 1 1 0 1 1 + )5 )+ (-5
1 00000100 +4
29.
.
+4 .
:
( 1 1 1 1 0 1 1 1 )9 ) ( -9
00000101+ +5
11111100 -4
.)-4( 0 0 0 0 0 1 0 0
:
( 1 1 1 1 0 1 1 1 )9 -9
( 1 1 1 1 1 0 1 1 + )5 )+ (- 5
1 11110010 - 14
( ) 1
00001110 (.)-14
2-6-2 Over flow error

( ) +127
-128
. :
01111101 125
00111010+ 58 +
10110111 +183
1
.
+127 .
1
.
30.
.
3-6-2
) ( 9-5 )(9
) (-5 ) (-5 .5 ) 9-(-5
) (9 ) -(-5 5 5 .
.
:
00001000 8
(1 1 1 1 1 1 0 1 + )3 -3
00000101 +5
( 1 1 1 1 1 0 0 0 )8 -8
( 1 1 1 1 1 1 0 1 + )3 -3
1 11110101 -11
00001011 ) (-11 .
.
7-2 Octal system

0, 1, 2, 3, 4, 5, 6, 7 :
7 :
6, 7, 10, 11, 12, ... , 15, 16, 17, 20, 21, ... , 25, 26, 27, 30, 31 , ...
1-7-2
.
8 83, 82, 81, 80 :.
:
(235)8 =2*82+3*81+5*80
=2*64+3*8+5 =(157)10
31.
.
2-7-2
8 :

157
19 5
8
19
2 3
8
2
0 2
8
.2358

8 8
:
( 0.35 )8 =3*8-1+5*8-2
= 0.45310
= ( 0.56 )10 0.56 0.48 0.84

8x 8x 8x
4.48 3. 84 6.72
= 0.436...8
3-7-2

0 0 0 0 .2-2
1 0 0 1
2 0 1 0
3 0 1 1 :
4 1 0 0
5 1 0 1 ( 354 )8 = 011 101 1002
6 1 1 0
7 1 1 1
2-2 3
:
1011100101 = 1 011 100 1012 = 13458
32.
.
8-2
Hexadecimal system
16 :

0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
0 0 0 0 0 9
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 A B C D E .F F
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1 16 160 161 162
8 1 0 0 0
9 1 0 0 1 163 . :
A 1 0 1 0
B 1 0 1 1
C 1 1 0 0
D 1 1 0 1
E 1 1 1 0
F 1 1 1 1
3-2
0,1,...,9,A,B,C,D,E,F,10,11,12,...,19,1A,1B,...,1F,20,21,...,29,2A,...,2F,3
40,... 0,31,...,39,3A,...3F,
16 :
3F216 =3*162+15*161+2*160
= 101010
16 :

323
20 3
16
20
1 4
16
1
0 1
16
32310 = 14316
.
33.
.
4 .3-2
:
4F216 = 0100111100102
1A4916 = 11010010010012

. 12410 :
12410 = 11111002
= 1748
= 7C16
12410 3 7
3 .
9-2
Binary Coded Decimal (BCD) Numbers
.
. 1-2
9 .

.
1-9-2

. 55 0101 0101 93 1001 0011.

4 :
349 = 0011 0100 1001
158 = 1 0101 1000
.
34.
.
2-9-2
( )
.
. 9 .
9

(0110) 6 . :
00100011 23 0011 3
00010101 + 15 + 0100 + 4+
00111000 38 0111 7
0100 0101 0000 450

0100 0001 0111 + 417 +
1000 0110 0111 867
9
. :
1001 9
0100 + 4+
1101 13
6 0110 +
1 0011
1001 9
1001 + 9+
1 0010 18
6 0110 +
1 1000
35.
.
0001 0110 16
0001 0101 + 15 +
0010 1011 31
6 0110 +
0011 0001
:
0110 0111 67
0101 0011+ 53 +
1011 1010 120
0110 0110 + 6
1 0010 0000
(
) 6 .
10-2
-1 7 :
7000,67 845,673 576,12 487
-2 :
10100, 1100.101, 01001.001, 1110.1111, 101010.11011
-3 :
4 7 10 11 16 .
-4 :
30,1 45,43 653 777 55
-5 :
00011 11111 00111 100001 10001 011110
-6 :
.110110111 00011 110111 1001 1100
36.
.
-7 8
:
.55+ 99- 123- 66- 25+
-8
:
.11110111 01110000 00011100 10011001 10111111
-9 5 .
-10 :
.777 111 11 375 335
-11 1 .
-12 6 .
-13 :
.B33 5A FF1 3F4
-14 1 .
-15 6 .
-16 :
(4310)5, (198)12, (345)6, (2376)8, (2FA1)16
-17 :
.1045 156 100 124 555 344 10
-18 :
.1001 1000 0000 1000 0111 0011 0001 1001 1001
37.
3

Logic Gates And Its Chips
..
1- 3

.
.
. : NOT gate
AND gate OR gate NAND gate NOR gate
. XOR gate
NOT gate 2- 3

.

. ()1 -3
.
I
.

.
( )1 -3
. ( )1 -3
. I
0 1 ( .)1 -3
1 0
.
( )2 -3 .

( )2 -3 .
1

X= A : X
0
.A ( )3 -3
1
0
.
( )3-3
39.
..
3- 3 AND gate

A
.
B F
.
A

&
F
B . ( )4 -3
. &
. ( )5 -3
( )4 -3
3 .
. 3

A B C F 23=8 (.)5 -3
0 0 0 0 F=ABC :
0 0 1 0
0 1 0 0 . ( )6 -3
0 1 1 0 .
1 0 0 0
1 0 1 0 A B C .
1 1 0 0 .
1 1 1 1

( )5 -3

.

A

B
. ( )7 -3
C

.
( )6 -3 3

40.
..
.
( .)7 -3
. B ( )7 -3 Enable .A
A B B
. F=ABC :
.
A

1 B
( )7 -3
A

B
F 4- 3 OR gate

A .

B
F .

( )8 -3
. (-3
)8 .

A B C F 1 . ( )9 -3
0 0 0 0 3.
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
( )9 -3

41.
..

A
:
B F=A+B+C
. ( )10 -3
C

.

( )10 -3 3

A B C .

() .

. ( )11 -3
( )11 -3
.
5- 3 NAND gate

A
A B C F
B F 0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
A
& 1 0 0 1
1 0 1 1
B
F
1 1 0 1
1 1 1 0
( )13 -3
( )12 -3
.
.
42.
..
.
A

B

C

.
( )14 -3 3 ( )12 -3
. ( )13 -3
A
3 . ( )14 -3

F
B .

F= ABC : .
A

F 6- 3 NOR gate
B

( )15 -3

.
A B C F .
0 0 0 1
0 0 1 0 .
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0 .
1 1 0 0
1 1 1 0
( )16 -3

43.
..
( )15 -3
A
()16 -3
B 3
. ( )17 -3
C

.

( )17 -3 3
F= A B C :
.
A

B
F
7- 3

XOR gate
A
Exclusive OR, XOR
=1
F

B

.
( )18 -3
.
( )18 -3 ( )19 -3

A B F .
0 0 0
0 1 1
1 0 1 8- 3 XNOR gate
1 1 0
.
( )19 -3 .

( )20 -3 ( )21 -3
.
44.
..
A

9- 3

B
F
Inverter chips
7404
A 74LS04 74S04 6
=1 ( .)22 -3

F
B 7404 10 12 .
74LS04 9,5
2,4 74S04
( )20 -3
3 22
. 7405 6
7404
A B F
0 0 1 .open collector
0 1 0 4,5
1 0 0
1 1 1 . ( )23 -3
. 7405 40 12
( )21 -3
. .
74LS05 17 2,4
74S05 5 20
.
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
( )22 -3 ( )23 -3 6 7405

7404 6
45.
..
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7406, 7416 7407, 7417

( )24 -3 7406 ( )25 -3 7407
6 7416 6 7417
7406
( .)24 -3 ( )25 -3 7407 6
. 7416 6
7406 . 7417 6 7407 (-3
)24 (.)25 -3
10-3 AND gate chips

( )26 -3 7408 4 . 74LS08
74S08 . ( )27 -3 7409 4
.open collector ( )28 -3 7411
( )29 -3 7415
. ( )30 -3 7421 .
46.
..
1 1 Vcc 14
Vcc 14
2 13 2 13
12 3 12
3
11 4 11
4
5 10 5 10
9 6 9
6
8 7 GND 8
7 GND
7408 7409
( )26 -3 ( )27 -3 7409

4 7408 4
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7411 7415
( )28 -3 7411 ( )29 -3 7415

47.
..
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7421 7432
( )30 -3 7421 ( )31 -3 4 7432

11-3 OR gate chips
( )31 -3 7432 4 .
12-3 NAND gate chips
( )32 -3 7400 7437 4 .
( )33 -3 7403 7426 7438 4
.
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
( )33 -3 7403
( )32 -3 7400
7426 7438
4 7437

48.
..
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7410
7401, 7439
( )35 -3 7410
( )34 -3 7401 4 7439

1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7420, 7440 7412

( )36 -3 7420 ( )37 -3 7412
7440
( )34 -3 7401 7439 4

. ( )35 -3 7410 3 ( )36 -3
49.
..
7420 7440 . ( )37 -3 7412

3 .
1 Vcc 14 1 Vcc 16
2 13 2 15
3 12 3 14
4 11 4 13
5 10 5 12
6 9 6 11
7 GND 8 7 10
7430 8 GND 9
( )38 -3 7430
74133
( ) 39-3 74133
13
1 Vcc 16 ( )38 -3 7430

2 OE 15 . 9 10
13 . ( )39 -3
3 14
74133 13.
4 13 ( )40 -3 74134
12 12 .15
5
OE
6 11
.
7 10 high
9 .impedance
8 GND
.
74134
( )40 -3 74134
12
50.
..
13-3 NOR gate chips

( )41 -3 ( )44 -3
. 7425
.
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7402, 7428 7433

( )41 -3 7402 ( )42 -3 4 7433
4 7428
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7425 7427
( )44 -3 2 7425 ( )43 -3 7427

51.
..
14-3
XOR and XNOR gate chips
( )45 -3 7486 4 ( )46 -3 74266

4 .
1 Vcc 14 1 Vcc 14
2 13 2 13
3 12 3 12
4 11 4 11
5 10 5 10
6 9 6 9
7 GND 8 7 GND 8
7486 74266
( )45 -3 7486 ( )46 -3 4 74266

4
15-3
-1 (-3 )1 3 .
A
.
B
-2 (-3 )1 3 .
C
(-3)1

.
-3 A, B, C (-3 )3 (-3 .)1 F
.
52.
..
-4 (-3.)3
A
-5 (-3
.)5
B
F
C

(-3)3
-6 (-3 )5
A

B 5 .
C F
-7 (-3
.)7
(-3)5

A -8 (-3 )7
F .7
B -9 (-3.)9
.7
(-3)7
-10 (-3 )9
A
.9
F -11 .
B .
-12 11 .
(-3)9
-13 A B (-3 )1
F .
-14 13 .
-15 7400 .74133 .
-16 . .
-17 16 .
53.
4
Boolean Algebra And Logic Simplification

. .
1- 4
George Boole
.1854
.

.
2- 4
.
AND OR .NOT
.
1-2-4 Logic Variable

. ( )0
(.)1
2-2-4 Complement

. .
.
A A=1 A = 0 .
Not gate .Inverter
3-2-4 Logic addition

OR 0+0=0 :
0+1=1 1+0=1 .1+1=1 sum term
A+B : A +B A+B+C .
. .
.OR gate
55.
. .
4-2-4 Logic multiplication

AND 0.0=0 :
0.1=0 1.0=0 .1.1=1 multiplication term
AB : ABCD . A BC
.
.And gate
1-4
A, B, C, D :
A +B+ C A B C
A=1 C=1 .B=0
B=1 A=0 C=0 .
A=0 B=1 .C=0
A=1 B=0 C=1 .
3- 4
.
.
1- 3- 4 Commutative law

:
A+(B+C)=(A+B)+C ()1-4
A.(B.C)=(A.B).C ()2-4
2- 3- 4 Associative law

:
A+(B+C) = (A+B)+C ()3-4
A.(B.C)=(A.B).C ()4-4
56.
. .
3-3-4 Distributive Law

:
A(B+C)=AB+AC ()5-4
1-4 12 .

. 10 11 12 :
10
)A+AB=A(1+B
=A.1
=A

1-4
.
1 A+0=A
2 A+1=1 11
3 A.0=0 A+ A B=A+B
4 A.1=A
5 A+A=A A+ A B=(A+AB)+B A
6 A+ =1 =(AA+AB)+B A
7 A.A=A
=AA+AB+A A + A B
8 A.=0
9 )=(AA+A A )+(AB+ A B
=A
10 A+AB=A =(A+ A )A+(A+ A )B = A+B
11 A+ B=A+B .
12 (A+B)(A+C)=A+BC
12
(A+B)(A+C)=A+BC
=AA+AC+AB+BC
=A(1+C)+AB+BC
=A.1+AB+BC
=A(1+B)+BC
=A.1+BC
57.
. .
=A+BC
.
Demorgans Theorems 4- 4
.
:
XY X Y ()6-4
X Y XY ()7-4

( .)6-4 (.)4-7
( )6 -4 ( )7 -4 .
.
2-4
WXYZ . W X Y Z :
WXYZ W X Y Z
:
W X Y Z W . X .Y .Z
:
) ( AB C )( A BC
.
:
) ( AB C)( A BC ) ( AB C) ( A BC
.

:
)( AB C) ( A BC ) ( A B).C A.( B C
.
.
58.
. .
5- 4
A
B F
C .
D
( )1 -4
( )1 -4

F=(AB+C)D :
.
F A B C
D F :
F=(AB+C)D ()8-4
6- 4

2-4 .
()1 -4 .

D C B A F=(AB+C)D
0 0 0 0 0
.
0 0 0 1 0
0 0 1 0 0 ( .)1 -4 4 ()A, B, C, D
0 0 1 1 0 .F
0 1 0 0 0
0 1 0 1 0 .24=16
0 1 1 0 0 16 .2-4
0 1 1 1 0
1 0 0 0 0
1
1
0
0
0
1
1
0
0
0 7- 4
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1 .
1 1 1 1 1

.
.
59.
. .
.

. :
3-4
:
F=(A B (C+BD)+ A B )C
-1 :
F=( A B C+A B BD+ A B )C
-2 B B 1
. :
F=( A B C+ A B )C
-3 :
F=A B CC+ A B C
-4 7 1 CC=C :
F=A B C+ A B C
-5 C B :
) F= B C(A+ A
-6 6 1 .A+ A =1 :
F= B C
A B C D
F
F

( )2 -4
60.
. .
. (2-4
) () ()
. AND
. .
.
8- 4
.
.
.
1-8-4 Sum of product form

A B C D E
AND
F1 OR .
:
F1=AB+ABCD
F2=ABC+CDE+ ABC
F2

AND
( )3 -4 OR
( )3 -4
. ( )3 -4
.AND-OR circuit
. .
F1 4 A, B,
C, D A, B .
.
.
:
61.
. .
4-4
F1 . F1:
F1=AB+ABCD
AB C D .
C+ C ( : )C+ C =1
F1=AB(C+ C )+ABCD
:
F1=ABC+AB C +ABCD
D .
:
F1=ABC(D+ D )+AB C (D+ D )+ABCD
:
F1=ABCD+ABC D +AB C D+AB C D +ABCD
.F1
2-8 -4 Product of sum form

A B C
( )AND ()OR
. :
F1
)F1=(A+ B )( A +B+C
)F2=( A + B +C)(A+ B +C+D

( )4-4 OR

AND ( )4-4 .F1 ()4-4
.OR-AND circuit
.
.
F1 3 A, B, C
B A .
.

62.
. .
8 1-4 . 12
) A+BC=(A+B)(A+C
:
5-4
F1 . F1:
)F1=(A+ B )( A +B+C
A+ B C . C C
:
)F1=(A+ B + C C )( A +B+C
12 :
)F1=(A+ B +C)( A+ B + C )( A +B+C
. F1
.
9- 4
.
3-4
6-4 . :

A B C F
0 0 0 0 6-4
0 0 1 1 :
0 1 0 0
0 1 1 0 F= A B C+A B C +ABC
1 0 0 1 3 23=8
1 0 1 0
1 1 0 0 .
1 1 1 1 .3-4

.
63.
. .
10- 4
(
)
1-10-4

.
( )3-4 F=1 :
A=0, B=0, C=1 .C B A A=1, B=0,
C=0 .A B C A=1, B=1, C=1
.ABC
:
F= A B C+A B C +ABC
.
.
2-10-4

. ( )3-4
F=0 : A=0, B=0, C=0
C B A A=0, B=1, C=0 B A C
. :
F = A B C + A B C + A BC+A B C+AB C
. F
:
) ( F ) ( A.B.C A.B.C A.B.C A.B.C A.B.C
F
:
)F=(A+B+C)(A+ B +C)(A+ B + C )( A +B+ C )( A + B +C
64.
. .

A .
A AB
B
11- 4
A
B
( )5 -4

A B C D E
.
.
F1
( )5 -4

. (5 -4)
A B C D E
AA A :
F1
. (5 -4)

( )6 -4
AB

AB . (5 -4) .
) . ( A.B
A+B .

(6 -4) . .
.
(6 -4) .
65.
. .

X Y Z

.
F

. :
-1
( )7 -4 :
F=X( Y Z ) XY
F=X Y XZ X Y
-2
A

A A+B .
B
:
A
F= X Y XZ XY
B
-3
( )8 -4
.
:
) F= ( X Y )( XZ )( X Y
( ) . ( )7 -4 .
12- 4
. (-4
)8 . (4-8)
:
A A A . (8 -4)

A B A+B
66.
. .
. (8 -4) .
) . ( A. B
AB .
A B C D E

F1
(9 -4) .
.

A B C D E .
(9 -4).
F1

.
( )9 -4

. :
-1 .
-2 .
-3
. .
67.
. .
13- 4 ( )
Karnaugh Map

.

.

( )10 -4

F
.
. .

.

.

( )11 -4
.

.
( )12 -4 ()8 -4

.
.
( ) Quine McClusky
. .
:
68.
. .
F=X Y +XY+ X Y
( )10 -4 .

4
.
X
. X

( )13 -4 Y
.Y
( ) X Y
( ) Y X ( ) X Y (
) .XY 4 X .Y

. 3 3
( .)10 -4 .
.
.XY+ X Y Y
X .
Y . Y
X .
. X Y .
X . F
:
F=X+Y
.
:
F= X Y Z +XY Z +XYZ
( )11 -4 .
:
F=XY+Y Z
69.
. .
Y .Z
. YZ=00
YZ=01 Z YZ=11
Y .
.
:
F= X Y Z +XY Z +XYZ+ X YZ ()8-4

(.)12 -4

Y
.

:
F=Y
( )14 -4 4

.
:
F= X Y Z +X Y Z + X Y Z +XY Z
( )13 -4 F= Z :
( )4-14 4 .
:
F= X W Y Z + X W Y Z + X W Y Z +X W Y Z
:
F= W Z
4
4
.
70.
. .
. .XWYZ
:
F= W Z +WXYZ
14- 4
-1 A, B, C :
a) AB b) ABC C) A+B d) A B C e) ABC
-2 :
a) X=(A+B)C+B b) X= ( A B)C )c) X=(A+BC)( B C
-3 :
a) A B b) AB C) AB CD )d) A B(C D ) e) AB(CD EF
f) ( A B C D ) ABC D ) g) ( ABC )( EFG ) ( HIJ )( KLM

-4 1 .2
-5 :
)a) BD + B(D+E) + D(D+F b) AB ABC A
c) AB ABC ABCD ABC DE )d) ( A A)( AB ABC
e)ABC(AB+ C (BC+AC)) f)ABCD +AB( CD ) + ( AB )CD
-7 SOP:
)a) (A+B)(C+ B ) b) (A+ B C)C c) (A+C)(AB+AC
)d) AB +CD(AB+AC) e) A+B(AC+(B+C)D
-8 .7
-9 .
-10 .5
-11 (-4 )11 .SOP
-12 .11
71.
. .
-13 12 .
-14 11 .
D C B A F -15 (-4
0 0 0 0 0
0 0 0 1 0 )11 .POS
0 0 1 0 0 -16 .15
0 0 1 1 1
0 1 0 0 0 -17 16 .
0 1 0 1 0 -18 15 .
0 1 1 0 1
0 1 1 1 0 -19 3
1 0 0 0 0 .
1 0 0 1 1
1 0 1 0 0 .
1 0 1 1 0 -20 4
1 1 0 0 1
1 1 0 1 1
3 ( ) .
1 1 1 0 0 .19
1 1 1 1 1
(-4)11
72.
5
Decoders And Encoders

.
Decoders 1 -5

0
1
n
2 . n
83 3
decoder 4 2n
5
6 .
7
2 22=4
( )1 -5 83 .11 10 01 00 :
3 8
.111 110 101 100 011 010 001 000 : n
combinational 2n .
. ( )1 -5 3 8
. .7 000 0
011 3 . . . .
n m=2n .
( )2 -5
A2 A1 A0 .
000 D0 AND
001 D1

.
010 D2
inverters
AND

011 D3
100 D4
. D3
101 D5 A0=1
110 D6 A2=0 A2=1
A2
111 D7
D3
( )2 -5 011
AND .
74.
.

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
1-5 83
1-5 .83
. 42 164 .2568
( )1 -5 .
. 164
.
binary coded decimal, BCD .

A1 A0
E A1 A0 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1

0 1 1 1 1 1 0
1 X X 1 1 1 1
Enable, E

( )3 -5 42 NAND E
- -
75.
.

.
.
NAND AND .
.
. ( )3 -5 42 E
.NAND E=1
.
42
D0
A0 A0 D1
A1 A1 D2
. ()4 -5
A2 E1 D3 42 .83
A0 A1
42 A2
D4
A0 D5 E1
A1 D6 E2 .
E2 D7
E1 E2
83 . A2=0
( )4 -5
83 42 D0 D3
A0 .A1 A2=1
D4 D7
A0 .A1

.
()5-5
7442
76.
.
2-5 74LS42 7442

BCD to Decimal Decoder
4 ( )5-5
. 16 8 .
. .
( )1001 . 7442 15
28 74LS42 18 7
. 83 D . ( )5-1
.

D C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
2-5 7442
3-5 7445
/ BCD to Decimal Decoder/Driver
4 .
( .)6 -5 16 .8 -5
3 . .
( )1001 . 28 .
83 D .
80 solenoid .LEDs
77.
.
( )6 -5
7445

D C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
3 -5 7445
4-5 7446 7447 7448 7449

7/
BCD to 7 segment Decoder/Driver
4 BCD
( .)7 -5 7
A B C D E F G . ( )8 -5
.7446 16 .8
78.
.
( )0 . sink 40
. 16 8 .
F B
G
E C
D
( )7 -5

( )8 -5 7446
7446 3
.
Ripple Blanking Input, RBI
( )0
.

. Lamp Test, LT
( )9 -5 7447

.
Blanking Input, BI/Ripple Blanking Output, RBO
( )1
. RBO
. ( )5-9 .7447 4-5 7446 7447

.Vcc
79.
.

LT RBI 8 4 2 1 RBO A B C D E F G
0 H X L L L L H L L L L L L H
1 H X L L L H H H L L H H H H
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
X X X X X X L H H H H H H H
H L L L L L L H H H H H H H
L X X X X X H L L L L L L L
4-5 7446 7447
7448 7446
7447
( .)10 -5
) .(1
.

.
( )10 -5 7448
80.
.
( )11 -5 7449
7448
.
Blanking Input, BI

( )0 . 16
8 .
( )11 -5 7449
0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1
RBI RBI RBI RBI

7447 7447 7447 7447
RBO RBO RBO RBO
( )12 -5
RBI RBO ( ) .
006.4 6.4 . 006.400 6.4
. ( )12 -5 .
RBI .
RBO . RBO RBI
.
(.)13 -5
81.
.
0 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
RBI RBI RBI RBI

7447 7447 7447 7447
RBO RBO RBO RBO
( )13 -5
5-5 74LS137 8/3

8/1

3 to 8 Decoder/1 of 8
Demultiplexer with input latch
3 A B C
Y0 .Y7 ( )14 -5
74LS137
( .)0 ( )14 -5
. 16
8 .
.5-5 E 2 5
E1 .6 E2=0 .E1=1
Latch Enable, LE A
B C . .
E1 Demultiplexer
E1 A B .C .
82.
.
Input Output

E2 C B A

H L H X X X S S S S S S S S
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H L L H H L H H H H H H
L L H L H L H H L H H H H H
L L H L H H H H H L H H H H
L L H H L L H H H H L H H H
L L H H L H H H H H H L H H
L L H H H L H H H H H H L H
L L H H H H H H H H H H H L
= X = L Dont care = H Low = S High . Stable
5-5 74LS137
6-5 74LS138 8/3

8/1
3 to 8 Decoder/1 of 8
Demultiplexer
3 A B C
Y0 .Y7
( )15 -5 ( .)0 ( )15 -5
74LS138 . 16 8
.
.6-5 3
G2A G2B .G1 G2A G2B
G1 . Demultiplexer G2A
G2B A B .C 74LS138 ()
Propagation delay 20 6.3 . 74S138
7 49 .
83.
.
Input Output

G1 C
B A

H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H L L H H L H H H H H H
L L H L H L H H L H H H H H
L L H L H H H H H L H H H H
L L H H L L H H H H L H H H
L L H H L H H H H H H L H H
L L H H H L H H H H H H L H
L L H H H H H H H H H H H L
= X = L Dont care = H Low . High
6-5 74LS138
7-5 74LS139 4/2

4/1
Dual 2 to 4 Decoder/1 of 4
Demultiplexer
2 A B
Y0 .Y3
( .)0 ( )16 -5
. 16 8 .
( )16 -5
74LS139 .7-5
E .
. Demultiplexer
E A .B 74LS139 ()
Propagation delay 19 6.8 . 74S139 6
60 .
84.
.
Input Output

B A

H X X H H H H
L L L L H H H
L L H H L H H
L H L H H L H
L H H H H H L
7-5 74LS139
8-5 74145 / ( )
)BCD to Decimal Decoder/Driver (Open Collector
4 A B C D
.
.
.
( )1001
. 43 24
. ( )17 -5 . 16
8 .
83 D .
( )17 -5 solenoid
74145
.
7445 .
85.
.
9-5 74154 74LS154 16/4 16/1

4 to 16 Decoders/Demultiplexers,
4 A B C D
.15
.
.
( )18 -5 . 24
12 .
G1 G2
( )1
( .)1
. demultiplexer

.
74154 21 34 .
( )18 -5 74LS154 15
74154
9 .
10-5 2 74155 4/2 4/1

74155 2 4 ( .)19 -5 1Y0
1Y3 2Y0 .2Y3 . 1G
1C . 2G 2C .
A B
A .B 74155 18 25 .
16 .8 74LS155 17
6 . .
86.
.
11-5 74156 74LS156

2 4/2 4/1
74156 74LS156
74155
( )19 -5
.Open Collector

Vcc
4.7 . 74156
20 25
. 74LS156
31 6 .
( )19 -5 74155
Encoders 12-5
.

. n . 2n
8 3 8-5 8 3
.
87.
.

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
8-5 8 3

D0 D1 D2 D3 D4 D5 D6 D7
A0 OR

A1 :
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2
A2 = D4 + D5 + D6 + D7

( )20 -5 8 3 OR ( .)20 -5
.
13-5 74147 10 4
10 to 4 lines priority encoder
9 4 ( .)21 -5

. I1=0 1110 .
9 I0
1111
.
88.
.

. I9 I8
I0 . 16
.8 ( )22 -5
74147

.
( )21 -5
74147
Vcc
7X4.7K
7 8 9
4 5 6
0 1 2 3
( )22 -5 74147
89.
.

1 2 3 4 5 6 7 8 9 D C B A
H H H H H H H H H H H H H
X X X X X X X X L L H H L
X X X X X X X L H L H H H
X X X X X X L H H H L L L
X X X X X L H H H H L L H
X X X X L H H H H H L H L
X X X L H H H H H H L H H
X X L H H H H H H H H L L
X L H H H H H H H H H L H
L H H H H H H H H H H H L
9 -5 X . 74147
14-5 74148 8 3
Encoder 8 to 3 with priority
74148 8

A0 A1 A2
(.)23 -5
7
0 .
EI ()0
( .)1
EO ( )0
( )1 Group
Signal, GS ( )0
( .)0
( )23 -5 74148
.
.10-5
90.
.

H X X X X X X X X H H H H H
L H H H H H H H H H H H H L
L X X X X X X X L L L L L H
L X X X X X X L H L L L H H
L X X X X X L H H L L H L H
L X X X X L H H H L L H H H
L X X X L H H H H L H L L H
L X X L H H H H H L H L H H
L X L H H H H H H L H H L H
L L H H H H H H H L H H H H
10-5 74148
15-5 Multiplexers/Data selector

MUX .
.select lines n
.2n ( )24 -5 .
S1 S0
D0
S0
S1
MUX D1
Y
1 4 Y
D0 D2
D1
D2
D3 D3
( )24 -5 .4
91.
.
D0 D3 .
S0 .S1
.
2 ( .)25 -5
.Enable, En OR .
S2=0

S0 S0
S0
S1 .
S1 S1
En
S2=1
En
S2
Y Y
Y
D0
D0
D1
D1 .
D2
D2
D3 OR
D3
.
( )25 -5 1/8 1/4

A B C D 2
S0
2 .
S0
S0
S1
S1 OR
S1
En
En
1 Y Y Y0
A0 D0
A1 D0 B0 Y1
B1 D1 C0
D1
D2

C1 D2
D1 D3
D0 D3 ( .)26 -5
3 4 .
( )26 -5 2 1/4
universal circuit

. AND OR NOT XOR .
1/4 :
Y S 0S1D0 S 0S1D1 S 0S1D2 S 0S1D3
92.
.
D0=D1=D2=0 D3=1 :
Y= S0S1
AND S0 .S1 D0=0 D1=D2=D3=1 :
Y S 0S1 S 0S1 S 0S1
= S0 + S1
OR S0 .S1
D0=D2=1 D1=D3=0 :
Y S 0S1 S 0S1
= S1
.S1 S0
.
D0=D3=0 D1=D2=1 :
Y= S 0S1 S 0S1
.XOR .

. .
( )27 -5
74150
16-5 74150 1/16

16 E0 E15 A B C D W
( .)27 -5
G ( )0
. 17 40 .
24 12 .
93.
.
17-5 74151 1/8

74151 1/8 8 D0 D7 A B C
G
W Y (.)28 -5
( )1 Y=0 W=1
.
74151 18 29
. 74LS151 12
6 . 74S151
9 45 .
TTL 8 GND 16
.Vcc
( )28 -5
74151
18-5 2 74153 1/4
2 1/4 1Y
1C0 1C3 1G
. 2Y 2C0 2C3
2G .
A .B ( )29 -5
.
1G=2G=0 2
4 2
1C0 2C0 1C1
2C1 . 8 16 .Vcc
74153 18
( )29 -5 36 . 74LS153
74153
18 6 . 74S153
9 45 .
94.
.
19-5 74157 74158 1/2
( )30 -5 74157 74158
74157 ( )30 -5 4 1/2

A2 A1 A0 Y 1A 1B 1Y 2A 2B
0 0 0 0 2Y 3A 3B 3Y
0 0 1 1
0 1 0 0 4A 4B .4Y A/B
0 1 1 1 A
1 0 0 0
1 0 1 1 .B G
1 1 0 1 . 74158 74157
1 1 1 0
. 8
11-5
16 Vcc .
1-5

. AND OR
:
1-5
74151 .11-5
A0 A1 A2
. :
95.
.
Y ABCD0 ABCD1 ABCD2 ABCD3 ABCD4 ABCD5 ABCD6 ABCD 7

D0=D2=D4=D7=0 D1=D3=D5=D6=1 A B C
A0 A1 A2 Y . 0
. G
0
1
0 20-5 74251
1
0
1/8
1 8 input Multiplexers (3 state
1
0 )output
A0 74151
A1 8 D0 D7
A2
0
Y W Y
W
( )31 -5 1-5
74151 3 A B .C

G
high
.impedance 16 8 .
( )32 -5 .
( )32 -5
74251
96.
.

B A D0 D1 D2 D3 D4 D5 D6 D7 W Y
H X X X X X X X X X X X Z Z
L L L L L X X X X X X X H L
L L L L H X X X X X X X L H
L L L H X L X X X X X X H L
L L L H X H X X X X X X L H
L L H L X X L X X X X X H L
L L H L X X H X X X X X L H
L L H H X X X L X X X X H L
L L H H X X X H X X X X L H
L H L L X X X X L X X X H L
L H L L X X X X H X X X L H
L H L H X X X X X L X X H L
L H L H X X X X X H X X L H
L H H L X X X X X X L X H L
L H H L X X X X X X H X L H
L H H H X X X X X X X L H L
L H H H X X X X X X X H L H
12-5 74251
Z high impedance
21-5 2 74253 1/4

)Dual 4 input multiplexers (3 state output
74153 1Y 2Y .
high impedance 1G 2G . .74153 16
8 16 .Vcc ( )5-33 .
22-5 4 74S258 1/2

)Quad 2 input multiplexers (3 state output
( )34 -5 74158
G ( )1 .high impedance
74158 . 16 8 16 .Vcc
97.
.
( )5-34
74S258
( )5-33
74253
23-5 Demultiplexer/Data distributor

.
.
. n
.2n ( )35 -5 4/1 4 D0 D1 D2 D3 .I
I AND S0
.S1 I .
( )35 -5 .I
I I=0 .

.
( )36 -5 74154
G1
98.
.
.
S1 S0 .

D0 .
74137 : 74138 74139 74154
D1 74155 74156
.
D2
24-5
D3 -1 (-5 )1 5 AND

I
-2 0000 :
( )35 -5
1100 1001 1110100 11001100
101010

-3

-4
1010, 1100, 0011, :

.0000

. .
-5
(-5 )4
I
-6 7442

(-5)6
( )36 -5 74154 -7 (-5 )6

( 7447
7) .
99.
.
-8 4 8/3 E 4/2
.32/5
A3 A2 A1 A0
-9
-10 4/2 AND
Y0
NOR
-11 4/16
Y1
-12 1/16 1/8
1/2
Y2 -13 11
-14 1/4
Y3
-15 1/8 :
(-5)1
Y ABC ABC ABC ABC
A0
A1 Y
A2
(-5)4
A0
A1
7447
A2
A3
(-5)6
100.
6
Arithmetic Circuits
. .
1-6
.
.
.
.
2-6 Arithmetic circuits

1-6
A=a3a2a1a0=1101 :B=b3b2b1b0=1011
1111
A= 1101
B= 1011 +
1 1000
b0 a0 bn an cn-1
HA FA
c0 cn
s0 Sn
( )1 -6 ( )2 -6

4 4 A
a0=1 B b0=1 S0=0 c0=1
. a0 b0 S0
.c0 2 Half Adder,
.HA ( )1 -6 .
102.
. .
n cn-1 n A
an n B bn Sn cn .
3 cn-1 an bn Sn .cn
.Full Adder, FA ( )2 -6
.
b3 a3 c2 b2 a2 c1 b1 a1 c0 b0 a0
FA FA FA HA
C3
S3 S2 S1 S0
( )3 -6 4
A B 2
3 . ( )3 -6 A B
3 .
. .
3-6 Half Adder circuit

a0 b0 s0
.c0 1-6 .
:
0 0 + 0
= 0 0 ()1-6
= a0 b0
c0 = a0b0 ()2-6
.XOR ( )1 -6 ( )2 -6
( .)4 -6 S0 XOR S0
1-6 .XOR
c0 AND c0 .
103.
. .

b0 a0 S0 c0
b0 a0
XOR 0 0 0 0
0 1 1 0
S0 1 0 1 0
1 1 0 1
1-6
c0
.
( )4 -6 4-6 Full Adder, FA
cn-1
an bn Sn cn . 2-6
. Sn cn :
=

1 + 1 +

1 + ()3 -6
=
1 + 1 +
1 + 1 ()4 -6
( )3 -6 ( )4 -6 (.)5 -6
an bn cn-1
Cn-1 bn an Sn cn
0 0 0 0 0
an bn cn-1 0 0 1 1 0
Sn 0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
F. A 1 1 0 0 1
1 1 1 1 1
2-6
Cn
Cn Sn
-
-
( )5 -6
104.
. .
( )1 -6 Sn XOR a0 .b0
cn-1 Sn
XOR ( )6-6 an bn bn an
.cn-1 Sn
:
an bn cn-1 an bn cn-1
Sn
H.A H.A
Sn
Cn
Cn
( )7 -6
( )6-6

Sn=(an bn) cn-1 )(5-6

2-6 ( )6-6 cn :
Cn= an bn + (an bn)cn-1 )(6-6
.
( )6-6 ( )7 -6
.
OR cn .
5-6 Binary subtraction

. :
2-6
.A=1101 ones complement = 0010
.
:
105.
. .
A=1101 a0
=0010 a1 4
1+ a2
1 0000 a3 bit

b0
: adder
b1
A + + 1 = 0 )(7-6
-A : b2 Carry
-A=+1 )(8-6 b3
( )8 -6
S2 S1 S0
( .)1 + ( )8 -6/ 4
:
A B = A + + 1 )(9-6
B C = B + + 1 )(10-6

.
( )8 -6 4
A B
4 3 S0 S1 . S2
XOR

( )9 -6
7483 . S1 ( )8 -6
A S1=0 A
.S1=1 S2 B ( )S2=0 ( .)S2=1
A B S0 . S2=S1=S0=0
.A+B S2=S0=1 S1=0 A+ +1
106.
. .
.A-B A B
S0 S1 S2 .
6-6 7483 4
4 bit Parallel Adder
4 A B
C0 4 S1,S2,S3,S4
.Cout ( )9 -6 .
5 12
16.
( )10 -6
74LS283
7-6 74LS283 4
4 bit Parallel Adder
7483 16
8 TTL . (-6
)10 .
. ( )11 -6 7483
8 8 . .
B8 B7 B6 B5 A8 A7 A6 A5 B4 B3 B2 B1 A4 A3 A2 A1
C1 C1
7483 7483
Cout S8 S7 S6 S5 Cout S4 S3 S2 S1
( )11 -6
4
107.
. .
8-6
Ripple Carry Adder and Look Ahead Carry adder
parallel
. .carry
ripple carry
. (-6
)3 . n an bn
n-1 an-1 bn-1 cn-1 cn
.n propagation c0
. T ( )
nT n .

a1 b1 c0
.look ahead adders

.

Cout1
S1 FA a1 b1 c0
. Cout
( )12 -6 :
FA a1 b1
generated carry . :
Cg1=a1 b1 ()11-6
c1
a1 b1 . propagated carry
:
Cp1=(a1+b1)c0 ()12-6
:
Cout1=Cg+Cp
(Cout1= a1 b1+(a1+b1)c0 )13-6
( )12 -6 Cout1 . Cout1
. :
108.
. .
Cout2=Cg2+Cp2
=a2 b2+(a2+b2)Cout1
:
}Cout2=a2 b2+(a2+b2){a1 b1+(a1+b1)c0 ()14-6
:
Cout3=Cg3+Cp3
=a3 b3+(a3+b3)Cout2 ()15-6
Cout2 ( .)14 -6 ( )14 -6 ( )15 -6

A .B
. ( )13 -6 3 .
A B c0
.
a3 b3 c2 a2 b2 c1 a1 b1 c0
FA3 FA2 FA1
S3 S2 S1
( )13 -6 3
7483 74283 4 .
4
.
Comparators 9-6
A B
A=B
A>B .AB A=B AB B
AND
A>B . AB3 A3=1
A>B AND A3 3 3 =0
. A=B AB2
A>B . AND A2 2
AND XOR A3 .B3 AB AB AB . A B
2 3 4 AB iA=B iAB AB3 x x x x x x H L L
A3<B3 x x x x x x L H L
A3=B3 A2>B2 x x x x x H L L
A3=B3 A2<B2 x x x x x L H L
A3=B3 A2=B2 A1>B1 x x x x H L L
A3=B3 A2=B2 A1<B1 x x x x L H L
A3=B3 A2=B2 A1=B1 A0>B0 x x x H L L
A3=B3 A2=B2 A1=B1 A0<B0 x x x L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H
A3=B3 A2=B2 A1=B1 A0=B0 x x H L L H
A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L
A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L
3-6 7485
11-6 74LS682 74LS684 74LS688

8
A3 A2 A1 A0 A7 A6 A5 A4
Vcc
A3 A2 A1 A0 A3 A2 A1 A0
iA>B A>B iA>B A>B

iA=B 7485 A=B iA=B 7485 A=B

iAB .A=B (19 -6 19 -6)
(20 -6 20 -6) . 1 74LS682 74LS684
A>B .74LS688
1 G Vcc 20 1 A>B Vcc 20

2 A0 A=B 19 2 A0 A=B 19
3 B0 B7 18 3 B0 B7 18
4 A1 A7 17 4 A1 A7 17
5 B1 B6 16 5 B1 B6 16
6 A2 A6 15 6 A2 A6 15
7 B2 B5 14 7 B2 B5 14
8 A3 A5 13 8 A3 A5 13
9 B3 B4 12 9 B3 B4 12
10 GND A4 11 10 GND A4 11
(19 -6) (19 -6)

74LS688 74LS68274LS684
12-6
-1 Sn cn ( )3 -6 (.)4 -6
-2 ( )5 -6 .
-3 7483 8.
-4 3 12 .74283
-5 .7483 .
:
A1=10001100, B1=11001100
A2=11001010, B2=10010011
A3=01011111, B3=10100111
A4=10011001, B4=00111101
113.
. .
(20 -6)
74LS688
(20 -6)
74LS682 74LS684
-6 4.
-7 ( )8 -6 3 S0, S1, S2
.
-8 5 .7485
A=B A>B AB, A<B .
114.
7
Latches And Flip Flops
..
1-7
.combinational circuits

.
.
.sequential circuits
.
.
.
R-S 2-7
latch
R
Q
bistable multivibrator
.
Q Q Q=0 =1
S Q .
S ( .)1 -7
Q
R
Reset S Set
. NOR
R
(1 -7) NAND (1 -7) .
( )1 -7 RS ( )NOR R S
R=1 S=0
Reset Q S=1 R=0 Q=1 Set
. ( )NAND R=1 S=0 Reset
Q S=1 R=0 Q=1 Set .
1-7 . S=R=0
Q Q NOR
NAND Q Q
. S=R=1
116 .
..
NOR .NAND
( )1 -7 .1-7
( )1 -7 .
NOR
S=1, R=0, Q=0
NOR NAND
R S Q Q
S=1, Q=0
0 0
0 1 1 0 1 0

1 0 0 1 0 1
1 1
Q Q
1-7 ()1 -7

Q .
S
R=0, Q =0 Q=1
S=1
R
R=0 .Q=1
- RS Q=1 .
S Q (.)1 -7

R Q
. ( )2 -7
- RS
.
( )2 -7 RS
1-2-7 RS
bounce
. (3 -7)
. RS .debouncer (3 -7)
. 1 R=1 S=0
R1 .Q=0
1 2 R=0 R2 S=1
.Q=1 S S=0
S=R=0 . S=1
117 .
..
.
. (.)3 -7
1 2
R R1 R2

2 2 Q
Vcc S

1 Vcc R 2 1
1
( )3 -7 RS
3-7 74279 RS
( )4 -7 .
4 .RS
S
R
S .R
16 Vcc 8
.
.
( )4 -7 74279
4-7 RS
R
Q
Clock
S R
CK

S
clock
Q
S . ( )5 -7
CK
R .
CK=0 AND
( )5 -7

118 .
..
. CK=1 AND R S
.
1-7
Q RS
S
R S CK
R (.)6 -7

CK CK=1 R S

Q
. ( )6 -7
( )6 -7 1-7
.
5-7 D
( )7 -7 . D RS
R S
R S .
D=1 CK=1 Q . ( .)7-7 Q
D . Q D Delayed
.D
D
Q CK D Q Q
S D
1 1 1 CK
CK 1 0 0
0 x
R X

do not care

( )7-7 D
119 .
..
6-7 7475 D
7475 4 D ( )8 -7 . Q
Q . 1 2 CK1
3 4 .CK2 Vcc 5 .12
7-7 Flip Flops

.
CK=1
.CK
R S CK=1
CK
( )8 -7 74ls75 . ( )9 -7
.
Q Q CK
S S
CK CK
R R .
Q
Q
CK .
CK

S R CK Q S R CK Q . ( )9 -7
1 0 1 1 0 1
0 1 0 0 1 0 .
0 0 0 0 CK

1 1 ? 1 1 ?
RS .
RS
2-7
( )9 -7 RS
CK S R
( .)10 -7
:
120 .
..
S=R=0 1 .
S=0, R=1 2 .
S=1, R=0 3 .
S=0, R=1 4 .
S=1, R=0 5 .
S=1, R=0 6 .
1 2 3 4 5 6
CK
Q R CK S
( )10 -7 2-7 Q
8-7 trigger

.

. ( )11 -7 AND

.
A ( .)11 -7
RS
.
121 .
..
A B S
C S Q
A CK
R
B R
C ( )11 -7 trigger

9-7 JK
JK . J K
. RS

J .R=S=1
S Q
JK
CK

R JK
K
J K .

( )12 -7 JK .Toggle
Q=1 J=K=1
)J K CK Q(n+1 ()
0 0 )Q(n
( .)Q=0 Q=1 J=K=1
1 0 1
0 1 0 () ( .)Q=1 (-7
1 1 )12 .

RS
2-7 Q K
JK Q . J
2-7 . JK
J=1, k=0 .Q(n)=0
AND AND K=Q=0
122 .
..
. R S Q(n+1)=1
Setting . ) Q(n 1 . .J=K=1
Q=0 AND
AND Q .
R S Q=1 .
J=K=1, Q=1 .Q=0 J=K=0
. ( )12 -7 2-7 .
J K D .RS
JK
.
10-7 Asynchronous Inputs

J K
synchronous
K
Q
.
CK

.
J

Q
( )13 -7 JK J Q=0
CK

K

. ( )13 -7
JK
. CLR
Q
. PRE
.CK .
123 .
..
11-7 T
T JK
T J K
J Q .T J=K=1
. T
CK
T=1 .
K .
( )14 -7 .
T toggle
( )14 -7 T
.
12-7 74ls74 D
( )15 -7 74ls74
( )16 -7 74ls76
D Vcc 14
7 .
. CLR PRE
. ( )15 -7 .
13-7 74ls76 JK
JK Vcc 5
13 .
124 .
..
. CLR PRE
. ( )16 -7 .
14-7 Master Slave Flip Flop

( )
.
edge triggered
.
( )17 -7 JK 3-7 .
( )17 -7 RS .
master .slave .
. Q
Q () .JK JK
. (.)17 -7
K
Q
CK
CK
Master Slave
( )17 -7 JK Master Slave
Q )J K CK Q(n+1
J 0 0 )Q(n
CK 1 0 1
K 0 1 0
1 1
( )18 -7

3-7
JK
125 .
..

. CK ( )
.
.
CK
. Q
. ( )18 -7
3-7 .
.
15-7 7473 JK
JK
. J K CK=1
.
CLR . 74ls73 7473
. Vcc 4 GND
.11 ( )19 -7 .
( )19 -7 7473 74ls73
16-7 74107 JK
JK
. J K CK=1
.
126 .
..
CLR . 74ls107 74107

. Vcc 14
GND .7 ( )20 -7 .
( )20 -7 74107 74ls107
17-7 74109 JK

JK
.
CLR
PRE . ()21 -7
( )21 -7
. Vcc
74109
16 GND .8

( )22 -7 74112 74113
127 .
..
18-7 74112 JK
JK .
CLR PRE . (22 -7)
. Vcc 16 GND .8
19-7 74113 JK
JK .
PRE . (22 -7) . Vcc
14 GND .7
20-7 74116 4
4 .
E 0 E1 .
D .Q Q D
.transparent
MR . ( )23 -7 .
Vcc 24 GND .12 24.
( )23 -7 74116
128 .
..
21-7 74173 D

4 D CLK
E 0 E1 .
. Q
.

NOR OE0
OE1
OE0 OE1
.
.
MR
. ( )24 -7
. 16 16
( )24 -7
74173 Vcc 8 .GND
.
22-7 74174
D
D

Q .
MR
. 16
16 Vcc 8
( )25 -7
74174 .GND ( )25 -7 .
129 .
..
23-7 74175 D
D

.
Q . Q MR

. 16 16 Vcc
8 .GND ( )26 -7
.
( )26 -7 24-7 74273

74175
D
D

.CLK MR
.
20 20 Vcc
10 .GND ( )27 -7
.
25-7 74373 74374

D
( )27 -7
74273
D
CLK .74374 CLK
74373
.transparent
OE
.
130 .
..
. ( )28 -7 . 20
20 Vcc 10 .GND
( )28 -7 74373 74374
26-7
1-26-7 Propagation delay time

.
. ( )29 -7
:
-1 Tplh ( )
%50 . (29 -7).
-2 Tphl ( )
( ) %50 . (29 -7).
CLR
. PRE
131 .
..
2-26-7 Set up time

ts
CLK CLK
%50 %50
( R S J K D )T
Q
%50 %50 Q .
Tphl
Tplh

( )29 -7 . ()30 -7

.
R S J K D T .
CLK 3-26-7 Hold time

th ( R S
ts J K D )T
. ( )31 -7
( )30 -7 ts
.
R S J K D T
4-26-7
Maximum clock frequency
CLK fmax
th
.
( )31 -7 th

27-7

.
132 .
..
28-7
(-7)1 -1
S S
Q

R R
R S

(-7)1
RS
.
S
S Q Q
CLK
CLK

R
R -2
Q RS
(-7)2
CLK

CLK (-7.)2
2 D -3
S
RS
R RS -4
(-7)4 .
(-7)4
1

Ja Qa Jb Qb

CLK CLK
Ka Kb -5
D RS
(-7)7 -6
JK RS
Qb (-7)7 -7
-8
:
133 .
..
-9 30
37

1 -10 (-7
Qa
Ja Jb Qb )10
CLK CLK

Ka Kb
20
25
(-7)10
25
-11 RS
(-7)11
S Q
-12 ( )10 -7
CLK 10
R Q .
(-7)11
134 .
8
Digital Counters
..
1-8

. .

.
2 -8
Ripple (Asynchronous) Counters
Q
( )1 -8 3
T J K .

1 .
Q0 Q1 Q2

J0 Q0 J1 Q1 J2 Q2
CLK CLK CLK
K0 K1 K2 . (-8
)2
( )1 -8 3
Q2 Q1 Q0 1 2 3 4 5 6 7 8
0 0 0 0 CLC
1 0 0 1
2 0 1 0 Q0 0 0 0 0 0
1 1 1 1
3 0 1 1
4 1 0 0 0 0 1 1 0
Q1 0 0 1 1
5 1 0 1
6 1 1 0
Q2 0 0 0 0 1 1 1 1 0
7 1 1 1
8 0 0 0
( )2 -8
1-8
.
3
. 001
010 111
. 7 8
136.
..
000 111 .1-8 2n

n .
ripple .
( )3 -8
CLC

Q0 3Tp Tp

Q1 3 .
Q2
T0p

T1p

T2p

( )3 -8

. 10 .
100=1010 . (
) :
1
=Fmax =10 mega Hertz ()1-8
100x10 9
.
3-8
2n
n . 18
.2
9 10 . .
.
( )1010 . ( )4 -8 .
4 3 8
4 . ( ) Q1 Q3
( )1010 . CLR
. ( )5 -8 .
glitch Q1 .
137.
..
Q1 .
CLR .
oscilloscope
.Logic analyzer .
.
1 Q0 Q1 Q2 Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CLK CLK CLK CLK
K0 K1 K2 K3
CLR CLR CLR CLR
( )4 -8
1 2 3 4 5 6 7 8 9 10
CLK
Q0
Q1
Q2
Q3
CLR
( )5 -8
.2 Q0
. Q1 Q0
. Q3
.
138.
..
4 -8
Synchronous Counter
.
.
.
J K .
.

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 d 0 d 1 d
0 0 1 0 1 0 0 d 1 d d 1
0 1 0 0 1 1 0 d d 0 1 d
0 1 1 1 0 0 1 d d 1 d 1
1 0 0 1 0 1 d 0 0 d 1 d
1 0 1 1 1 0 d 0 1 d d 1
1 1 0 1 1 1 d 0 d 0 1 d
1 1 1 0 0 0 d 1 d 1 d 1
2-8 3
3 . 2-8 .
. 2-8 (-8
.)6 d do not care
. Q0 J0=1 K0=0
setting .JK Q0
J0=1 K0=1 .
Q0 J0=1 K0
.d d
d . d
( J0 K0 ( ))6 -8 d=1
. J0 K0 d=1 .J0=K0=1
J2 K2 d=1
.
( )7 -8 3 .
4 5 J K
139.
..

( )8-8 .
( )6 -8 3
1 Q0 Q1 Q2
J0 Q0 J1 Q1 J2 Q2
CLK CLK CLK
K0 K1 K2
CLK
( )7 -8 3
01111
Q0 Q0

. n .
T= (n-2)Ta + Tff. ()2-8
140.
..
Ta Tff .
. nTff
(.)2 -8
1 Q0 Q1 Q2 Q3 Q4
J0 Q0 J1 Q1 J2 Q2 J3 Q3 J4 Q4
CLK CLK CLK CLK CLK
K0 K1 K2 K3 K4
CLK
( )8-8 5
.
J K .
. 3-8
( )9 -8
:
J0=K0=1, J1= Q3 Q0, K1=Q0, J2=K2=Q1Q0, J3=Q2Q1Q0, K3=Q
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 0 1 0 d 0 d 0 d 1 d
1 0 0 0 1 0 0 1 0 0 d 0 d 1 d d 1
2 0 0 1 0 0 0 1 1 0 d 0 d d 0 1 d
3 0 0 1 1 0 1 0 0 0 d 1 d d 1 d 1
4 0 1 0 0 0 1 0 1 0 d d 0 0 d 1 d
5 0 1 0 1 0 1 1 0 0 d d 0 1 d d 1
6 0 1 1 0 0 1 1 1 0 d d 0 d 0 1 d
7 0 1 1 1 1 0 0 0 1 d d 1 d 1 d 1
8 1 0 0 0 1 0 0 1 d 0 0 d 0 d 1 d
9 1 0 0 1 0 0 0 0 d 1 0 d 0 d d 1
10 1 0 1 0 d d d d d d d d d d d d
11 1 0 1 1 d d d d d d d d d d d d
12 1 1 0 0 d d d d d d d d d d d d
13 1 1 0 1 d d d d d d d d d d d d
14 1 1 1 0 d d d d d d d d d d d d
15 1 1 1 1 d d d d d d d d d d d d
3-8
141.
..
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CLK CLK CLK CLK
K0 K1 K2 K3
CLK ( )9 -8
5 -8 Down Counters
.
Q2 Q1 Q0
0 0 0 0
1 1 1 1 . ( )10 -8 .
2 1 1 0
3 1 0 1 Q
4 1 0 0 .
5 0 1 1
6 0 1 0 Q0
7 0 0 1 Q0
8 0 0 0
Q1 Q1
4-8

3 .
4-8 .
1 Q0 Q1 Q2
J0 Q0 J1 Q1 J2 Q2
CLK CLK CLK
K0 K1 K2
( )10 -8 3
142.
..
6 -8
Up/Down Counter
. .

.

. :
0, 1, 2, 3, 4, 3, 2, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2,

. ( )11 -8
. ( )12 -8
.
.
J0 Q0 J1 Q1 J2 Q2
CLK CLK CLK
K0 K1 K2
Up/Down
( )11 -8 3
143.
..
J0 Q0 J1 Q1 J2 Q2
CLK CLK CLK
K0 K1 K2
Up/Down
( )12 -8 3
7 -8 7490
4
.
( )2
(
.)5
. CLK0
CLK1
.

( .)10
( )13 -8 7490
.
MR1 MR2
. MS1 MS2
( )
. 4 . 13 4
Not Connected, NC .
14 5 Vcc 10 .GND 30
. 74ls90 42 .
144.
..
30 9 .74ls90 ( )13 -8 5-8

. X .
MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3

H H L X L L L L
H H X L L L L L
X X H H H L L H
L X L X Count
X L X L Count
L X X L Count
H L L X Count
5-8 7490
8 -8 7492 12
4
.
(
)2
( .)6
.
6 CLK0
CLK1
.
( )14 -8 7492 12
( .)12

. MR1 MR2
MR1 MR2 Q0 Q1 Q2 Q3
H H L L L L
L H Count
H L Count
L L Count . 4
. 2 3 4 13
6-8
7492 Not Connected, NC
. 14
145.
..
5 Vcc 10 .GND 28.

74ls90 42 . 28
9 .74ls90 ( )14 -8 6-8
.
9 -8 7493 4
4
.
(
)2 (
.)8
. CLK0
CLK1
.

( )15 -8 7493
( .)16

. MR1 MR2
MR1 MR2 Q0 Q1 Q2 Q3
H H L L L L

L H Count
H L Count . 4
L L Count
. 4 6 7
7-8 13 Not Connected, NC
7493
.
14 5 Vcc 10 .GND 40
. 74ls90 42 . 28
9 .74ls90 ( )15 -8 7-8
. .
146.
..
10 -8 74160 74162
4
( )10
.

PE
.
D0 D3

. CET
CEP
.
( )16 -8 74160
.CLK

MR
CLK CEP CET Dn Qn TC
L X X X X L L
H X X L Dn Dn L .
H H H L ) H(9 X
H X L X H X TC
X L
8-8 74160
)1001( 9
TC . 16
Vcc 16 .8 ( )16 -8
8-8 . 32 61 .
11 -8 74161 74163 4
74160 74162
15 9 . TC 15
147.
..
9 . 74161 74163
.
12 -8 74LS168 74LS169
/
74168 4
(
)10
D
U/

.

.

D0 D3
PE

( )17 -8 74LS168
74LS169

. TC (
)9 .
. CEP CET
. 16 16 Vcc 8
. 32 74168A 70 . (-8
)17 9-8 . 74169
74168 15 TC
15 9 .
148.
..
U/ CLK Dn Qn TC
X X X L Dn Dn H
H L L H ) L(9,15 X
L L L H X
X H X H X
X H
9-8 741LS168 74LS169
13-8 74190 74191 /

74190

U /D

.

D0 D3
PE
.
.

( )18 -8 74190
74191
CE

. TC ( )9

( ) .
. RC .
16 16 Vcc 8 . 25
65 . ( )18 -8 . 74191
149.
..
74190 15 TC
15 .
14-8 74192 74193 /

74192 74190
CLKu CLKd
.
. CLKd
CLKu .
D0 D3 PE .
MR

. TCu

9

TCd

.
( )19 -8 74192 16
74193
16 Vcc
8 . 32 65 . ( )19 -8
. 74193 74192 15
TCu . TCd
150.
..
15 -8 74LS197 4
4
.
( )2
(
.)8

CLK0 .

CLK1 .
MR

( )20 -8 74LS197 .

D0 D3
PE .
CLK Dn Qn
14 14 Vcc
L X X X L
H L X L L 7 . 40
H L X H H
16 . (-8
H H X
)20 10-8
.
10-8 74LS197
16 -8 74LS290
4 2 5
.
. MR1 MR2
.
MS1 MS2
.)1001( 9 .
. 14 14 Vcc 7
151.
..
2 6 .Not connected, NC 42 9
. ( )21 -8 11-8 .
17 -8 74LS293 4
4
2
8
.

.
MR1 MR2

. 14
( )21 -8 74LS290
14 Vcc
7 1 2 3

6 Not
MR1 MR2 MS1 MS2 Q3 Q2 Q1 Q0 .connected, NC 42
H H L X L L L L
H H X L L L L L 9 .
X X H H H L L H ( )22 -8
L X L X
X L X L 12-8 .
L X X L
X L L X
11-8 74LS290
MR1 MR2 Q3 Q2 Q1 Q0
H H L L L L
H L
L H
L L
12-8 74LS293
152.
..
18 -8 74LS390

2
3
( .)5
4

3
.
( )22 -8 74LS293

()
2 : 4 5 10 20 25
50 .100

.
MR

. 16
16 Vcc
8 .
55
15 . ( )23 -8
.
( )23 -8 74LS390
19 -8 74LS393 4
4 (
.)16 .
. 14 14
153.
..
Vcc 7 . 35 15 .
( )24 -8 .
20 -8
1-20-8

.
( 1 ).

.
10

10
( )24 -8 74393 1
.

. 1
50 60 .
220 5 ( ) 5.
50 60 .
1 5 . ( )25 -8

. 4 :
-1 1 50
( 10 ) .5 74160
( )26 -8 5
5 ( )27 -8 6
MR .
-2 1 60 .74160
10 ( )26 -8 6
( )27 -8 .
-3 2 (26 -8 .)27 -8
154.
..
-4 ( )26 -8 .
12
. ( )28 -8 74160
.
50 1
220
50

10 5

10 6 10 6 10
( )25 -8
1
MR
PE
CET 74LS160 TC
CEP
CK

( )26 -8 74160
155.
..
MR
PE
1 CET TC
74LS160
CEP
CK

Q3 Q2 Q1 Q0
( )27 -8 74160
6 5
0 0 0 1
D3 D2 D1 D0
1 MR J Q
PE CK
CET 74LS160 TC K
CEP CLR
CK
1
Q3 Q2 Q1 Q0 Q0

( )28 -8
156.
..
21-8
-1 (-8.)1
-2 1 8
.
1
J0 Q0 J1 Q1 J2 Q2
Clock
>CK >CK >CK
K0 K1 K2
(-8)1
-3 ( ) 9 : 11 13 14 25 .50 .
-4
.3
-5 2
D0 Q0 D1 Q1 D2 Q2
.
>CK >CK >CK -6
Clock
.
(-8)11
-7 3
0
.
-8

00 :
4
10 11 00 .
16 16 .JK
Clock
CK
-9 8 0 : 9

15 1 8 2 7 3 6 4 5
0 .
(-8)13
-10
4 . U/D
:
0, 1, 2, 3, 4, 5, 4, 3, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2, 3, 4, 5, 4, 3, 2, 1
157.
..
-11 (-8.)11
-12 10000 .100000 .
-13 (-8 )13 16 .
.
-14 1000 .74160
-15 .30000
-16 ( )25 -8
.
-17 .
.
-18 15
.
-19 (-8 )13
.
-20 .
158.
-1
9
Shift Registers
..
1-9
shift registers .
.

.
. .
2 -9
.D D
CK . Q . Q D
Q CK D .delay
( )1 -9 D .
1 D Q 1 0 D Q 0
CK CK
( )1 -9 D
3 -9
. ( )2 -9
.

( )2 -9
160.
..
4 -9
Serial In Serial Out
( )3 -9 4 D
.CK
. 1-9
.1011 4
.
Q0
Q1 Q2 Q3
1011 D0 Q0 D1 Q1 D2 Q2 D3 Q3
CK CK CK CK
FF0 FF1 FF2 FF3

CK
( )3 -9
CK D0 Q0 Q1 Q2 Q3 CK
0 0 0 0 0 0
D0
1 1 1 0 0 0
2 1 1 1 0 0 Q0
3 0 0 1 1 0
4 1 1 0 1 1 Q1
1-9 4 Q2
1011 Q3

CK D0 Q0 Q1 Q2 Q3 ( )4 -9
4 1 1 0 1 1
5 0 0 1 0 1
6 0 0 0 1 0
7 0 0 0 0 1
2-9 D0
8 0 0 0 0 0 4
2-9 Q3

. ( )4 -9
( )3 -9 D3
CK .
161.
..
5 -9
Serial In Parallel Out
( )3 -9 .
Q0 Q1 Q2 Q3 .
.
6 -9
Serial Right To Left Shift
( )3 -9
. .
( )5 -9 .
Q2
Q0 Q1 Q3
D0 Q0 D1 Q1 D2 Q2 D3 Q3
CK CK CK CK

FF0 FF1 FF2 FF3
CK 1011
( )5 -9
( )5 -9 1011
1-9 .2-9
(.)4 -9
7 -9

.
162.
..
. ( )6 -9 .
.
( )6 -9 Chold=0

. CS/P . CS/P=1
.CL/R
CL/R=1 ( .)DL
CL/R=0 ( .)DR
CS/P=0
AND ( )X0, X1, X2
.
.
( )6 -9
8 -9 7491 8
8 bit serial left to right shift register
7491 8 .
Dsa Dsb .AND Dsa=Dsb=1 1
. Dsa=Dsb=0 .
.
163.
..
Q7 ( )7 -9
. 3,5
18 . Q0
Q1 Q2
.Q7
.
( )7 -9 clear .
7491 .
5 10 14.
9 -9 7494 4
4 bit parallel in serial out shift register
4
)Ds( 7
D0a, D0b, D0c, D0d
.D1a, D1b, D1c, D1d
Pl0=1
Pl1=0
Pl1=1 Pl0=0
D0 .D1
MR .
CK
.
( )8 -9
3,5 Propagation
7494
delay 25 . ( )8 -9
. 5 12 16.
10 -9 7495 4
4 )Ds( 1
. D0, D1, D2, D )SP( 6
164.
..
.

CK2
D0, D1, D2, D3 Q0, Q1,
Q2, Q3 . DS
CK1
Q0 Q1 Q1
Q2 Q0
.
( )9-9
7495
Q3 Q2 Q2 Q1
Q3 Q3 D2 Q2
D1 . .D3
CK1 CK2 .
39 36 . ( )9-9
14 14 .7
11 -9 7496 5

5
D0, D1, D2, D3 PE
.Ds
CK
PE
DS Q0 Q0 Q1 Q1 Q2 .

Q0 Q4
( )10 -9 DS .
7496 MR .
48
165.
..
25 . ( )10 -9 5 12
16.
12 -9 74164 8

8 bit serial in parallel out shift
register
8
Q0 Q7 ( .)11 -9
Dsa Dsb

.AND
( )11 -9
Dsa Dsb
74164

Dsb Dsa .
Dsa Dsb
.

Q0 Q0 Q1 Q1
Q2 .Q7 MR

. 37
36 . 14 14
7 .
( )12 -9
74165
166.
..
13 -9 74165 8
8 bit parallel in/serial in, serial out shift register
8 Ds
D0 .D7 Q7 .Q7 SH/LD
D0 D7 Q0 .Q7
SH/LD=1 Ds
.Q7 CK
hold . hold=1
. 42 26 . 16
16 8 (.)12 -9
14 -9 74166 8
8 bit parallel in/serial in, serial out shift register
8 Ds
D0 .D7 . PE PE =0
CK D
.Q PE =1 Ds Q0 Q1
Q2 . CK .
hold . MR
. 90 35 .
16 8 16 (.)13 -9
15-9 74194 4
4 bit bidirectional universal shift register
4 .
S0 S1 . S0=1 S1=1
D0 D3 Q0 Q3
.CK Q0 Q3 S0=1 S1=0
( Dsl .)2
167.
..
( )14 -9
74194
( )13 -9
74166
Q3 Q0 S0=0 S1=1
( Dsr .)7 MR
. 39 36 .
16 8 16 (.)14 -9
16-9 74195 4
4 D0
D3 PE =0 CK
D0 D3 Q0 .Q3 PE =1
Q0 Q3 J K .
CK . MR
168.
..
. 39 39 . 16
8 16 (.)15 -9
( )15 -9 74195
( )16 -9
74199
17-9 74199 8
8 D0
D7 PE =0 CK
D0 D7 Q0 .Q7 PE =1
Q0 Q7 J K .
CK . MR
. hold
. 90 35 . 24
12 24 (.)16 -9
169.
..
18-9 Ring Counters
D0 Q0 D1 Q1 D2 Q2 D3 Q3
CK CK CK CK

CK
( )17 -9 4
Q0 Q1 Q2 Q3
.
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
. ( )17 -9
3-9 4 3-9

.
presetting
.clear ( )17 -9 Q0=1
.3-9

.
4
3-9 4 n n .
Q3
( .)18 -9 4-9
8 4 2n n
.
170.
..
D0 Q0 D1 Q1 D2 Q2 D3 Q3
CK CK CK CK
Q3

CK
( )18 -9 4
Q0 Q1 Q2 Q3

0 1 0 0 0
1 1 1 0 0
2 1 1 1 0
3 1 1 1 1
4 0 1 1 1
5 0 0 1 1
6 0 0 0 1
7 0 0 0 0
4-9

19 -9
Time delay

. (-9
) 19
4 4 1 .
171.
..
CK=1
MHz 1
CK

= 4
( )19 -9

Serial To Parallel Conversion Of Data
.
. ( )20 -9
. ( .)21 -9
.
JK
. ( )
3 8 .
8
. AND .
( ) CK
( )
. AND
one shot JK
. UART
Universal Asynchronous Receiver Transmitter .
172.
..

.
.

D
1 8
J Q EN CK
CK

K Load
CLR 8
CK
CK

T 3
Q
Out
CLR
( )20 -9
D0 D1 D2 D3 D4 D5 D6 D7
2
Start bit Stop bits
( )21 -9
173.
..
20-9
-1
-2 4
. 10011101010001110
-3 5
.
-4 74195 8.
-5 74194 8
.
-6 .
-7 10 .D
-8 6 .
.
-9 .7
-10 6 7 8 .
-11 74195 16.
-12 .
-13 5 . 100.
174.
-1
10
Memory
..
1-10

.
() .
.
.
.
. .
semiconductors .
. () .
2-10 ( )
.bit .
4 .
( nibble ) .
8 byte
16 . 2 word .
() .
(1 -10)
( 4) (1 -10)
(1 -10) 64
() . 164
64 . 416 16 . 88
8 .
. 16 4 . 16
16 8 16 8 .

.
. 3
10.
176 .
..
1 1
2 1
2
3 3
2
3
4
5
6

7
8
13 ( )1 -10
14
62
15

63
64 16
3-10
. Write, WR
Read, RD .
.
.

.
. 8 .
.

.
.
.

2 . 4
16=42 8 256=82 .
177 .
..
.
( )2 -10 .
decoder .

.
Read, RD Write, WR
.
Active low :
RD WR
( )2 -10
WR . RD .

.
. RD / WR :
1-3-10
3 :
-1 .
-2 .
-3 WR
. ( )3 -10 .
2-3-10
3 :
178 .
..
-1 .
-2 .RD
-3 .
. ( )4 -10 .

11101100
011
0 1 0 0 1 1 0 0 1 2
1 1 0 0 0 1 0 0 0 1
2 1 0 1 0 0 0 1 0

3 1 1 1 0 1 1 0 0

4 0 1 0 0 1 1 1 1
5 1 1 0 1 1 0 1 0
6 0 0 0 0 1 1 1 1
7 0 1 1 0 1 0 0 0
RD WR 3
( )3 -10

11101100
011
0 1 0 0 1 1 0 0 1 3
1 1 0 0 0 1 0 0 0 1
2 1 0 1 0 0 0 1 0

3 1 1 1 0 1 1 0 0

4 0 1 0 0 1 1 1 1
5 1 1 0 1 1 0 1 0
6 0 0 0 0 1 1 1 1
7 0 1 1 0 1 0 0 0
2 RD WR
( )4 -10
179 .
..
4-10
Random Access Memory, RAM

.
Volatile
Read Only Memory , ROM
.Nonvolatile
RAM

. RAM
.
RAM

Bipolar
Static RAM Dynamic RAM
technology
MOS
.BiMOS
Bipolar MOS BiMOS MOS

( )5 -10
Static RAM, SRAM
Dynamic
Column
Row .RAM, DRAM
Q

.
& D

Read/

( )6 -10
.
180 .
..
. ( )5 -10
.
SRAM latch
Bipolar MOS BiMOS
. ( )6 -10 .
3 :
Row=1 Column=1
/ . = 0
.
./ = 0
/
= 1
.
D3 D2 D1 D0
A0

A1
A2
A3
A4
A5 3232
A6
A7
()
Q3 Q2 Q1 Q0
( )7 -10 4256
.
. (-10
181 .
..
)7 1024 4256 .
4 4 .
32 32 . 256 8 5 . A0
A4 32
. 4 8 .
.
A5 .A7
. 000
. 4 4
A5 A6 .
D0 D3
.
. CS 0 R / W 1
CS 0 . R / W 0 ()8 -10
.

A0-A7
Write
Read Read
D0-D3
Q0-Q3

( )8 -10
182 .
..
5-10
Dynamic RAM, DRAM
.

.
2 4 .
. ( )9 -10
CMOS . Row
source drain .

. .
( )10-10 . R / W 0
Din=1
Row=1 .
Refresh=0 .
( )11 -10 . Din=0

.
Refresh=0
Colum
Row=1 n
+
1 Colum
Dout Row n
-
Din=1

( )10-10 1
( )9 -10

( )12 -10 R / W 1
Dout .
. ( )13 -10
R / W 1 Refresh=1
183 .
..
.
.
Refresh=0
Colum
Row=1 n
0
Dout
Din=0

( )11 -10

Refresh=0
Colum
Row=1 n
1
Dout
Din=1

( )12 -10

184 .
..
Refresh=1
Colum
Row=1 n
1
Dout
Din=1

( )13 -10

6-10
Read Only Memory, ROM
.
Column .
Row
Vcc

. ROM
. PROM
( )14 -10
ROM
Electrically Erasable
Row
Column .Programmable ROM, EEPROM
Vcc ROM
Row

Vcc
( )15 -10 .Column
ROM
Column
. ( )14 -10 ( )15 -10
. . ( )16 -10 ( )17 -10
185 .
..
MOS ( 14-10 -10

.)15
Column Column
Row Row
Vdd Vdd
( )16 -10 ( )17 -10

ROM ROM
MOS MOS
( )18 -10 16 . 4
16 () .
.
.

.
.
.
. ( )19 -10 .
.
.

. 250
.
. PROM
.

20
.
186 .
..
1 1
1 1
164
A0-A3
1 1 1
1 1
D0 D1 D2 D7
( )18 -10 ROM
Column
Row
Vcc .
Erasable
.PROM, EPROM

( )19 -10
PROM .
Electrically Erasable PROM,
.EEPROM
187 .
..
7-10 2114 1 4
1024 4
1 A6 Vcc 18
.
2 A5 A7 17 450 . A0 A9
3 A4 A8 16 D1 D4
. WE
4 A9 15
A3 . CS
Intel 2114
5 A0 D1 14
6 A1 D2 13
. ( )20 -10 .
7 A2 D3 12
8 D4 11
9 GND 10
( )20 -10
2114
8-10 6116 2
2048 . 11 A0 A10
D0 .D7 CS =0 .
WE OE .
( )21 -10 . 150.
9-10 6264 8
8 . 13 8
. CS2 CS .
WE OE . 28
1 .NC 120 . ( )22 -10
.
188 .
..
1 NC Vcc 28 1 A7 Vcc 24
2 A12 27 2 A6 A8 23
3 A7 CS2 26 3 A5 A9 22
4 A6 A8 25 4 A4 21
6116
5 A5 A9 24 5 A3 20
6 A4 A11 23 6 A2 A10 19
7 A3 22 7 A1 18
8 A2 A10 21 8 A0 D7 17
6264 D6 16
9 A1 20 9 D0
10 A0 D7 19 10 D1 D5 15
11 D0 D6 18 11 D2 D4 14
12 D1 D5 17 12 GND D3 13
13 D2 D4 16 ( )21 -10
14 GND D3 15 6116
( )22 -10
6264
10-10 62256 32
32 . 15 8
. . CS WE
. OE 28 6264 1
A14 26 A13 CS2 . 120.
( )23 -10 .
189 .
..
1 A7 Vcc 24 1 A14 Vcc 28
2 A6 A8 23 2 A12 27
3 A5 A9 22 3 A7 A13 26
4 A4 Vpp 21 4 A6 A8 25
2716
5 A3 20 5 A5 A9 24
6 A2 A10 19 6 A4 A11 23
7 A1 18 7 A3 22
8 A0 D7 17 8 A2 A10 21
D6 16
62256
9 D0 9 A1 20
10 D1 D5 15 10 A0 D7 19
11 D2 D4 14 11 D0 D6 18
12 GND D3 13 12 D1 D5 17
( )24 -10 13 D2 D4 16
2716 14 GND D3 15
( )23 -10
62256
11-10 2716 2 EPROM

2 .
6116 11 A0 A9
D0 .D7 CS 18 . OE 20
21 25 . 5
.
190 .
..

1 A7 Vcc 24
2 A6 A8 23 FF .
125 . ( )24 -10
3 A5 A9 22
.
4 A4 A11 21 15.
2732
5 A3 20
A2
.
6 A10 19
18
7 A1
12-10 2732
4 EPROM
8 A0 D7 17
D6 16
9 D0 ( )25 -10 .
10 D1 D5 15 2716
11 D2 D4 14
. 2732
2716
12 GND D3 13
.A11
( )25 -10 20
2732 Vpp OE
(5
) .
13-10 2764 8 EPROM 27256

32 EPROM
( 26 -10 )27 -10 .
.2716 PGM 2764 ()
( 5) .
191 .
..
1 Vpp Vcc 28 1 Vpp Vcc 28
2 A12 27 2 A12 A14 27
3 A7 NC 26 3 A7 A13 26
4 A6 A8 25 4 A6 A8 25
5 A5 A9 24 5 A5 A9 24
6 A4 A11 23 6 A4 A11 23
7 A3 22 7 A3 22
8 A2 A10 21 8 A2 A10 21
2764 62256 CS
9 A1 20 9 A1 20
10 A0 D7 19 10 A0 D7 19
11 D0 D6 18 11 D0 D6 18
12 D1 D5 17 12 D1 D5 17
13 D2 D4 16 13 D2 D4 16
14 GND D3 15 14 GND D3 15
( )26 -10 ( )27 -10

2764 62256
14-10
RAM ROM . -1
. -2
CE CS . -3
15 8 . -4
( )7 -10 8 256 4256. -5
2114 1 8. -6
6116 2 16. -7
192 .
..
-8 6116 2716
.
193 .
11
Timing Circuits
..
1-11

. timer

. :

R

C +
Vc
Vin _

( )1 -11

Vc
Vfinal

.
Vc=e-t/

Vinitial .
t

( )2 -11
.
.
2-11
R C ( )1 -11
Vinitial Vfinal :
)Vc = Vinitial + (Vfinal - Vinitial) (1-e-t/ )(1-11
:
=RC )(2-11
t=0 ( )1 -11 Vc=Vinitial ,
t= Vc=Vfinal
. ( )2 -11
195.
..
.
(.)1 -11
3-11 Comparator
V2 R Q
+ Vo
RS
V1 _ S

Vo ( )4 -11 RS
+Vcc
V2-V1

-Vcc .

( )3 -11 (3 -11 ) .

.
V2 V1
Vcc (3 -11) . V1>V2
Vcc .
V2>V1 5 ( ) V1>V2
. uA741
.uA311

4 -11 Flip Flop
Qn Qn+1 R S
0 0 d 0 R-S
0 1 0 1 truth table (-11
1 0 1 0
1 1 0 d .)4
1-11 S R
RS
S R
. . Q=0
196.
..
S = 0 R = 0 S = 0 .R = 1
1-11 S = 0 R = d d do not care
( ) Q = 1
S= 0 R = 0 S=1 R=0
1-11 S=d . R=0
( .)5 -11
.

( )5 -11 LED

. .

5 .

. R=47K
V .
.
.

.

.
. ( )6 -11 .
S .Vcc P
.
.Vcc N P
197.
..
Vcc -Vcc P .
N P

. ( )6 -11 .
.
( )6 -11
5-11 NE555
NE555
.
Monostable
Astable
. ( )7 -11
. Q
TR
Trigger CV
Control Voltage DIS
Discharge
THR
( )7 -11 NE555 Threshold R
Reset
. 8 .1
198.
..
6-11
Monostable Operation
Q . Trigger
2 Vcc R C
. ( )8 -11 NE555
R C .
. 1 8 8 (-11
.)7 14.
Vcc
8
4
R
R1
5 -
6 1 R Q T3
+
C
R
R2 7 RS
2 3
-
2 S
+
S
R
T1 T2
1 G
( )8 -11 NE555
R Vcc
.
2
1 ( )8 -11 ( ) Vcc 2
3
1
( ) .Vcc 1 C
3
2 2 .trigger
( )8 -11 2 Vcc ( R2
) Vcc S
199.
..
.
2
. Vcc
18 5.
1 R 2 S .

. R S
. Q T3
Emitter . Q T1
T2 . T1 T2 T3
collector

open circuit .

(
)2
Vcc 2
S

S .
Q Q .
T3 T2 T1

2
0 C
Vc T1 .
0

t 1
0
T
t
( )

( )9 -11
R=0 Q
NE555

.2
200.
..
2 S
( .)8 -11
2
. S Q Q=1. Q =0
T1 T2 C
R RC .Vcc T3
Vcc .
T1 C
.Vcc 1
.
1 Vcc

.R=1 S=0

Q=0 Q =1
T3
. T2 T1

C

2 .
Vc
0 t
Vcc
T1 T2 2
0 t Vcc
3
( )10 -11 .
NE555
C R
:
) Vc Vcc (1 e t / RC )(3-11
201.
..
2
t=T T ( )9 -11 Vc Vcc
3
. ( )3 -11 :
2
) Vcc Vcc (1 e T / RC )(4-11
3
T :
)T=RCln(3 )(5-11
:
T=1.1RC )(6-11
R C T . ( )9 -11
.
R 100 C 100 1000
10 1000
.
7-11 Astable Operation

2 6 2
. Rb 6 7 .
( )10 -11 .
Ra Rb C Rb
C
. .
Ra Rb Vcc
2
1 Vcc
3
. Q =1 T1 T2
C Rb 7
1
.T1 Vcc
3
2 S=1
Q=1
2
Ra Rb Vcc
3
. T1 .T2
202.
..
1
T1 Vcc Vcc
3
2
Vcc . :
3
1 1
) Vc Vcc (Vcc Vcc )(1 e t /( Ra Rb ) C )(7-11
3 3
2
t=T1 Vc= Vcc
3
T1 :
T1=(Ra+Rb)Clin2
T1=0.693(Ra+Rb)C )(8-11
T2
2
Rb Vcc
3

:
2
Vc Vcce t / RbC )(9-11
3
1
t=T2 Vc= Vcc
3
T2 :
( )11-11
555 T2=RbClin2
T2=0.693RbC )(10-11
( )8 -11 ()10 -11
:
T=T1+T2
=0.693(Ra+2Rb)C )(11-11
:
1 1.44
F )(12-11
T ( Ra 2 Rb )C

. NE555
.
555 Ra+Rb
Rb
. Ra=0
203.
..
. ( )11-11
( ) . Rb
Rb .T1=0.693RaC
Rb .T2=0.693RbC
Ra=Rb .
NE555 one shot timers
.unprogrammable R C
.
.
.

.

. Timer/Counter
.
8-11 Timer Counters

.

.NE555

( )12 -11 XR2240 .

.
204.
..
.
XR2240 .
9-11 XR2240 Timer Counter

( )12 -11
Vcc :
1 4.7K -1 555

XR2240 13
Vcc 16

13 .9
.
14
( )13 -11 ( .)12 -11
XR2240
12 1 .555

11
14 frequency modulated
.
1
-2
2
8 8
3 ( .)12 -11
( )14 -11 .

)f0( 2 ( ) )12 -11 4
256 .f0/128
-3
Reset .10
.trigger 11
.
205.
..
Vcc

4.7K .open collector
1
XR2240
2

3 4.7
.Vcc (-11
)13 f0 1
.
( )15 -11
XR2240
11
14
1
2
( )16 -11
1 2 3 XR2240
1
.
( .)14 -11 13
11
( )14 -11
. 8
.

Vcc ( .)15 -11 Wired
206.
..
.OR gate
. ( )16 -11
f0 f0/2 f0/4 7 .
7=4+2+1 7
( .)16 -11 1 2 3 4
15 . 1
5 ( .)17 -11
256 .
11
14
( )17 -11 1 3
XR2240

.
10 ( ) Reset .
. ( )18 -11
255 11
. S
XR 556 10-11
.555
( )19 -11 556

Vcc 5 18 .
207.
..

. 150 .
10K
( )18 -11
S
( )19 -11 XR556
208.
..
11-11 XR 558/559
Reset

( )20 -11
.

555 .

Discharge
555 .556
( )20 -11 XR
558/559
Trigger
(-11
.)22
558
open
.collector

Vcc
4.7 .
( )21 -11
558 559 Vcc

. 100 . 559 558
open emitter
.558 559 4.7
. 100 .
.Vcc 5 18 . ( )21 -11
558 559 . Trigger
209.
..
.
( )23 -11
.
Reset 13 .
4 Control voltage
Pulse width modulation .
(.)21 -11
( )22 -11 558

( )23 -11
558
.

210.
..
12-11 ZN1034
XR2240 . (-11
)24 .
14 13 13 . 12
4095 4096 .122 Trigger
1 .
4096 Q 3 Vcc
Q 2 . 2 3 .
25 .
( )24 -11 ZN1034
:
T=K4095RC
R 14 13 C 13 . K
. ( )
12 ( .)25 -11
11 12 short circuit K .0.668
R C . 1-11
Rcal 100
211.
..
300 .
12 1 ( ) 2.7 (
ZN1034 ) .
Rcal
5 .
14
3 1
R
10 ( .)26 -11
13
C 7 1 .
( )25 -11
ZN1034
11 C R =Rcal =Rcal
100K 300K
12 0.01uF 39K 1sec 2.9sec
3 0.1uF 220K 1min 2.7min
14 1uF 100K 5min 12.5min
10K 1uF 1.2M 1Hr 2.5Hrs
R 10uF 3.3M 1day 2.7days
100uF 2.2M 1week 2.7weeks
13 1
C 2-11
ZN1034

K
( )26 -11
ZN1034

13-11
-1 (:)5 -11
47.
( .)V
.C
R C .
212.
..
-2 555 .
-3 .
-4 (.)12 -11
-5 R C 555
10 : 5 12 .
-6 R C 555
100 : 500 1000 5 .
1 .3
-7 8 ( )
( 2 6) 10 .
.
-8 5 .2240
-9 6 .2240
-10 7 .2240
-11 8 6
6 8
.
-12 3 .
( ).
-13 2240 :
731
851
6321
.
213.
-1
12
..
1 -12

. tristate logic
.
2-12
. ( )1 -12
1 5 1 2 2
3 . ( )1 -12 .
( )1 -12

5

3 2 1 .

.
( )1 -12

( ) .
1 2 .
5 5 Short circuit

1 2 3

( )2 -12

.5

.
215.
..
. ( )2 -12
.
( )

.
()
high impedance .

.
. ( )
.
. ( )3 -12
. (3 -12)
. (3 -12)

. (-12
( )3 -12 3) .
(3 -12) .

.
1
Vcc 14
.
2 13
3 12 3-12 74125
4 11
5 10 ( )4 -12 4
.
6 9

7 GND 8 .
74125 .
( )4 -12 74125
4
216.
..
4-12 74126
( )5 -12 4 .
.
.
1 Vcc 14
1 Vcc 20 2 13
2 19 3 12
3 18 11
4
4 17
5 10
5 16 9
6
6 15
7 GND 8
7 14
74126
8 13 ( )5 -12 74126
4
9 12
10 GND 11
74240
( )6 -12 74240
8
5-12 74240
8 ( .)6 -12
. 4

1 19 .
217.
..
6-12 74241
8
( .)7 -12
1 Vcc 20 74240
2 19
.
4
3 18

4 17 1
.19
5 16
6 15
7 14 7-12 74242 74243

8 13
74242 74243 .
9 12
( )1
10 GND 11 A B
74242 B A
74241
( )7 -12 74241 74243 B .A
8 ( )13
B A
74242 A B 74243 A
.B ( )8 -12 (.)9 -12
8-12 74244
8 ( .)10 -12
. 4

1 19 .
218.
..
1 Vcc 14 1 Vcc 14
NC 2 13 NC 2 13
1A 3 12 NC 1A 3 12 NC
2A 4 11 1B 2A 4 11 1B
3A 5 10 2B 3A 5 10 2B
4A 6 9 3B 4A 6 9 3B
7 GND 8 4B 7 GND 8 4B
74242 74243
( )8 -12 74242 ( ) 9-12 74243
4 4

9-12 74245
( )11 -12 .
) CE ( 19 ( )1
. 19 1 A
.B 19 1 B .A
19 1 Send/ Re ceive
. .
219.
..
S/
1 Vcc 20
1 20 Vcc
2 19
1A 2 19
3 18
2A 3 18 1B
4 17
3A 4 17 2B
5 16
4A 5 16 3B
5A 6 6 15
15 4B
7 14
6A 7 14 5B
8 13
7A 8 13 6B
8A 9 12 7B 9 12
10 11 8B 10 GND 11
GND
74245 74244
( ) 10-12
( ) 11-12 8 74245
8 74244

220.
Dictionary
..

A .
Access time Binary Coded Decimal, BCD
.

. .
Adder Bipolar
. Bipolar transistor .

. .
Address Bistable
.
. .
Bit
.
Amplitude .
. Boolean algebra
.
Analog
.
Borrow

. .
AND gate Bounce
AND "" .
.
.
Astable .
Buffer
.
.
Asynchronous .
.
. Bus

.
. .

B .
Bidirectional Byte
. .
. C

Capacitor
. capacitance
Binary .
Binary signal
() ().
222.
..
Carry .
.
. Decoder
.
.
Clear n
2n
. .
Clock Decrement
. .
Demultiplexer
.
Code
.
Combinational logic circuit .
Digital
.
.
. Digit
.
Driver
. .
Commutative law .
Dynamic RAM, DRAM
. x+y=y+x . .
Comparator
4
.
.
Complement
ones complement E
. twos
complement Edge triggered flip flop

. (
Counter ) ( ).
. EEPROM
.
D EPROM
Data
.
D flip flop .
D Enable
D . .
Decade
Decade counter .
. .
Decimal Encoder
223.
..
Hexadecimal
. . 16
.F
Hold time
.

Exclusive NOR .

. I
Exclusive OR Increment
.
. Integrated Circuit, IC
.
F .
Frequency Inverter
. . .
. .
Feedback J
JK flip flop
.
Flip flop .
. .
. Johnson counter
JK D
T .
.
.
Full Adder, FA
K
3 Karnaugh map
.
.
G
Gate L
Large Scale Integration, LSI
.
.
. 1000 10000
Glitch .
Latch

. . flip flop .
Least significant bit, LSB
H ()
Half adder .
2 Logic
. .

.
224.
..
Look ahead
look ahead carry adder
. Octal
.8
M One shot
.
Master slave flip flop .
master Open collector
.slave
. .
Medium Scale Integration, MSI .
OR gate
OR "" .
100 1000
. .
Monostable Oscillator
.
.
.
. Output
Most significant bit, MSB .
Overflow
.
Multiplexer, MUX

.
Multivibrator .

. P
Parallel
N
NAND gate .
NAND Potentiometer

. .
Nibble Power dissipation
4 . .
Nonvolatile
.
Preset
.ROM
NOR gate .
NOR Priority encoder

.
NOT gate .
NOT .
.
O
225.
..
Product Of Sums, POS Resistance

.
AND Resistance network
OR . .
Propagation .
Propagation delay R-S flip flop
R S
.
Pulse
.

. S
Pull up resistor Sequential circuit

() . .
.
. .
.
R .
Random Access Memory, RAM Serial

.
. Set
.
Read .reset
. Set up time
Register

.
Reset .
. Shift register
. .
Ring counter .
. Sign

.
. Sign bit
Ripple .
Ripple carry adder .
Ripple counter .
. Small Scale Integration, SSI
Rise time

%10 %90 . 100.
Reliable Speed Power product
reliability
.
Remainder .
. S-R flip flop
226.
..
R S
.
Tristate logic
.
Stage

. .
Truth table

Static Memory, SRAM .
TTL, Transistor Transistor Logic
.
Strobe .
5
.
.
Subtractor U
Ultra large scale Integration, ULSI
.
Sum Of Products, SOP
.
OR Universal gate
AND . .
Synchronous
. NAND
. . .NOR
Universal shift register

T
Terminal Count, TC
() . .
9 . Up/down counter
Timer
. .
Timing diagram
V
Very Large Scale Integration, VLSI

.
T flip flop 100000
T .
. Volatile
.
Toggle .
.RAM
.
Trailing edge X
. XOR gate
Trigger
227.
..

.
XNOR gate
.
W
Word
16 2 .
.
Write
.
228.

الدوائر المنطقية - د. محمد العدوي

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الدوائر المنطقية - د. محمد العدوي

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..

128 2 4 Transparent 74116

73 : Decoders And Encoders

101 : Arithmetic circuits

104 4-6 Full adder

115 : Latches and flip flops

129 21-7 74173 D

135 : Digital Counters

153 19-8 74LS393 4

159 : Shift Registers

214 : Tristate logic gates

Integrated Circuits, ICs 4 -1

-4 Very Large Scale Integration, VLSI

( )32 -1 Power supply

2-2 Decimal system

3-2 Binary system

1-5-2 : Sign magnitude

2-6-2 Over flow error

7-2 Octal system

= ( 0.56 )10 0.56 0.48 0.84

0100 0101 0000 450

( )22 -3 ( )23 -3 6 7405

7406, 7416 7407, 7417

10-3 AND gate chips

( )26 -3 ( )27 -3 7409

7420, 7440 7412

( )34 -3 7401 7439 4

7420 7440 . ( )37 -3 7412

1 Vcc 16 ( )38 -3 7430

13-3 NOR gate chips

7402, 7428 7433

( )45 -3 7486 4 ( )46 -3 74266

( )45 -3 7486 ( )46 -3 4 74266

Boolean Algebra And Logic Simplification

1-2-4 Logic Variable

3-2-4 Logic addition

4-2-4 Logic multiplication

3-3-4 Distributive Law

1-8-4 Sum of product form

2-8 -4 Product of sum form

f) ( A B C D ) ABC D ) g) ( ABC )( EFG ) ( HIJ )( KLM

Decoders And Encoders

2-5 74LS42 7442

4-5 7446 7447 7448 7449

4-5 7446 7447

RBI RBI RBI RBI

RBI RBI RBI RBI

5-5 74LS137 8/3

6-5 74LS138 8/3

7-5 74LS139 4/2

)BCD to Decimal Decoder/Driver (Open Collector

9-5 74154 74LS154 16/4 16/1

10-5 2 74155 4/2 4/1

11-5 74156 74LS156

15-5 Multiplexers/Data selector

Y S 0S1D0 S 0S1D1 S 0S1D2 S 0S1D3

AND S0 .S1 D0=0 D1=D2=D3=1 :

Y S 0S1 S 0S1 S 0S1

16-5 74150 1/16

17-5 74151 1/8

19-5 74157 74158 1/2

( )30 -5 74157 74158

74157 ( )30 -5 4 1/2

Y ABCD0 ABCD1 ABCD2 ABCD3 ABCD4 ABCD5 ABCD6 ABCD 7