-----------------------------------------------------

--
-- Design Name : ram_sp_sr_sw
-- File Name : ram_sp_sr_sw.vhd
-- Function : Synchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_sp_ar_sw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock
Input
address :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address Input
data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data
bi-directional
cs :in std_logic; -- Chip
Select
we :in std_logic; -- Write
Enable/Read Enable
oe :in std_logic -- Output
Enable

);
end entity;
architecture rtl of ram_sp_ar_sw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;

signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1

downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin

----------------Code Starts Here------------------

-- Tri-State Buffer control
-- output : When we = 0, oe = 1, cs = 1
data <= data_out when (cs = '1' and oe = '1' and we = '0') else
(others=>'Z');

-- Memory Write Block

-- Write Operation : When we = 1, cs = 1
MEM_WRITE:
process (clk) begin
if (rising_edge(clk)) then
if (cs = '1' and we = '1') then
 mem(conv_integer(address)) <= data;
end if;
end if;
end process;

-- Memory Read Block

-- Read Operation : When we = 0, oe = 1, cs = 1
MEM_READ:
process (clk) begin
if (rising_edge(clk)) then
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end if;
end process;

end architecture;

-----------------------------------------------------
--
-- Design Name : ram_sp_ar_sw
-- File Name : ram_sp_ar_sw.vhd
-- Function : Asynchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_sp_ar_sw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock
Input
address :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address Input
data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data
bi-directional
cs :in std_logic; -- Chip
Select
we :in std_logic; -- Write
Enable/Read Enable
oe :in std_logic -- Output
Enable

);
end entity;
architecture rtl of ram_sp_ar_sw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
 signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1

downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin
----------------Code Starts Here------------------
-- Tri-State Buffer control
-- output : When we = 0, oe = 1, cs = 1
data <= data_out when (cs = '1' and oe = '1' and we = '0') else
(others=>'Z');

-- Memory Write Block

-- Write Operation : When we = 1, cs = 1
MEM_WRITE:
process (clk) begin
if (rising_edge(clk)) then
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end if;
end process;

-- Memory Read Block

-- Read Operation : When we = 0, oe = 1, cs = 1
MEM_READ:
process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end process;

end architecture;

-----------------------------------------------------
--
-- Design Name : ram_sp_ar_aw
-- File Name : ram_sp_ar_aw.vhd
-- Function : Asynchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_sp_ar_aw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
address :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address Input
 data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data
bi-directional
cs :in std_logic; -- Chip
Select
we :in std_logic; -- Write
Enable/Read Enable
oe :in std_logic -- Output
Enable
);
end entity;
architecture rtl of ram_sp_ar_aw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;

signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1

downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin

----------------Code Starts Here------------------

-- Tri-State Buffer control
data <= data_out when (cs = '1' and oe = '1' and we = '0') else
(others=>'Z');

-- Memory Write Block

MEM_WRITE:
process (address, data, cs, we) begin
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end process;

-- Memory Read Block

MEM_READ:
process (address, cs, we, oe, mem) begin
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end process;

end architecture;

-----------------------------------------------------
--
-- Design Name : ram_dp_sr_sw
-- File Name : ram_dp_sr_sw.vhd
-- Function : Synchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_dp_sr_sw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
clk :in std_logic; --
Clock Input
address_0 :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address_0 Input
data_0 :inout std_logic_vector (DATA_WIDTH-1 downto 0); --
data_0 bi-directional
cs_0 :in std_logic; -- Chip
Select
we_0 :in std_logic; --
Write Enable/Read Enable
oe_0 :in std_logic; --
Output Enable
address_1 :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address_1 Input
data_1 :inout std_logic_vector (DATA_WIDTH-1 downto 0); --
data_1 bi-directional
cs_1 :in std_logic; -- Chip
Select
we_1 :in std_logic; --
Write Enable/Read Enable
oe_1 :in std_logic --
Output Enable
);
end entity;
architecture rtl of ram_dp_sr_sw is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;

signal data_0_out :std_logic_vector (DATA_WIDTH-1 downto 0);

signal data_1_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1

downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);

begin
----------------Code Starts Here------------------
-- Memory Write Block
-- Write Operation : When we_0 = 1, cs_0 = 1
MEM_WRITE:
process (clk) begin
if (rising_edge(clk)) then
if ( cs_0 = '1' and we_0 = '1') then
mem(conv_integer(address_0)) <= data_0;
elsif (cs_1 = '1' and we_1 = '1') then
mem(conv_integer(address_1)) <= data_1;
end if;
end if;
end process;

-- Tri-State Buffer control

data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0')
else (others=>'Z');
 -- Memory Read Block
MEM_READ_0:
process (clk) begin
if (rising_edge(clk)) then
if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then
data_0_out <= mem(conv_integer(address_0));
else
data_0_out <= (others=>'0');
end if;
end if;
end process;

--Second Port of RAM

-- Tri-State Buffer control
-- output : When we_0 = 0, oe_0 = 1, cs_0 = 1
data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0')
else (others=>'Z');

-- Memory Read Block 1

MEM_READ_1:
process (clk) begin
if (rising_edge(clk)) then
if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then
data_1_out <= mem(conv_integer(address_1));
else
data_1_out <= (others=>'0');
end if;
end if;
end process;

end architecture;

-----------------------------------------------------
--
-- Design Name : ram_dp_ar_aw
-- File Name : ram_dp_ar_aw.vhd
-- Function : Asynchronous read write RAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_dp_ar_aw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
address_0 :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address_0 Input
data_0 :inout std_logic_vector (DATA_WIDTH-1 downto 0); --
data_0 bi-directional
cs_0 :in std_logic; -- Chip
Select
 we_0 :in std_logic; --
Write Enable/Read Enable
oe_0 :in std_logic; --
Output Enable
address_1 :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address_1 Input
data_1 :inout std_logic_vector (DATA_WIDTH-1 downto 0); --
data_1 bi-directional
cs_1 :in std_logic; -- Chip
Select
we_1 :in std_logic; --
Write Enable/Read Enable
oe_1 :in std_logic --
Output Enable
);
end entity;
architecture rtl of ram_dp_ar_aw is
----------------Internal variables----------------

constant RAM_DEPTH :integer := 2**ADDR_WIDTH;

signal data_0_out :std_logic_vector (DATA_WIDTH-1 downto 0);

signal data_1_out :std_logic_vector (DATA_WIDTH-1 downto 0);

type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1

downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin

----------------Code Starts Here------------------

-- Memory Write Block
-- Write Operation : When we_0 = 1, cs_0 = 1
MEM_WRITE:
process (address_0, cs_0, we_0, data_0, address_1, cs_1, we_1, data_1)
begin
if (cs_0 = '1' and we_0 = '1') then
mem(conv_integer(address_0)) <= data_0;
elsif (cs_1 = '1' and we_1 = '1') then
mem(conv_integer(address_1)) <= data_1;
end if;
end process;

-- Tri-State Buffer control

data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0')
else (others=>'Z');

-- Memory Read Block

MEM_READ_0:
process (address_0, cs_0, we_0, oe_0, mem) begin
if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then
data_0_out <= mem(conv_integer(address_0));
else
data_0_out <= (others=>'0');
end if;
end process;

-- Second Port of RAM

-- Tri-State Buffer control
data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0')
else (others=>'Z');
 -- Memory Read Block 1
MEM_READ_1:
process (address_1, cs_1, we_1, oe_1, mem) begin
if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then
data_1_out <= mem(conv_integer(address_1));
else
data_1_out <= (others=>'0');
end if;
end process;

end architecture;
-----------------------------------------------------
--
-- Design Name : cam
-- File Name : cam.vhd
-- Function : CAM
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity cam is
generic (
ADDR_WIDTH :integer := 8
);
port (
clk :in std_logic; -- Cam clock
cam_enable :in std_logic; -- Cam enable
cam_data_in :in std_logic_vector (2**ADDR_WIDTH-1 downto 0); --
Cam data to match
cam_hit_out :out std_logic; -- Cam match has happened
cam_addr_out:out std_logic_vector (ADDR_WIDTH-1 downto 0) -- Cam
output address
);
end entity;
architecture rtl of cam is
----------------Internal variables----------------
constant DEPTH :integer := 2**ADDR_WIDTH;

signal cam_addr_combo :std_logic_vector (ADDR_WIDTH-1 downto 0);

signal cam_hit_combo :std_logic;
signal found_match :std_logic;
begin
---------------Code Starts Here-------
process (cam_data_in, cam_hit_combo, cam_addr_combo, found_match) begin
cam_addr_combo <= (others=>'0');
found_match <= '0';
cam_hit_combo <= '0';
for i in 0 to DEPTH-1 loop
if (cam_data_in(i) = '1' and found_match = '0') then
found_match <= '1';
cam_hit_combo <= '1';
 cam_addr_combo <= conv_std_logic_vector(i,
cam_addr_combo'length);
else
found_match <= found_match;
cam_hit_combo <= cam_hit_combo;
cam_addr_combo <= cam_addr_combo;
end if;
end loop;
end process;

-- register the outputs

process (clk) begin
if (rising_edge(clk)) then
if (cam_enable = '1') then
cam_hit_out <= cam_hit_combo;
cam_addr_out <= cam_addr_combo;
else
cam_hit_out <= '0';
cam_addr_out <= (others=>'0');
end if;
end if;
end process;

end architecture;

-----------------------------------------------------
--
-- Design Name : syn_fifo
-- File Name : syn_fifo.vhd
-- Function : Synchronous (single clock) FIFO
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity syn_fifo is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
clk :in std_logic; -- Clock input
rst :in std_logic; -- Active high reset
wr_cs :in std_logic; -- Write chip select
rd_cs :in std_logic; -- Read chipe select
data_in :in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data
input
rd_en :in std_logic; -- Read enable
wr_en :in std_logic; -- Write Enable
data_out :out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data
Output
empty :out std_logic; -- FIFO empty
full :out std_logic -- FIFO full
 );
end entity;
architecture rtl of syn_fifo is
-------------Internal variables-------------------
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;

signal wr_pointer :std_logic_vector (ADDR_WIDTH-1 downto 0);

signal rd_pointer :std_logic_vector (ADDR_WIDTH-1 downto 0);
signal status_cnt :std_logic_vector (ADDR_WIDTH downto 0);
signal data_ram_in :std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_ram_out :std_logic_vector (DATA_WIDTH-1 downto 0);

component ram_dp_ar_aw is
generic (
DATA_WIDTH :integer := 8;
ADDR_WIDTH :integer := 8
);
port (
address_0 :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address_0 Input
data_0 :inout std_logic_vector (DATA_WIDTH-1 downto 0); --
data_0 bi-directional
cs_0 :in std_logic; -- Chip
Select
we_0 :in std_logic; --
Write Enable/Read Enable
oe_0 :in std_logic; --
Output Enable
address_1 :in std_logic_vector (ADDR_WIDTH-1 downto 0); --
address_1 Input
data_1 :inout std_logic_vector (DATA_WIDTH-1 downto 0); --
data_1 bi-directional
cs_1 :in std_logic; -- Chip
Select
we_1 :in std_logic; --
Write Enable/Read Enable
oe_1 :in std_logic --
Output Enable
);
end component;

begin
-------------Code Start---------------------------
full <= '1' when (status_cnt = (RAM_DEPTH-1)) else '0';
empty <= '1' when (status_cnt = 0) else '0';

WRITE_POINTER:
process (clk, rst) begin
if (rst = '1') then
wr_pointer <= (others=>'0');
elsif (rising_edge(clk)) then
if (wr_cs = '1' and wr_en = '1') then
wr_pointer <= wr_pointer + 1;
end if;
end if;
end process;

READ_POINTER:
process (clk, rst) begin
if (rst = '1') then
rd_pointer <= (others=>'0');
 elsif (rising_edge(clk)) then
if (rd_cs = '1' and rd_en = '1') then
rd_pointer <= rd_pointer + 1;
end if;
end if;
end process;

READ_DATA:
process (clk, rst) begin
if (rst = '1') then
data_out <= (others=>'0');
elsif (rising_edge(clk)) then
if (rd_cs = '1' and rd_en = '1') then
data_out <= data_ram_out;
end if;
end if;
end process;

STATUS_COUNTER:
process (clk, rst) begin
if (rst = '1') then
status_cnt <= (others=>'0');
-- Read but no write.
elsif (rising_edge(clk)) then
if ((rd_cs = '1' and rd_en = '1') and not(wr_cs = '1' and wr_en
= '1') and (status_cnt /= 0)) then
status_cnt <= status_cnt - 1;
-- Write but no read.
elsif ((wr_cs = '1' and wr_en = '1') and not (rd_cs = '1' and
rd_en = '1') and (status_cnt /= RAM_DEPTH)) then
status_cnt <= status_cnt + 1;
end if;
end if;
end process;

data_ram_in <= data_in;

DP_RAM : ram_dp_ar_aw
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH
)
port map (
address_0 => wr_pointer, -- address_0 input
data_0 => data_ram_in, -- data_0 bi-directional
cs_0 => wr_cs, -- chip select
we_0 => wr_en, -- write enable
oe_0 => '0', -- output enable
address_1 => rd_pointer, -- address_q input
data_1 => data_ram_out, -- data_1 bi-directional
cs_1 => rd_cs, -- chip select
we_1 => '0', -- Read enable
oe_1 => rd_en -- output enable
);

end architecture;
-----------------------------------------------------
--
-- Design Name : rom_using_file
-- File Name : rom_using_file.vhd
-- Function : ROM using readmemh
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity rom_using_file is
port (
ce :in std_logic; -- Chip Enable
read_en :in std_logic; -- Read Enable
address :in std_logic_vector (7 downto 0); -- Address input
data :out std_logic_vector (7 downto 0) -- Data output
);
end entity;
architecture behavior of rom_using_file is

-- RAM block 8x256

type RAM is array (integer range <>)of std_logic_vector (7 downto 0);
signal mem : RAM (0 to 255);

-- Subprogram to read a text file into RAM --

procedure Load_ROM (signal data_word :inout RAM) is
-- Open File in Read Mode
file romfile :text open read_mode is "memory.list";
variable lbuf :line;
variable i :integer := 0;
variable fdata :std_logic_vector (7 downto 0);
begin
while not endfile(romfile) loop
-- read digital data from input file
readline(romfile, lbuf);
read(lbuf, fdata);
data_word(i) <= fdata;
i := i+1;
end loop;
end procedure;

begin

-- Procedural Call --
Load_ROM(mem);

data <= mem(conv_integer(address)) when (read_en = '1' and ce = '1')

else (others=>'0');

end architecture;
-----------------------------------------------------
--
-- Design Name : rom_using_case
-- File Name : rom_using_case.vhd
-- Function : ROM using case
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rom_using_case is
port (
ce :in std_logic; -- Chip Enable
read_en :in std_logic; -- Read Enable
address :in std_logic_vector (3 downto 0); -- Address input
data :out std_logic_vector (7 downto 0) -- Data output
);
end entity;
architecture behavior of rom_using_case is

begin

process (read_en, address) begin

if (read_en = '1') then
case (address) is
when x"0" => data <= conv_std_logic_vector(10,8);
when x"1" => data <= conv_std_logic_vector(55,8);
when x"2" => data <= conv_std_logic_vector(244,8);
when x"3" => data <= (others=>'0');
when x"4" => data <= conv_std_logic_vector(1,8);
when x"5" => data <= x"ff";
when x"6" => data <= x"11";
when x"7" => data <= x"01";
when x"8" => data <= x"10";
when x"9" => data <= x"00";
when x"A" => data <= x"10";
when x"B" => data <= x"15";
when x"C" => data <= x"60";
when x"D" => data <= x"90";
when x"E" => data <= x"70";
when x"F" => data <= x"90";
when others => data <= x"00";
end case;
end if;
end process;

end architecture;
-----------------------------------------------------
--
-- Design Name : rom_using_constant
-- File Name : rom_using_constant.vhd
-- Function : ROM using constant
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-----------------------------------------------------
--
library ieee;
 use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rom_using_constant is
port (
read_en :in std_logic; -- Read Enable
address :in std_logic_vector (3 downto 0); -- Address input
data :out std_logic_vector (7 downto 0) -- Data output
);
end entity;
architecture behavior of rom_using_constant is
subtype ROM_Word is std_logic_vector (7 downto 0);
subtype ROM_Addr is integer range 0 to 15;

type ROM is array (ROM_Addr) of ROM_Word;

constant ROM_Table :ROM := (

conv_std_logic_vector(10,8),
conv_std_logic_vector(55,8),
conv_std_logic_vector(244,8),
"00000000",
conv_std_logic_vector(1,8),
x"ff",
x"11",
x"01",
x"10",
x"00",
x"10",
x"15",
x"60",
x"70",
x"90",
x"00");

begin

process (read_en, address) begin

if (read_en = '1') then
data <= ROM_Table(conv_integer(address));
end if;
end process;

end architecture;