Highly Linear Mixer for On-Chip RF

Test in 130nm CMOS

Master thesis performed at division of Electronic Devices
by

Ghulam Mehdi
Thesis No: LiTH-ISY-EX--06/3913--SE

Linkping Date: 2007-01-01

ii
Highly Linear Mixer for On-Chip RF Test

Master thesis in Electronic Devices

at

Linkping Institute of Technology

by

Ghulam Mehdi
LiTH-ISY-EX--06/3913--SE

Supervisor: Dr. Jerzy Dabrowski

Examiner: Dr. Jerzy Dabrowski

Linkping 2007-01-01

iii
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Presentation date: Division of Electronic Devices
2006-12-15 Department of Electrical Engg.
Publication date:

Language Type of Publication ISBN (Licentiate thesis)

English Licentiate thesis ISRN:
Swedish Degree thesis LiTH-ISY-EX--06/3913--SE
Number of pages Thesis C-level
82 Thesis D-level Title of series (Master thesis)
Report
Other (specify below) Series number/ISSN ()

URL, Electronic Version

http://www.ep.liu.se

Publication Title
Highly Linear Mixer for On-Chip RF Test in 130 nm CMOS
Author
Ghulam Mehdi

Abstract
The complexity of wireless communication integrated circuits is increasing day by day
due to the trend of multifunction and multistandard support. This has not only increased
the production cost of these RFICs but the testing cost is also increased significantly, as
much advanced test equipments and instruments are needed to carry out the
sophisticated performance tests. To avoid this higher cost and to reduce the test time,
the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test
technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain
through a test attenuator (TA) during the test mode. A highly linear offset mixer is
needed to implement this on-chip loopback test for these transceivers. The aim of this
thesis work is to design a highly linear upconversion offset mixer for loopback test in
CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards.
Few highly linear mixer architectures were simulated in 0.35um AMS process using
Cadence SpectreRF software. When compared with active mixers, passive mixer
consumes no dc power and there is significant reduction in silicon area overhead. The
thesis presents a highly linear passive mixer with very low conversion loss and noise
figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off
frequency and improved conversion loss. Pre and Post layout simulation results of the
designed mixer are presented.

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Abbreviations

BalUn Balanced Unbalanced

1 db CP Input Referred one dB Compression Point
dB Decibels
dBm Power level in dB (decibels) with respect to 1 mW
DfT Design for Test
DRC Design Check Rules
EDGE Enhanced Data Rate
EDGE Enhanced Data Rate for GSM Evolution
ETSI European Telecommunication Standards Institute
FDD Frequency Division Duplex
FM Frequency Modulation
FSK Frequency Shift Keying
GC Power / Voltage Conversion Gain
GMSK Gaussian Minimum Shift Keying
GSM Global System for Mobile communications
IF Intermediate Frequency
IIP3 Input Referred 3rd Order Intercept Point
IM Intermodulation Products
IMD Inter Modulation Distortion
IQ Inphase Quadrature
LFSR Linear Feedback Shift Register
LO Local Oscillator
MOS Metal Oxide Semiconductor
PA Power Amplifier
PAC Periodic
PNoise Periodic Noise
PSK Phase Shift Keying
PSP Periodic

PSS Periodic Steady State

QPAC Quasi Periodic
QPSS Quasi Periodic Steady State

vii
RF Radio Frequency
RFIC Radio Frequency Integrated Circuit
Rx Receiver
SDF Spectral Density Function
SSB NF Single Side Band Noise Figure
TA Test Attenuator
TDD Time Division Duplex
TPG Test Pattern Generator
Tx Transmitter
UMTS Universal Mobile Telecommunications System
WCDMA Wideband Code Division Multiple Access

viii
 Abstract

The complexity of wireless communication integrated circuits is increasing day

by day due to the trend of multifunction and multistandard support. This has not
only increased the production cost of these RFICs but the testing cost is also
increased significantly, as much advanced test equipments and instruments are
needed to carry out the sophisticated performance tests. To avoid this higher
cost and to reduce the test time, the alternative is to perform on-chip test. .In RF
transceivers, loopback is an on-chip test technique in which Tx signal, instead of
radiating through antenna is fed to the Rx chain through a test attenuator (TA)
during the test mode. A highly linear offset mixer is needed to implement this
on-chip loopback test for these transceivers. The aim of this thesis work is to
design a highly linear upconversion offset mixer for loopback test in CMOS
technology. This mixer is designed for Bluetooth and GSM/EDGE standards.
Few highly linear mixer architectures were simulated in 0.35um AMS process
using Cadence SpectreRF software. When compared with active mixers, passive
mixer consumes no dc power and there is significant reduction in silicon area
overhead. The thesis presents a highly linear passive mixer with very low
conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS
process for higher cut off frequency and improved conversion loss. Pre and Post
layout simulation results of the designed mixer are presented.

ix
x
 Preface

This master thesis work describes the design of a highly linear CMOS
upconversion mixer aimed for loopback test in RF transceivers. The aim is to
design a highly linear mixer with good noise figure and conversion gain for the
desired application. The scope of the thesis work is to understand basic loopback
BiST concepts followed by a through study on mixers with emphasis on
linearity. The work includes studying and implementing different linear mixer
architectures and then selecting the most appropriate architecture which meets
the required specifications for loopback test configuration. Transistor level and
post layout simulations are done to verify the performance of the designed
mixer. The simulation tool is Cadence RF Spectre and AMS 0.35 um and AMS
0.13 um processes are used for transistor and layout level simulations.

Chapter-1 starts with an introduction and motivation to this thesis work.

Different wireless standards are described in this chapter. It also explains BiST,
DfT and Loopback Test in RFICs meant for wireless standards like GSM,
EDGE and GPRS etc.
Chapter-2 describes the basic mixer theory and working principle. Different
types of mixers are discussed in this section along with their applications. This
section also covers the specifications of a typical mixer like conversion gain,
noise figure, linearity, port to port isolation, power consumption and area.
Chapter-3 includes the circuits and simulation results of four linear mixer
architectures implemented in Cadence at transistor level. The specifications of
these architectures are compared to select an appropriate architecture for the
aimed mixer.
Chapter-4 In this chapter, a mixer with high linearity is proposed for loopback
test. Mixer design from schematic to layout level is discussed. Pre and post
layout results are presented in this section.
Chapter-5 concludes this thesis work and indicates some future work
directions.
At the end, all the references of the literature reviewed during the entire thesis
work are given.

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 Acknowledgments
I am thankful to my supervisor Prof. Jerzy Dabrowski for providing me the
opportunity to perform this thesis work and for his guidance. I am greatly
thankful to Rashad Ramzan, PhD student at Electronic Devices division, ISY
dept, for his guidance and encouragement during this thesis work.
I would like to acknowledge and thank to Dr.Jahangir K.Kayani, CESAT,
Pakistan for his support, encouragement and technical guidance.
I am also thankful to the people at Electronic Devices department, Linkping
University for helping me in technical and administrative issues.
At the end, I am thankful to my parents and my family for their support,
patience and encouragement during my MS studies at Linkping.

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 Table of Contents
Preface ................................................................................................................ xi
Table of Contents................................................................................................ xv
1. Introduction....................................................................................................... 1
1.1. Introduction................................................................................................ 3
1.2. Wireless Standards..................................................................................... 3
1.2.1. GSM.................................................................................................... 4
1.2.2. UMTS ................................................................................................. 5
1.2.3. Bluetooth............................................................................................. 5
1.2.4. Zigbee ................................................................................................. 6
1.3. BiST Technique ......................................................................................... 7
1.4. Loopback Test ........................................................................................... 7
1.4.1. TDD with Modulation at Baseband .................................................... 8
1.4.2. TDD with Directly Modulated VCO .................................................. 9
1.4.3. FDD with/without Modulated VCO ................................................. 10
1.5. Offset Mixer Placement in Loopback...................................................... 11
1.5.1. Placement before Test Attenuator (TA) ..................................... 11
1.5.2. Placement after Test Attenuator (TA) ........................................ 13
1.6. Required Mixer Specifications ................................................................ 14
2. Mixer Theory, Types & Specifications .......................................................... 15
2.1. Introduction.............................................................................................. 17
2.2. Ideal Multiplier ........................................................................................ 17
2.3. Mixer Types............................................................................................. 18
2.3.1. Up & Down Conversion Mixers....................................................... 18
2.3.2. Unbalanced & Balanced Mixers ....................................................... 19
2.3.3. Passive & Active Mixers .................................................................. 22
2.4. Mixer Performance Parameters ............................................................... 25
2.4.1. Conversion Gain ............................................................................... 25
2.4.2. Noise Figure...................................................................................... 27
2.4.3. Port-Port Isolation............................................................................. 31
2.4.4. Linearity............................................................................................ 31
3. Highly Linear Mixer Architectures ................................................................ 35
3.1. Introduction.............................................................................................. 37
3. 2. Nonlinearities in CMOS Mixers............................................................. 37
3.2.1. Nonlinearities in CMOS Active Mixers ........................................... 38
3.2.2. Nonlinearities in CMOS Passive Mixers.......................................... 39
3.3. Highly Linear Active Mixer .................................................................... 39
3.3.1. Resistive Source Degenerated Gilbert Mixer ................................... 40
3.3.2. Class AB Transconductor Mixer ...................................................... 42
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 3.3.3. CMOS Transconductor Mixer .......................................................... 48
3.4. Highly Linear Passive Mixer ................................................................... 54
3.4.1. Resistive Ring Mixer .................................................................. 54
3.5. Summary.................................................................................................. 59
3.6. Offset Mixer Placement Prospective ....................................................... 60
3.6.1. Passive Offset Mixer......................................................................... 61
3.6.2. Active Offset Mixer.......................................................................... 61
3.7. Conclusion ............................................................................................... 62
4. Proposed Mixer for Loopback Test ................................................................ 63
4.1. Passive Ring Mixer in 0.13 m CMOS........................................................ 65
4.1.1. Design & Circuit Description ............................................................... 65
4.1.2. Simulation Results ................................................................................ 67
4.2. Layout Design.............................................................................................. 68
4.3. Pre & Post Layout Results Comparison ...................................................... 69
5. Conclusions and Future Work ........................................................................ 73
5.1. Conclusion: .................................................................................................. 75
5.2. Future Directions ......................................................................................... 76
References........................................................................................................... 77

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 List of Figures
Figure 1: Recent trend in wireless standards ........................................................ 4
Figure 2: Typical BiST setup................................................................................ 7
Figure 3: Loopback test setup............................................................................... 8
Figure 4: Loopback setup for TDD with modulation at BB................................. 8
Figure 5: Loopback setup for TDD with direct modulated VCO......................... 9
Figure 6: Alternate loopback setup for TDD with direct modulated VCO .......... 9
Figure 7: Carrier frequency offset in FDD transceivers ..................................... 10
Figure 8: Loopback test setup in FDD transceivers............................................ 10
Figure 9: Offset mixer before TA, LO connected to PA out .............................. 12
Figure 10: Offset mixer before TA, LO connected to SG .................................. 12
Figure 11: LO connected to PA out through TA (not suitable setup) ................ 13
Figure 12: RF connected to PA out through TA................................................. 13
Figure 13: Ideal Mixer ........................................................................................ 17
Figure 14: Mixer output frequency spectrum ..................................................... 17
Figure 15: Upconversion mixer .......................................................................... 18
Figure 16: Upconversion mixer in RF Tx........................................................... 19
Figure 17: Single transistor unbalanced mixer ................................................... 20
Figure 18: Dual gate unbalanced mixer.............................................................. 20
Figure 19: Single balanced mixer ....................................................................... 21
Figure 20: Double balanced Gilbert mixer ......................................................... 22
Figure 21: Single balanced passive mixer .......................................................... 23
Figure 22: Double balanced passive mixer......................................................... 24
Figure 23: Balanced transmission gate switch.................................................... 24
Figure 24: MOS noise model for RF .................................................................. 28
Figure 25: Input 1dB Compression Point of a mixer.......................................... 32
Figure 26: Intermodulation products .................................................................. 33
Figure 27: IIP3 of a mixer .................................................................................. 34
Figure 28: Source degenerated Gilbert mixer..................................................... 41
Figure 29: Class AB transconductor mixer ........................................................ 44
Figure 30: S21, S22, and S33 & NF of class AB transconductor mixer ............ 45
Figure 31: S11 response...................................................................................... 45
Figure 32: Conversion gain and NF with LO sweep .......................................... 46
Figure 33: 1 dB compression point class AB Transconductor mixer................. 46
Figure 34: IIP3 class AB Transconductor mixer ................................................ 47
Figure 35: Replacing (a) single transistor by (b) CMOS pair ............................ 48
Figure 36: MOS Transconductor (a) with tail current (b) without tail current... 49
Figure 37: CMOS transconductor mixer ............................................................ 50
Figure 38: Conversion gain and NF vs. LO........................................................ 51
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Figure 39: S21, S22, S33 & NF.......................................................................... 52
Figure 40: 1 dB compression point at 5 dBm LO............................................... 52
Figure 41: IIP3 at 5 dBm LO.............................................................................. 53
Figure 42: Equivalent circuit of MOS transistor ................................................ 55
Figure 43: Approximate small signal model ...................................................... 55
Figure 44: Variation in g ds (1, 2,3) with change in Vds ............................................ 55
Figure 45: Resistive quad passive mixer ............................................................ 56
Figure 46: Conversion loss & NF with LO power sweep .................................. 56
Figure 47: S11 response of passive mixer .......................................................... 57
Figure 48: S parameters & NF response for 100 MHz output bandwidth.......... 57
Figure 49: 1dB compression point at 5 dBm LO................................................ 58
Figure 50:IIP3 at 5 dBm LO............................................................................... 58
Figure 51: 1dB CP and IIP3 with LO sweep ...................................................... 59
Figure 52: Schematic diagram 0.13um CMOS passive mixer ........................... 67
Figure 53: Complete layout of mixer.................................................................. 68
Figure 54: Pre & post layout result comparison ................................................. 69
Figure 55: Post layout 1 dB CP at 5 dBm LO .................................................... 70
Figure 56: Post layout IIP3 at 5 dBm LO ........................................................... 70
Figure 57: IIP3 for 60 MHz LO and 2.4 GHz RF in .......................................... 71

xviii
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1. Introduction

1
2
1.1. Introduction
The complexity of wireless communication integrated circuits is increasing day
by day due to the trend of multifunction and multistandard support. A hot
research is in progress to develop low cost multistandard chip solutions. This
has not only increased the production cost of these RFICs but the testing cost is
also increased significantly, as much advanced test equipments and instruments
are needed to carry out the sophisticated performance tests. To avoid this higher
cost and to reduce the test time, the alternative is to perform on-chip
performance testing also referred to BiST. In BiST, on-chip testing is carried out
to measure the performance parameters of RF front end and to detect possible
defects by enabling the test mode in the transceiver. Some extra circuitry has to
be put on the chip to implement BiST. This may increase the power
consumption and silicon area overhead of the chip but the testing cost is reduced
drastically [1, 2].
The emergence of various wireless communication standards has also increased
the complexity to incorporate on-chip BiST. Todays complex RF transceiver
architectures provide better sensitivity, selectivity, dynamic range and adjacent
channel blocking. In RFICs, one of the most common implementation of BiST
is Loopback Test in which Tx signal, instead of radiating through antenna is
fed to the Rx chain through a test attenuator (TA) during the test mode.
Different configurations of loopback test are described in section 1.2. An offset
mixer is required to implement this on-chip loopback test.
The objective of this thesis work is to explore and design a highly linear
upconversion mixer in CMOS technology. This mixer is designed primarily for
GSM/EDGE standards but can be used for loopback test in other transceivers as
well.

1.2. Wireless Standards

The field of wireless communication and networks has attained tremendous
growth in recent years. The idea of having multi functions like phone, video,
digital camera, web browser and email etc in a single terminal has led to
different wireless standards. Wireless communication systems, such as cellular,
cordless and satellite phones as well as wireless local area networks (WLANs)

3
have become an essential tool to many people in every-day life. As the
technology is advancing, these standards are becoming more and more stringent
emphasising on enhanced data rates, circuit miniaturization, and multi function
and multi standard support [3]. These standards are meant for both short and
long range wireless communication. Zigbee, UWB, DECT and Bluetooth are
standards for short-range communication. Fig.1 shows the recent trend in
wireless standards.

Figure 1: Recent trend in wireless standards

Following is a brief description of these wireless standards.

1.2.1. GSM
GSM standard for mobile telephony was developed by ETSI and was operating
in 900 MHz band. EDGE-GSM is enhanced data rate GSM standard.

Mobile Frequency Rx: 1805-1880, Tx: 1710-1785

Range (MHz) Rx: 1930-1990, Tx: 1850-1910
Multiple Access Method TDMA/FDM
Duplex Method FDD
Number of Channels 124
Users Per Channel 8
Channel Spacing 200 KHz
Modulation GMSK,8-PSK (EDGE only)
Channel Bit Rate 270 833 kb/s

Table 1: GSM specifications

4
In EDGE, the transmission rate is three times for the same bandwidth as used in
original GMSK modulation (standard GSM). EDGE is based on a modified 8
PSK scheme. Polar modulation is implied at the Tx. The input signal to the PA
is phase modulated with constant amplitude whereas amplitude modulation is
added at the output by varying the gain of PA [4]. GSM standards are
summarized in Table.1.

1.2.2. UMTS
Universal Mobile Telecommunications System is European 3G version of global
wireless systems for voice and information services. This provides various data
rates using WCDMA. UTMS is a FDD based system, so a highly linear receiver
is required to reject the Tx leakage into the Rx section [3]. UTMS specifications
are given in Table.2.

Mobile Frequency Rx: 2110-2170, Tx: 1920-1980

Range (MHz)
Multiple Access WCDMA
Method
Duplex Method FDD
Users Per Channel 8
Channel Spacing 5 MHz
Modulation QPSK/OQPSK
Channel Bit Rate 384.833 kb/s outdoor
2 Mb/s indoor

Table 2: UTMS specifications

1.2.3. Bluetooth
Bluetooth is a wireless standard for short-range communication and commonly
used for connectivity between electronic devices. This has enabled to replace the
cables used for interconnections. Bluetooth can also be used to provide ad hoc
networks or data/voice access points. Bluetooth operates in ISM band. Since
Bluetooth is primarily intended for portable battery driven devices, minimum
power consumption is essential. The constant envelope modulation scheme
(BFSK) allows to use power efficient switching PA in Bluetooth TX [3].
Specifications of Bluetooth are given in Table.3.
5
 Mobile Frequency 2402-2480
Range (MHz) (North America & Europe)

Multiple Access Frequency hopping

Method
Duplex Method TDD
Number of Channels 79
Users Per Channel 7 active, 200 inactive
Channel Spacing 1MHz
Modulation BFSK
(0.5 Gaussian Filter)
Channel Bit Rate 721 kb/s raw data
56 kb/s return

Table 3: Bluetooth specifications

1.2.4. Zigbee
Zigbee is a wireless networking standard that is aimed at remote control and
sensor applications which is suitable for operation in harsh radio environments
and in isolated locations. It builds on IEEE standard 802.15.4.Zigbee a very
attractive standard for wireless networking.

Frequency 2402-2480,1000 mW/MHz

Range (MHz) (N. America)
2412-2472, 100 mW/MHz
(Europe)
Multiple Access TDMA
Method
Duplex Method FDD
Users Per Channel 255
Channel Spacing 4 MHz
Modulation GFSK
(0.5 Gaussian Filter)
Channel Bit Rate 250/28 kb/s

Table 4: Zigbee specifications

6
1.3. BiST Technique
Built-in self-test is a technique to perform on-chip performance test or to detect
possible defects on-chip. BiST implementation usually requires extra hardware
circuitry to be introduced on the chip. BiST can also be defined as a DFT
technique in which testing is accomplished through built-in hardware circuitry.
BiST is a cheap test solution since no expensive external ATE is required [5, 6].
As shown in Fig.2, TPG generates the test bits. This TPG can be implemented as
a LFSR. Specifically, in digital RF transceiver the carrier signal is modulated
with this BB signal. The BB processor then evaluates the received demodulated
signal from Rx chain of DUT.
Test Pattern
Generator

BiST Device Under Test

Controller

Test Response
Evaluation

Figure 2: Typical BiST setup

1.4. Loopback Test

Loopback is straightforward test architecture for transceivers. In loopback test,
the Tx test signal is fed to the Rx usually through a test attenuator (TA) to check
the functionality of both the Tx and the Rx. The available baseband (BB)
processor acts as both test pattern generator and spectrum analyzer respectively
[6].
Fig.3 shows a typical loopback test setup. The primary advantage of on-chip
loopback other then reduced testing cost and testing time, is that no sensitive
block in the transceiver is accessed externally for test purpose and hence not
affected. As described in Section.1.2, different wireless standards with different

7
Tx and Rx architectures are in use so a generic loopback test setup not always is
fully compatible with them [7].

Figure 3: Loopback test setup

Beneath, some possible loopback test configurations are described and

requirement of a highly linear offset mixer is motivated, which is the core of this
thesis work.

1.4.1. TDD with Modulation at Baseband

In RF transceivers where TTD duplexing technique is used and the Tx signal is

modulated at the BB (LO is not directly modulated), a simple loopback
configuration is applied as shown in Fig.4. The signal is fed to the RX chain
through a TA. Usually this TA is programmable so that both the sensitivity and
linearity of the RX can be tested [8].

Receiver

LNA LPF ADC

Base
Test Band
TA LO Processor
Transmitter

LPF DAC xtest

Amp

Figure 4: Loopback setup for TDD with modulation at BB

8
1.4.2. TDD with Directly Modulated VCO
Baseband signal directly modulates the VCO. There may be two loopback test
setup configurations.

(a) In TDD, LO is shared by both Tx and Rx. In this scenario, LO is directly

modulated by the BB signal. Both the LO of Rx and test signal are the same.
This will generate DC at the Rx output. An offset mixer must be introduced in
the test path as shown in the Fig.5 to strip off the modulation [7, 9]. Conversely,
if LO remains unmodulated, modulation is achieved in the offset mixer so the
test is feasible as well. One of the inputs of the offset mixer is the RF signal and
the other input is the BB test signal. The transmission line delay in the RF signal
path may degrade the loopback test performance.

R e c e i v e r (zero-IF)

LNA LPF ADC

Test Base
TA Control Band
xtest Processor

Amp LO LPF DAC

xtest
Transmitter

Figure 5: Loopback setup for TDD with direct modulated VCO

Receiver

LPF ADC
LNA
fRx Base
TA Test
Band
Xtest Processor

fTx
Amp LO LPF DAC xtest

Transmitter

Figure 6: Alternate loopback setup for TDD with direct modulated VCO
9
(b) The alternate approach may be to place the offset mixer between the LO and
the receiver mixer, instead of placing it in the main loopback path. This is
depicted in Fig.6. The directly modulated test signal is applied to the input of
LNA through TA. The same signal is mixed with the BB signal using an offset
mixer, to remove the modulation. Since offset mixer drives the Rx
downconversion mixer, this mixer should be highly linear with minimum noise
figure and large output swing.

1.4.3. FDD with/without Modulated VCO

In FDD, there is separate LO for Tx and Rx and transmitting and receiving

frequencies are also different, therefore loopback test without offset mixer can
not be performed in such transceivers [9].
For example, in GSM, the Tx band is from 1710 to1785 MHz and Rx band is
from 1805 to1850 MHz, as shown in Fig.7. The f may vary in range of few
tens of MHz.
Tx band Rx band

fTx fRx
f

Figure 7: Carrier frequency offset in FDD transceivers

Receiver

LNA LPF ADC

fRx
TA Test Base
Band
LO Processor

f fTx

Amp LPF DAC xtest

Transmitter
Figure 8: Loopback test setup in FDD transceivers
10
The conversion gain of offset mixer is relaxed in this configuration as it can be
compensated by the attenuation of programmable TA. The test setup for FDD
transceivers is depicted in Fig.8.

1.5. Offset Mixer Placement in Loopback

A mixer can either be passive or active. Placement of an offset mixer is critical
and determines the suitability of a mixer type and its specifications for loopback
test. There are following two options for the placement of offset mixer in the
main test loop.

1.5.1. Placement before Test Attenuator (TA)

Offset mixer can be placed between PA of Tx and TA. This mixer can be either
passive, or active with some conversion gain. For passive mixers, conversion
loss is approximately equal to NF. Since TA is also passive, placement of
passive offset mixer before or after TA has not effect on total noise figure
(NFtotal).
Consider an example where passive offset mixer with NF of 5 dB and
conversion loss of 5 dB is the first stage and TA with attenuation of 30 dB is
the second stage as depicted in Fig.9. Then NFtotal can be calculated using
following Friis formula:
NF2 1
NFtotal = NF1 +
G1
NFtotal = 35 dB
Total noise figure remains the same even if the passive mixer follows TA.
On the contrary when this offset mixer is active (with some conversion gain),
placement of mixer affects the overall noise figure. When TA follows the active
offset mixer, the mixer gain helps to reduce the total noise figure.
Consider an active mixer with NF of 10 dB and conversion gain of 5 dB. TA
follows the mixer with an attenuation of 30 dB. Then total noise figure is
NFtotal = 25.15 dB
By swapping their locations, the total noise figure of 40 dB is achieved. Hence,
we infer that an active offset mixer with typical NF and GC values should be
placed before TA.

11
Since the mixer is a three-port device, there are two more options regarding the
connectivity. Either LO or RF IN port can be connected to output of PA. Both
the options for active and passive mixer are considered.
Consider the case when LO is connected to PA output as depicted in Fig.9. RF
IN port is connected to on-chip test generator. The requirement for the signal
swing of this generator is relaxed in this case but a possible overdrive must be
avoided as well. Usually, PA output signal is large enough to drive the LO port
i.e. switching stage, both in case of active and passive mixer. However, a too
large LO swing used in active mixer leads to increased LO feedthrough and
spikes in the output signal.
LNA

TA

Xtest
(RF IN)
LO
Port PA

Figure 9: Offset mixer before TA, LO connected to PA out

Alternatively, PA output can be connected to RF IN port and then the on-chip

test generator drives LO port as shown in Fig.10. A large enough on-chip swing
is needed to drive the mixer LO port especially when a passive mixer is used.
Since there is no attenuator between PA and the offset mixer, high power from
PA output (typically 10 dBm) can saturate the transconductance stage of an
active mixer introducing nonlinear distortions.
LNA

TA

Xtest
(LO Port)
RF IN
PA

Figure 10: Offset mixer before TA, LO connected to SG

12
A passive offset mixer is more appropriate in this case provided that LO power
is typically 5 dB greater than the RF IN power. This ensures that MOS switch
operates in linear region and the 1dB compression point is not affected.

1.5.2. Placement after Test Attenuator (TA)

Placement of the passive mixer after or before TA doesnt affect NFtotal.
However, in case of an active offset mixer the overall noise figure may degrade
if it is directly connected to the LNA input.
LNA

Xtest
(RF IN)
LO
Port

TA

PA

Figure 11: LO connected to PA out through TA (not suitable setup)

Consider the setup when the LO port of the mixer is driven by PA through TA
and RF IN port is connected to on-chip test generator as depicted in Fig.11.
Since a large amplitude is needed for switching the LO port, this configuration is
neither suitable for active nor for passive mixers. A typical attenuation of TA
would reduce the LO amplitude too much to make the mixer switch. The
transceiver cant be tested in this setup.
LNA

Xtest
(LO)
RF IN

TA

PA

Figure 12: RF connected to PA out through TA

13
The last configuration is the one in which RF port is connected to PA output
through TA and LO port is connected to the test generator as depicted in Fig.12.
An active mixer driven by a relatively low LO power is suitable in this case. A
passive mixer can be used as well.

1.6. Required Mixer Specifications

The specifications of an offset mixer depend on the wireless standard, which it is
meant for, RF transceiver type (FDD or TDD) and loopback test configuration.
The aim of this work is to design an offset mixer to be used in the main
loopback test path.
Since this offset mixer is a part of an extra test circuitry to implement on-chip
loopback, the power and area constraints are very stringent. The portable
devices have certain amount of stored energy. Therefore, a BiST circuitry with
lowest power consumption is preferred. Area is another constraint as the cost
rises with increase in area. Conversion gain of the required mixer is not that
much critical as it can be compensated by the programmable TA. 10 dB, typical
mixer NF is targeted.
However, the main focus is on linearity of the mixer. A mixer with poor
linearity may obscure the test response and result in false rejects. The targeted
linearity specifications are given in Table.5.

RF input frequency 60 MHz

LO frequency 2.4 GHz
LO Power 5 dBm
GC 0 dB
NF < 10 dB
1 dB Compression Point 0 dBm
3rd Order Intercept Point 10 dBm
Power consumption & area Minimum

Table 5: Target mixer specifications

14
2. Mixer Theory, Types & Specifications

15
16
2.1. Introduction
An ideal mixer is a multiplier circuit and usually drawn with a multiplier symbol
as shown in Fig.13. An ideal mixer translates the modulation around one carrier
frequency to another carrier frequency. A linear time invariant (LTI) circuit
cannot perform frequency translation. Mixers can be realized with either time-
varying or non-linear circuits.
A mixer is a three-port device consisting of LO (local oscillator), RF IN (radio
frequency input) and IF OUT (intermediate frequency output) ports. LO port is
driven by a local oscillator, which is a fixed amplitude large signal.

Figure 13: Ideal Mixer

The mixer produces sum and difference frequencies along with other spurious
tones due to the even and odd harmonics as depicted in the Fig.14.

Figure 14: Mixer output frequency spectrum

2.2. Ideal Multiplier

The multiplier circuit multiplies the two input signals A and B, and generates
product terms. Multiplication in time domain is convolution in frequency
domain. The following mathematical expression shows the generation of sum
and difference frequency products.
A = A1Cos1t (2.1)
B = A2Cos 2 t (2.2)

17
Multiplying the two signals a and b
A.B = ( A1Cos1t )( A2Cos 2 t ) (2.3)

Using the trigonometric identity, we have

AA AA
A.B = 1 2 Cos (1 2 )t + 1 2 Cos (1 + 2 )t (2.4)
2 2

2.3. Mixer Types

Classification of mixers is quite diverse. Mixers can be classified based on
functionality, topology, power consumption and transconductance stage.

2.3.1. Up & Down Conversion Mixers

The mixer produces two useful frequency components at the output i.e. the sum
and difference frequencies ( RF LO ) and other unwanted spurious signals.
The main difference between down and up conversion mixer is the different
output signal frequency. In downconversion mixer, the output signal frequency
is low usually few MHz, whereas in upconversion mixers, the output signal
frequency is high usually in GHz.

(a) Upconversion Mixer

In upconversion mixer, one of the input other than LO is usually called IF input
as it is much lower than LO frequency. The output of the mixer is sum of IF and
LO frequencies i.e. RF = ( IF + LO ) and called as RF out. Fig.15 shows
symbol of an upconversion mixer.

Figure 15: Upconversion mixer

18
Upconversion mixers are used at the Tx side, either as modulator or frequency
upconverter or both. This depends on the Tx architecture. Fig.16 shows a two
stage Tx. The first stage works as upconverter generates ( 1 + 2 ). The mixers
in the second stage act as IQ modulator [10].

Figure 16: Upconversion mixer in RF Tx

(b) Downconversion Mixer

Downconversion mixer in the Rx chain translates incoming high frequency into
a lower frequency to be processed by the IF stage of the Rx. The input signal is
called RF, and IF is the output frequency which is frequency difference of RF
and LO frequencies i.e. IF = ( RF + LO ) .

2.3.2. Unbalanced & Balanced Mixers

(a) Unbalanced Mixer

Unbalanced mixers are the simplest kind of mixer with lowest noise figure. A
single transistor unbalanced mixer is shown in Fig.17. This kind of mixer is also
called as Square Law Mixer. Mixing is performed by using nonlinear square law
characteristic of MOS transistor.
Conversion gain of such a mixer is independent of bias current and can be
expressed by Eqn.2.5 [11, 12].
C oxW
Gc = .V LO (2.5)
2L

19
 VDD

R C L

IF out

Vlo Vrf

Vss

Figure 17: Single transistor unbalanced mixer

An alternative configuration of unbalanced mixer is depicted in Fig.18. Mixing

is performed by modulating the transconductance of the driver stage with the
large LO signal. The LO signal modulates the transconductance of the driver
stage by varying the drain-source voltage vds of transistor M1. Drain of M1 is
biased just at the edge between triode and saturation region to maximize the
transconductance variation due to large LO signal [12]

M1
Vlo

M2
Vrf

Figure 18: Dual gate unbalanced mixer

The unbalanced mixers have very poor port to port isolation due to their
structure. Port-to-Port isolation determines what fraction of the IF signal that
appears at the RF. Feed through between different ports are undesirable in mixer
design and can degrade the Tx or Rx performance.
In unbalanced designs, noise from the driver stage at the IF can mix with the dc
component of the LO signal, and thus increase the noise power at the IF output
port. This noise can be reduced by capacitive degeneration at the driver stage
where M1 is the driver stage [12].
20
(b) Single Balanced Mixer
This type of mixer consists of a single transconductance stage and a differential
switching pair as shown in Fig.19. The incoming RF voltage is converted into
current by the transconductance stage with some gain and then multiplication is
performed in the current domain. The tail current is multiplied by the large LO
signal. Thus the output is sum and difference frequency components. Since the
output is differential and taken from both branches, RF feedthrough is cancelled
out [11, 13].
The circuit has a lower noise figure than the double balanced mixer due to its
fewer noise contributor devices. Source is degenerated for linearity
improvement. The common source transconductance stage can be replaced with
a common gate transconductance stage for better linearity but this makes the
design noisier as the noise contribution from the switching pair is not attenuated
[12].
VDD

IF

M2 M3
LO+ LO-

RF M1
Vss
L

Figure 19: Single balanced mixer

(c) Double Balanced Mixer

The most commonly used type of mixer is a double balanced mixer also known
as Gilbert mixer and will be discussed in detail in chapter 3. This kind of mixer
is suitable for both upconversion and downconversion applications. The mixer
consists of a differential transconductance stage and a differential switching
stage. Due to the fully differential structure, both the LO-IF and RF-IF
feedthrough is cancelled and isolation is improved significantly. Off course,
feedthrough exists due to the mismatches in the differential structure. However,
RF-LO and LO-RF feedthrough exists in double balanced mixer. The
21
transconductance stage provides gain to compensate the attenuation due to
switching stage and also to reduce the noise contribution from the switching
transistors [12, 13].
A doubled balanced Gilbert mixer is shown in Fig.20. The transconductance or
driver stage consists of transistors M1 and M2 whereas M3, M4, M5 and M6 form
the differential switching quad. For perfect switching, the size of transistors M3
to M6 is much smaller than M1 and M2.
Resistive load is suitable for broadband operation but reduces the voltage
headroom. For large output swing and save the voltage headroom, the resistive
load can be replaced with a LC tank circuit tuned at the mixer output frequency.
On the other side, this will limit the broadband operation of the mixer. The tuned
LC load is suitable for upconversion mixers as the output frequency is high and
an on-chip inductor can be realized at this frequency. For downconversion
mixers with low IF, inductor of large value can not be realized on-chip.
VDD

C L C L

IF-
IF+

M3 M4 M5 M6
LO+ LO+
LO-

RF+ M1 M2
RF-

Iss

Vss

Figure 20: Double balanced Gilbert mixer

To improve the linearity of a double balanced mixer, there are different

techniques and most common is the source degeneration. Degeneration can be
implemented by using resistor, capacitor or inductor. The reactive source
degeneration has lower NF than that with resistive degeneration [11, 12].

2.3.3. Passive & Active Mixers

Mixers are also classified on the basis of dc power they consume.

22
(a) Passive Mixers
Passive mixers, also known as switching mixers, are simple in construction.
These mixers dont consume any dc power. These mixers have conversion loss
instead of conversion gain due to the absence of transconductance stage. The
mixer performs a multiplication between the RF signal and the LO signal ideally
represented by a square wave switching between +1 and -1 as expressed in
Eqn.2.6.
1 1
COS ( RF t ).COS ( LO t ) = COS ( RF t + LO t ) + COS ( RF t LO t ) (2.6)
2 2
The passive mixers require good switches with minimum on-resistance for
reduced conversion loss. Similarly the switch must have a maximum high
resistance when off, to provide good isolation. One of the disadvantage in such
mixers is the need of large LO drive signal to turn the MOS switches on/off.
MOS transistor are very good switches for such high frequency applications.
When the MOS transistor is on, it operates in triode region and when off it is in
cut off region. For precise switching, ideally, the transistor should be biased
such that the gate-source voltage (VGS) is equal to the threshold voltage (VT) of
the transistor i.e. (VGS=VT). Lower the on resistance (Ron) of the switch, lesser
will be the conversion loss. The drain-source of passive mixers transistors are
slightly bias with positive VDS to attain optimum conversion loss and optimized
IMD performance mixers are [11, 14].

Figure 21: Single balanced passive mixer

Fig.21 shows the working of a single balanced passive mixer. Both the
transistors in the mixer switch on alternatively during the positive and negative
LO cycles.
23
Double balanced topology is preferred over the single balanced as it provides
higher port-to-port isolation. Fig.22 shows a passive double balanced mixer.
In mixers, the major source of non-linearity is the transconductance stage. Since
there is no transconductance stage and MOS transistor is fairly linear in triode
region when switched on, MOS passive mixers exhibit excellent linearity.
LO+ LO-

C C

RF+

VA VB

IF+ IF-
C C

RF-

C C

LO- LO+

Figure 22: Double balanced passive mixer

For improved port-port isolation and rejection of even order nonlinearity,

balanced transmission gate may be used instead of a single NMOS transistor
[15, 16]. Transmission gate also called as balanced switch consists of a NMOS
and PMOS transistor in parallel. A balanced transmission gate is depicted in
Fig.23.

Figure 23: Balanced transmission gate switch

(b) Active Mixers

Active mixers consist of two stages, switching stage and the transconductance
stage, hence consume static dc power. Active mixers can be either single ended
or double ended. The most commonly used active mixer is the standard Gilbert
24
cell mixer discussed in section 2.3.2(b). Since the circuit is active, the
transconductance stage provides voltage gain, however, NF is increased. The
non linear characteristics of transconductance stage degrades the over all
linearity of active mixers. Different active mixer architectures for improved
linearity have been proposed, and will be discussed in chapter 3.

2.4. Mixer Performance Parameters

The most important performance measure parameter of RF Rx is sensitivity and
selectivity. Sensitivity depends on system noise figure and type of demodulation
scheme. Selectivity includes adjacent channel selectivity, image rejection and
out of band blocker rejection, and depends on the third-order intermodulation
performance of the Rx front end. The total noise figure NFtotal and total third-
order intercept point IIP3total of a Rx can be calculated by using Eqn.2.7 and
Eqn.2.8.
F 1 F3 1
NFtotal = F1 + 2 + + ......... (2.7)
G1 G 1 G2
1
1 G1
2 2
G1 G 2
2

IIP3total = + + + .... (2.8)
IIP31 IIP3 2 IIP33
It is obvious from the above two formulas that NF of first stage and IIP3 of
second stage is critical in determining the overall noise figure and third-order
intermodulation performance. In heterodyne Rxs, first sage is LNA followed by
downconversion mixer as second stage.
Following is a description of different performance parameters of a mixer.

2.4.1. Conversion Gain

Conversion gain can be defined as either power conversion gain or voltage

conversion gain and represented by GC. Usually it is power conversion gain
unless otherwise specified. When the mixers input impedance and output
impedance are both equal to the source impedance, the power conversion gain
and voltage conversion gain, in dB, are the same.
The voltage conversion gain is the ratio of the IFrms voltage to RFrms voltage.

25
 V IF ( rms )
GC = (2.9)
V RF ( rms )
The power conversion gain is the ratio of the output power at the load to the
available RF input power.
Pout ( IF )
GC = (2.10)
Pin ( RF )

(a) Active Mixer GC

In active mixers like Gilbert mixer, transconductance stage provides the
conversion gain. All transistors operate in saturation region. The conversion gain
expression for a Gilbert mixer with source degeneration resistor RS and with a
load impedance RL is given by Eqn.2.11.
2
GC (dB ) = 20 log G m R L (2.11)

where
1
Gm = (2.12)
1
RS +
gm
and gm is the transconductance of V-I stage saturated transistor.
g m = n C ox (VGS VT )
W
(2.13)
L
2I D
gm = (2.14)
VGS VT
Therefore, increasing the width (W) of the transistor while keeping length (L) at
minimum increases the gain. Higher overdrive voltage also increases the gain.

(b) Passive Mixer GC

To derive the expression for conversion gain of an ideal mixer, consider the
following input signals.
v LO (t ) = a cos LO t (2.15)
v RF (t ) = b cos RF t (2.16)

26
The product of fundamental frequency of LO and RF signal is then
4
v IF t = a cos LO t.b cos RF t (2.17)

= . a.b[cos( LO + RF )t + cos( LO RF )t ]
1 4
2
2
v IF t = ab cos IF t (2.18)

2
Therefore, the ideal conversion gain of a passive mixer is GC = , which is

equal to 3.9 dB. With approximations, the above equation can be modified to
include the on-resistance of the mixer switches, which appears in series with the
source resistance.
2 RS
GC (dB ) = 20 log (2.19)
R S + 2 R on
RS is the source resistance; Ron is the average on-resistance of a single switch
transistor and can be determined by
1 L
Ron = = (2.20)
g ds eff C oxWV LO
Where VLO is the LO drive voltage. Minimizing Ron by device sizing improves
the conversion loss but generates matching issues due to addition of larger
parasitic capacitance. The other options to reduce Ron is to either increase the
LO drive or to use a transistor with minimum gate length [17].

2.4.2. Noise Figure

Noise figure is defined as the signal to noise ratio at the input to signal to noise
ratio at the output.
S input
N input SNRinput
NF = = (2.21)
S output SNRoutput
N output
Mixer noise figure can be specified as either single sideband (SSB) or double
sideband (DSB).SSB noise figure is used for the mixers in which the input
signal is contained in one sideband and the other sideband is removed by an
27
image rejection filter. DSB noise figure is applied for the mixers where the input
signal is contained by both the sidebands. DSB NF is applicable to direct
conversion mixers [12].
NFSSB NFDSB + 3dB
In this thesis work NF is SSB, unless otherwise specified.

(a) MOS Transistor Noise at RF

The noise consideration at RF is different then at low frequencies. The basic

noise behaviour is modelled by two correlated noise sources. The dominant
noise sources for active MOSFET transistors are the flicker and thermal noise.
The flick noise can be modelled as a voltage source in series with the gate as
shown in Fig.24.
The SDF of voltage for this source has the following value
v 2 ng Kf
= (2.22)
f WLC ox f
Where W and L are width and length of transistor respectively, Cox is the gate
capacitance per unit, f is the frequency and Kf is a constant and depends on the
process. It is important to note that for P channel device; this constant has much
smaller value than the N channel device.
2
Vng
G rg D

DC

Cgs 2
ind
g mV
gs

Figure 24: MOS noise model for RF

For thermal noise, the MOSFET noise model consists of following two noise
sources. The drain current noise is
i 2 nd = 4 KTg do f (2.23)
and the gate current noise is
28
 i 2 ng = 4 KTg g f (2.24)
where
2 C gs 2
gg = (2.25)
5 g do
The gate noise is correlated with the drain noise with the following correlation
factor
ing i nd
c= (2.26)
2 2
ing i nd

(b) Noise Analysis in CMOS Active Mixers

The CMOS mixers suffer from two types of noises, the flicker noise and the
white noise. Flicker noise is more critical in zero and low IF Rx architectures.
Active mixer consists of an input transconductance stage, switching stage and
output load. All transistors in the circuit contribute noise. Detailed high
frequency noise analysis of CMOS active mixers is presented in [18, 19] in
which both flicker and white noise issues are discussed. A brief description of
both types of noise is given below.
Flicker (1/f) Noise:

To minimize the load noise, PMOS loads can be used instead of NMOS. The
alternative is to use polysilicon resistors as load resistor is free from 1/f noise.
For zero or low IF architectures, the transconductance stage transistors only
contribute white noise after frequency translation. The flicker noise in these
transistors is unconverted to LO and to its odd harmonics.
Switching stage in active mixers significantly contribute flicker noise. This
noise can be minimized with sharp LO transitions. It has been observed that
noise reduces with lower LO frequency or with higher device fT [19].

White Noise:

In single balanced mixers, switches contribute white noise when both the
switches are ON. The noise added by a switching transistor is given by
29
 I
i n,o = 4 KT
2
(2.27)
A
Where = Channel noise factor
A= LO signal amplitude
I= dc bias current
The white noise generated in the transconductance stage is indistinguishable
from the RF input noise. So mixer commutation is assumed including
conversion gain of 2/, yields following expression
4 KT 2
2

v n ,o = n
2
g m RL (2.28)
gm
The total white noise at the output of the mixer is
4 KT 2
2 2
RL I
v n,o = 8 KTRL + 8 KT + n
2
g m RL (2.29)
A gm
Simplifying the above equation yields
R I g R
v n,o = 8 KTR L 1 + L + m L
2
(2.30)
A 2
The total output noise for doubled balanced mixer is
R I g R
v n,o = 8 KTR L 1 + L + m L
2
(2.31)
A 2
It is obvious from Eqn.2.31 that the output noise is proportional to
transconductance of the transistor, load resistance and dc bias current.

(c) Noise Analysis in CMOS Passive Mixers

For an ideal passive mixer

NF = Gc
GC is the conversion loss of the mixer. This equation is modified to include the
on resistance of the mixer switches, which appears in series with the source
resistance.
2R
NFdB = Gc 1 + on (2.32)
R s

30
Ron is the average on-resistance of a single switch and the above equation show
that the noise added by the switching transistor can be minimized by reducing
the Ron.

2.4.3. Port-Port Isolation

When port impedance is not matched to that of source impedance, some of the
power delivered to the port is reflected back to the source. Impedance matching
at RF and IF ports is necessary to avoid signal reflections.
Port-port isolation of a mixer depends on the architecture and topology. Higher
the isolation between the mixer ports, the better it is. The isolation between LO
and RF ports of the mixer is important as this feedthrough results in LO leaking
through antenna [12].

2.4.4. Linearity

A weakly nonlinear system can be approximated by the following 3rd order

polynomial.
y (t ) = 1 x(t ) + 2 x 2 (t ) + 3 x 3 (t ) + .... (2.33)
Thus the output of such a nonlinear circuit for a sinusoidal input signal
x(t ) = A cos t is
y (t ) = 1 A cos t + 2 A 2 cos 2 t + 3 A 3 cos t (2.34)

2 A 2
3 A 3
A 2
A 3
y (t ) = + 1 A + 3 cos t + 2 cos 2t + 3 cos 3t (2.35)
2 4 2 4
In Eqn.2.35, cos t is the fundamental frequency and rest is higher order
harmonics. A differential structure suppresses the even order harmonics. Odd
order harmonics make the system nonlinear [20].
An important specification of a mixer is its linearity. Mixers perform frequency
translation and realized by either using non-linear or time varying circuit. Thus
mixers are inherently non-linear. It is desirable for a mixer to act very linearly
with respect to all nonlinearities except the one giving the desired frequency
conversion. Two major sources of distortion in the mixer are the device
nonlinearities and the nonlinearities coming from the switching devices.
Linearity of a mixer can be estimated with following two parameters.
31
(a) 1dB Compression Point

1 dB compression point (P1dB) is a way to measure the extent of nonlinearities in

a mixer. A strong input signal saturates a mixer and reduces its power gain.
Input P1dB is the input power level that causes the mixer to decrease from its
linear magnitude response by 1 dB, and is equal to

0.145 1
P1dB = 10 log (2.36)
3

20log Aout

1dB

A 1-dB 20log Ain

Figure 25: Input 1dB Compression Point of a mixer

Fig.25 shows the output response of a mixer as a function of input signal power.
The straight line shows the linear magnitude response of a mixer. Due to odd
order nonlinearities and limiting (current limiting and/or voltage headroom
limiting), the conversion gain of the mixer is reduced at high input power level
as shown by the solid line. The point where the large-signal gain is 1 dB below
the small-signal gain is P1dB.
32
If the input signal is larger than the P1dB, this causes amplitude modulation (AM)
to phase modulation (PM) conversion. No information is lost if the desired
signal is frequency modulated but for phase modulated signal, BER increases
[12].

(b) 3rd Order Intercept Point (IIP3)

The other parameter to measure the extent of nonlinearity in mixers is the 3rd
order intercept point known as IP3. IP3 is defined as,
It is the extrapolated point where the fundamental and 3rd order intermodulation
products (IM3) intersect each other. At this point IM3=0 dBc
At this point, the input power level is called input referred IP3 (IIP3) and output
power level is called output referred IP3 (OIP3) and is given by Eqn.2.37.

4 1
AIIP 3 = (2.37)
3 3

Figure 26: Intermodulation products

When two signals close in frequency, are applied to a nonlinear circuit,

intermodulation products are generated other than the harmonics of input
frequencies. For input frequencies 1 and 2 , the intermodulation products
are 1 2 , 21 2 and 2 2 1 . If the frequency difference between 1 and
2 is small, then the components 21 2 and 2 2 1 are the third order
intermodulation products. These IM products will appear in the close vicinity of
1 and 2 as depicted in Fig.26.
33
Thus, it is apparent that a stronger interferer with a frequency, which is close to
the actual signal frequency, will corrupt the signal due to 3rd order
intermodulation products because the fundamental increases in proportion to A,
whereas IM3 increases in proportion to A3[20].
IP3 is measured by a two tone test. This two tone test is more relevant to
evaluate mixer performance as in real life; both the wanted signal and interferer
may exist. The magnitude of intermodulation products grows at three times the
rate at which the fundamental component increases. The intersection point of
these two lines is defined as the third order intercept point. The horizontal
coordinate of this intersection point is called input IP3 (IIP3) and the vertical
coordinate is called the output IP3 (OIP3). Fig.27 shows IP3 of a mixer.
Pout(dBm)

OIP3

output 1dB First-order 3rd-order

Compression output Intercept
Point

IP IIP3 Pin (dBm)

1dB

Figure 27: IIP3 of a mixer

34
3. Highly Linear Mixer Architectures

35
36
3.1. Introduction
To design a highly linear mixer, it is essential to understand the sources of
nonlinearities in mixers. This is discussed in section 3.1. Different reported
mixer architectures with high linearity were investigated and simulated with
Cadence software using AMS 0.35um CMOS process. Only a few suitable
architectures along with the simulation results are presented in this chapter, as
describing the rest is beyond the scope of this work. The primary objective is to
achieve highest possible linearity with good NF and GC. The mixer is aimed for
loopback test and is an extra component on the chip for BiST. Mixer design is a
trade off among its specifications, power consumption and silicon area. The
mixers presented in this chapter are designed and optimized for low dc power
consumption and with controlled silicon area.

3. 2. Nonlinearities in CMOS Mixers

The two dominant nonlinear sources in CMOS is the transconductance and
output conductance. The Taylor series is used due to its simplicity for weakly
nonlinear circuits. The drain current of a MOS in the Taylor expansion can be
expressed as follows:
ids (vGS , v DS ) = I DS (VGS , V DS ) + g m v gs + g d v ds + g m 2 v gs2 + g md v gs v ds
(3.1)
+ g d 2 v ds2 + g m3 v gs3 + g md 2 v gs2 v ds + g md 2 v gs v ds2 + g d 3 v ds3
In the above expression, gm3 is referred to as the third-order transconductance
and gd3 its third-order output conductance. Assuming that the drain current is
shorted at the signal frequency then all the output conductance terms and cross
modulation terms are vanished and only the transconductance terms are left.
IIP3 is given by
4 gm
IP3 = (3.2)
3 g m3
However, the above model is not accurate, as it does not include output
transconductance nonlinearity. Another model, which includes the nonlinearity
added by output conductance, is presented in [21].
37
According to this model, the third-order intermodulation current caused by the
transconductance and output conductance nonlinearities is given by
3 Gload
i IM 3,trans = g m 3 A 3 (3.3)
4 g d + Gload
3 Gload
i IM 3,cond = g d 3 v ds3 (3.4)
4 g d + Gload
where A is the fundamental amplitude at the gate and vds is the fundamental
voltage at the drain and can be expressed by
gm A
v ds = (3.5)
Gload + g d
At higher frequencies, the transconductance nonlinearity becomes a dominant
source. The internal capacitances dont add nonlinearity; however gain and
output swing is reduced at higher frequencies. At lower frequencies, the output
transconductance is the major source of nonlinearity. With technology scaling,
the transconductance becomes more linear but the output conductance
nonlinearity is increased [21].
The nonlinearities in active and passive CMOS mixers are as following.

3.2.1. Nonlinearities in CMOS Active Mixers

In active mixers, both the transconductance stage and switching stage add
nonlinearities. The transconductance has poor linearity due to the nonlinear
characteristics of the MOS transistors. The transistors operate in saturation
region with quadratic V-I characteristics. The following model is not accurate
for short channel devices. If the channel length modulation is neglected then the
drain current is given by

ID = (VGS VT )2 (3.6)
2
Consider the input signal vgs is applied at the input. The total instantaneous gate
to source voltage will be
vGS = VGS + v gs (3.7)
and the total instantaneous drain current is
1 W
i D = k n' (VGS + v gs V T ) 2 (3.8)
2 L

38
 1 'W W 1 W 2
iD = k n (VGS V T ) 2 + k n' (VGS V T )v gs + k n' v gs (3.9)
2 L L 2 L
The first term on the right hand side is the dc bias current. The second term is
the current, which is proportional to the input signal vgs. The third term is the
unwanted nonlinear term and generates distortion. This nonlinear term must be
kept small to reduce distortion, so that
1 'W 2 W
k n v gs << k n' (VGS V T )v gs (3.10)
2 L L
This result in
v gs << 2(VGS VT ) (3.11)
The above condition must be satisfied to neglect the last term and we have
W
i d = k n' (VGS V T )v gs (3.12)
L
i W
g m = d = k n' (VGS V T ) (3.13)
v gs L

3.2.2. Nonlinearities in CMOS Passive Mixers

Due to the absence of transconductance stage, only the switching transistors and
other circuit components add nonlinearities. The discontinuity in switching
action at zero crossing due to the voltage drop in gate voltage threshold of MOS
switches generates intermodulation distortion. The finite rise and fall time of LO
signals may create discontinuities and imbalance. Another phenomenon that
adds nonlinearities in switching mixers is the modulation of Ron by higher input
signal levels [23].

3.3. Highly Linear Active Mixer

Active mixers consist of two stages. Transconductance stage performs voltage to
current conversion and provides gain. Switching stage performs current
commutation. Different techniques exist to improve the linearity of
transconductance stage of active mixers. The architectures based on these
techniques have their own merits and demerits in terms of power consumption,
area consumption, and conversion gain and noise figure. While designing a

39
mixer with high linearity, the trade off for GC and NF is an important design
consideration.

3.3.1. Resistive Source Degenerated Gilbert Mixer

Gilbert mixer provides good port-to-port isolation with some conversion gain.
To improve the linearity of a Gilbert mixer, source degeneration technique is
implied. A small amount of resistance or reactance is inserted between source
and the ground. The reactance may be inductive or capacitive. Since the aimed
mixer is upconversion with input frequency of few MHz, an inductor of few
hundred nH is required. This huge size inductor cant be realized on-chip.
Therefore, resistive source degeneration is adopted.
This small resistance RS introduces negative feedback. RS reduces gm and
increases its output resistance. Now, only a fraction vgs of the input signal vi
appears between gate-source terminals [24].

(a) Circuit Description

The implemented Gilbert mixer circuit is shown in the Fig.28. The driver stage
consists of M1 and M2, operating in saturation region. Transistors should be
biased such that they dont leave saturation region for large input signals. The
gain of this stage is proportional to gm, and
W
g m = k n' (VGS VT ) (3.14)
L
It is obvious from the above equation that higher overdrive voltage provides
higher gain. Increasing the width W, while keeping the length L at minimum
also turn gain enhancement.
M3, M4, M5 and M6 are the current commutating transistor switches. The LO
power must be sufficient enough to drive the switches. However, large LO
signal level generates spikes, reduces switching speed and increases LO
feedthrough. The transistors in the switching stage are biased such that
VGS VT 0 (3.15)
This bias voltage ensures that when one transistor is on, the other one is off
hence minimizes the noise added by switching transistors.
As the mixer is an upconverter and its output frequency is 2.46 GHz, to save the
voltage headroom and attain large output swing, parallel LC tuned load is used

40
instead of resistor. 1 Pf capacitor in parallel to 4.185 nH inductor forms the
tuned load. This inductance value can be realized on-chip.
The resonant frequency of the tank circuit is
1
o = (3.16)
LC
Inductor and capacitor are open circuit at the resonance frequency and gain is
equal to gmRL. RS is the source degeneration resistor for linearity improvement.
The resistor adds thermal noise and degrades NF.
VDD

C L C L

IF-
IF+

M3 M4 M5 M6
LO+ LO+
LO-

RF+ M1 M2
RF-

Rs Rs
Iss

Vss
Figure 28: Source degenerated Gilbert mixer

(b) Design Approach

A bias current of 5mA is chosen with VDD of 3.3 V for nominal power
consumption. Channel length modulation effect is neglected during the design.
The switching transistors are biased just above the VT. The width of the
transistor is calculated using Eqn.3.17.
L.I DSS
W= ' (3.17)
k n (VGS VT )
where k n' = 175 A / V 2 ; VT = 0.7 V
VGS = 0.8 V ; L = 0.35 m
The width comes out to be 175 um. This much size of transistor adds lot of
parasitic capacitance and degrades LO port matching. The optimum width found
to be 100 um. The width of each driver stage transistor depends on the required
41
conversion gain. The width of 300 um provides conversion gain of 7dB. Further,
increase in width of driver transistor increases GC, reduces NF but degrades the
linearity. One way to improve the linearity is to increase the bias current. In the
design, bias current is fixed at 5 mA to avoid higher power consumption. The
alternate is to increase the overdrive voltage (VGS-VT) of driver stage. This
voltage is adjusted such that the transistors remain in saturation region for large
input swing and dont enter in the triode region.

(c) Simulation Results

The results tabulated in the following table show that there is a trade off between
linearity and other parameters of the mixer. Linearity is improved at the cost of
reduced conversion gain and increased noise figure.

Parameters Without Source With Source Reference Work

degeneration degeneration [32]

RS = 25
Power Cons 16.5 16 10.5
(mW)
GC (dB) 7.2 1.5 6.5
NF (dB) 5.5 7.5 8.5
P1dB (dBm) -15.5 -7.85 -12
IIP3 (dBm) -5.65 1.8 -3
LO Power 0 0 -8
(dBm)

Table 6: Double balanced Gilbert mixer results comparison

3.3.2. Class AB Transconductor Mixer

The linearity of classical source coupled pair transconductor (the one used in
Gilbert mixer in 3.3.1) is poor due to the quadratic characteristics of MOS
transistors. The maximum valid linear input range is
I SS
vin (3.18)
k n'

42
A class AB transconductor is made up of diode connected and common gate
transistors as shown in figure. The aspect ratio of all the transistors is equal and
quiescent current IB flows through each branch. The differential output current is
i out = 2 k n' I B vin (3.19)
The input swing range is
I
vin 2 B' (3.20)
kn
1 W
where k n' = n C ox
2 L
Comparison of above two equations shows that the input swing of class AB
transconductor is 2 that of source coupled pair [25].

(a) Circuit Description

Class AB transconductor is acting as transconductance stage. Transistor M1, M2,

M3 and M4 are the switching transistors. The differential RF input signal is
injected into the transconductance stage through diode connected transistors M9
and M12. M10 and M11 act as current mirrors.M5-M8 provides improved isolation
between LO and RF ports. All the transistors in transconductance stage are in
saturation. The aspect ratio of transistors M5 to M12 is the same to keep the bias
current IB equal in all branches [26].
VG is adjusted such that it is two times of VH. For optimal switching, M1 to M4
should be biased in saturation region; this is just above the triode region. Since
the mixer is of upconversion type with output frequency of 2.46 GHz, LC tuned
load is used to save voltage headroom. The on-chip inductor realization at this
frequency is easy to achieve [25, 26]. Fig.29 shows the schematic diagram of the
mixer.

(b) Design Approach

To have a fair comparison with the architecture described in section 3.2.1, the dc
bias current ISS is set to 2.5 mA. The transistors M5-M12 are biased in saturation
region. The current through one branch is 625 uA. To calculate VG and VH, we
know that
43
VG = 2V H (3.21)

IB
VH = VTn + (3.22)
n
1 W
where n = n C ox
2 L
For W = 300 m , L = 0.35m , n C ox = 175A / V 2 , VG is 1.3 V and VH is 0.65
V. Further increase in the width reduces GC and degrades NF. The input
matching is also disturbed due to significant added parasitic capacitance at
larger widths. The switching stage transistors are biased just above the triode
region and a width of 100 um provides good GC, NF and LO port matching

VDD VDD VDD

IF+ IF-

M1 M2 M3 M4

LO+ LO+
LO-

M5 M6
M6 M7

M1
VG
VH C1 C2
RF+
RF-
M9 M10 M11

M1 M12

Figure 29: Class AB transconductor mixer

(c) Simulation Results

The mixer is simulated in Cadence spectre using AMS 0.35 um process.

Conversion loss, noise figure, S22 and S33 response is depicted in Fig.30.
S11 of the mixer is simulated for input frequency up to 100 MHz and the
response is depicted in Fig.31.

44
Conversion gain and noise figure is simulated by sweeping LO power from 5
dBm to 5 dBm and the response is depicted in Fig.32. Larger LO drive reduces
signal attenuation due to switching stage, hence GC and NF is improved.

10

0
S22
S33
dB

-10
S21
NF
-20

-30
2.4 2.425 2.45 2.475 2.5

Frequency (GHz)

Figure 30: S21, S22, and S33 & NF of class AB transconductor mixer

-14

-15
dB

-16 S11

-17

-18
0 20 40 60 80 100
Frequency (MHz)

Figure 31: S11 response

45
 10

6
NF

dB
4
S21
2

-2
-5 -3 -1 1 3 5
LO (dBm)

Figure 32: Conversion gain and NF with LO sweep

Fig.33 shows 1 dB compression point of the mixer. Compression point is

simulated at 5 dBm LO power.

20

0
Pout (dBm)

-20

-40

-60
-65 -50 -35 -20 -5 10
Pin (dBm)

Figure 33: 1 dB compression point class AB Transconductor mixer

46
IIP3 of the mixer is depicted in Fig.34. IIP3 is measured using two-tone test.
Two tones of 60 MHz and 70 MHz are applied to the mixer input. QPSS
analysis in conjunction with QPAC analysis is run to find the third order
intercept point.

0
Pout (dBm)

-50

-100

-150

-200
-60 -45 -30 -15 0 15
Pin (dBm)

Figure 34: IIP3 class AB Transconductor mixer

Parameters Class AB Reference

Transconductor Work [26]
Process 0.35 m 0.13 m
Power Cons (mW) 8.25 5.6
GC (dB) 2.12 3.3
NF (dB) 9.5 14.87
P1dB (dBm) -0.5 -8.98
IIP3 (dBm) 8.5 5.46
LO Power (dBm) 5 -7

Table 7: Class AB Transconductor mixer specifications

Table.7 summarizes the simulation results of class AB transconductor mixer.

47
3.3.3. CMOS Transconductor Mixer
Another highly linear mixer architecture for wireless transceivers is the CMOS
transconductor mixer. A single transistor in the transconductance stage is
replaced by a combination of a PMOS and NMOS, called a CMOS pair as
shown in the Fig.35.

Mn
VG

VG

VS Mn
VS

Figure 35: Replacing (a) single transistor by (b) CMOS pair

From simple quadratic MOS model, for each transistor in the pair
1
V GS = VTH + 2I (3.23)

For the CMOS pair, an equivalent gate-source voltage can be expressed as
1 1
VGSeq = VTHn + VTHp + + 2I (3.24)

n p

The above expression can be written as

1
VGSeq = VTHeq + 2I (3.25)
eq
where
VTHeq = VTHn + VTHp (3.26)
n p
eq =
( ) 2
(3.27)
n + p
and the current through the pair is
eq
I= (V G VS VTHeq )
2
(3.28)
2
48
Thus, a pair of CMOS transistors acts as a single transistor and exhibits
excellent linearity [27]. In active mixers, the source coupled differential pair
contributes nonlinearities during V-I conversion due to the square law behavior
of MOS transistor. The transconductance stage becomes fairly linear over a wide
range of input voltage if the tail current source is eliminated. This is depicted in
the Fig.36.
ID1 ID2 ID1 ID2

M1 M2 M1 M2

Vin -Vin Vin -Vin

Iss

Vss Vss

Figure 36: MOS Transconductor (a) with tail current (b) without tail current

The differential output current for transconductor with tail current is

2I
I 1 I 2 = vi SS + vi2 (3.29)

where vi = vinP vinN
The differential output current for transconductor without tail current, is
I 1 I 2 = 2 vi (V SS VTn ) (3.30)
Instead of applying the RF input signal to the low impedance source terminal of
commutating transistors, PMOS transistor is used as source follower to
minimize the loading effect. The combination of NMOS in commutating stage
and PMOS in the source follower stage forms the CMOS pair. To keep the
PMOS transistors on, CMOS pair is biased such that a minimum bias offset of
VTHeq must exist between LO and RF inputs under full swing input conditions
[28, 29], that is
VG VS > VTHeq (3.31)
Conversion gain of this mixer depends on gm(eqv) and this value is less than both
gmn and gmp. Transconductance of PMOS transistor is lower than NMOS
transistor. Therefore, this type of mixer has low conversion gain. The equivalent
transconductance is given by
49
 1 1 1
= + (3.32)
g m ( eqv ) g mn g mp
and conversion gain is
2
GC = g m ( eqv ) R L (3.33)

(a) Circuit Description

Fig.37 shows the complete CMOS transconductor mixer.

VDD

C L C L

IF-
IF+
M2 M3
M1 M4

LO+ LO+
LO-
M5
M8
RF+ M6 M7
RF-

Figure 37: CMOS transconductor mixer

NMOS transistors M1-M4 are the commutating mixer biased just above the
threshold voltage. Transistors M5-M8 are biased in saturation region. Both the
NMOS and PMOS transistors are biased such that VG-VS>VTHeqv. Optimum
biasing of PMOS transistors was limited since on-chip, negative bias voltage is
not available and the gate terminal is connected to ground (that is VS=0).
However, with transistor sizing and appropriate VG, PMOS transistors are well
in saturation region.

(b) Design Approach

The design aim is to achieve high linearity (IIP3) with reasonable NF and GC.
Before starting the mixer design, linearity analysis of a single NMOS and a
50
single PMOS transistor were carried out. It is observed that for the same supply
voltage, bias current and transconductance, PMOS exhibits higher linearity than
NMOS but provides less gain due to difference in output impedance of both
transistors.
The design is initiated for low power consumption such as 6.5mW, with a
current of 2mA. VTHn and VTHp are known for 0.35 um CMOS process. The gate
of PMOS transistor is connected to ground and VS=0. Thus, required VG value
can be calculated to meet the following condition; VG-VS>VTHeqv
VTHn is 0.7 V and VTHp is 0.635 V. Therefore VG =1.5 V, is selected. M1-M4 are
biased just above the threshold voltage with transistor widths of 200 um.
Decreasing the width, reduces the IB, reduces GC and adds more switching noise.
The sizing of PMOS is important in determining the conversion gain and noise
figure of the mixer. A width of 400 um provides sufficient gmp for a conversion
gain of 2 dB at 0 dBm LO power.

(c) Simulation Results

The mixer is designed in Cadence in AMS 0.35um process. The S parameters

are measured using PSS and PSP analysis. Conversion gain and noise figure is
simulated using PSS, PAC and PNoise analysis. Finally, running QPSS and
QPAC analysis performs two-tone test for linearity.

15

10

5
Gc
dB

0
NF
-5

-10

-15
-5 -3 -1 1 3 5
LO (dBm)

Figure 38: Conversion gain and NF vs. LO

51
Conversion gain and noise figure response with LO power sweep is depicted in
Fig.38. S parameters and noise figure with frequency sweep is depicted in
Fig.39.

S21
-5 S22
dB

S33
NF
-15

-25
2.4 2.42 2.44 2.46 2.48 2.5
Frequency (GHz)

Figure 39: S21, S22, S33 & NF

25

10
Pout (dBm)

-5

-20

-35

-50

-65
-60 -45 -30 -15 0 15
Pin (dBm)

Figure 40: 1 dB compression point at 5 dBm LO

52
 25

-25

Pout (dBm)
-75

-125

-175

-225
-60 -45 -30 -15 0 15
Pin (dBm)

Figure 41: IIP3 at 5 dBm LO

1 dB compression point and IIP3 response of CMOS transconductor mixer is

depicted in Fig.40 and Fig.41 respectively. 1dB compression point of the mixer
is at 3.3 dBm. The mixer results an IIP3 of 13.5 dBm at 5 dBm LO power.

Parameters CMOS Reference

Transconductor Work [29]
Process 0.35 m 0.18 m
Supply Voltage 3.3 V 2.5 V
Power Cons (mW) 6.25 3.3
GC (dB) -0.2 -3
NF (dB) 8.2 -
P1dB (dBm) 3.3 -
IIP3 (dBm) 13.5 20
LO Power (dBm) 5 -

Table 8: CMOS transconductor specifications

Mixer simulated results are tabulated and compared with the reference work in
Table.8. Mixer provides excellent linearity with good NF at a power

53
consumption of 6.25mW. Since the PMOS has lower transconductance when
compared with NMOS, the drawback of this architecture is the large active area
occupied by the PMOS transistors to achieve good GC and NF.

3.4. Highly Linear Passive Mixer

As described in section 2.2.3.1, passive mixers are simple in construction and
easy to design. Passive mixers provide excellent linearity with minimum active
area overhead and without dc power consumption.

3.4.1. Resistive Ring Mixer

Resistive Ring Mixer is a double balanced passive mixer. This mixer is operated
by modulating the channel resistance with a large LO signal while the transistor
is kept in linear region. The channel is switched between two operating regions.
When the channel is in fully depleted region then the channel resistance is very
low and determined by the MOS dimensions. When the channel is in fully
inverted region, it has a very high resistance. The operation of mixer in linear
region results very low intermodulation products. A large LO signal is needed
for minimum conversion loss and higher linearity so that transistor fully
operates in the linear region [30].

(a) Mixer Design & Circuit Description

Generally, larger transistor width with minimum gate length reduces Ron but
adds more parasitic capacitance. On-resistance (Ron) of the switch is limited by
the channel conductance (gds) and the off-impedance is limited by the parallel
parasitic capacitances Cdb and Cgd. The equivalent circuit of a single MOS is
shown in Fig.42 and small signal model is given in Fig.43. gds is a time varying
function of LO power. The parasitic capacitances also give rise to harmonic
distortion because the parasitic capacitances behave like varactors [30].
In MOS resistive mixers, a small amount of VDS bias could be applied to
optimize the intermodulation distortion performance. MOS transistor exhibits
best linearity at some specific VDS [31].
Fig.44 shows the third derivative of output transconductance gds3 has minimum
value at a drain bias of 150 mV.

54
 G

RG

Cgd Cgs

D S

RD
Gds(t) RS

Cdb Csb

Figure 42: Equivalent circuit of MOS transistor

D

RD

Gds(t)

Cgd+Cdb
RS

Figure 43: Approximate small signal model

100

50
gds (mS)

gds3
gds2
gds1
0

-50
0 0.5 1 1.5 2

Vds (V)

Figure 44: Variation in g ds (1, 2,3) with change in Vds

55
The circuit consists of four switching transistors (M1-M4), drain-source biasing
network and coupling capacitors as shown in Fig.45. The switching transistors
are driven by LO signal in antiphase. Therefore, when M1 and M4 are on, output
is RF + , and when M2 and M3 are on, IF output is equal to RF-.

5k

LO+ LO-
10k
LO+ C C
C
RF+
LOP
VA VB

IF+ IF-
5k C C

RF-
10k
LO-
C C
C
LO- LO+
LON

Figure 45: Resistive quad passive mixer

(b) Simulation Results

12

NF
dB

0
S21

-6

-12
-5 0 5 10

LO (dBm)

Figure 46: Conversion loss & NF with LO power sweep

56
 -16.6

-16.9
dB S11

-17.2

-17.5
0 25 50 75 100
Frequency (MHz)

Figure 47: S11 response of passive mixer

10

0 S21
S22
dB

S33
-10 NF

-20
2.4 2.42 2.44 2.46 2.48 2.5
Frequency (GHz)

Figure 48: S parameters & NF response for 100 MHz output bandwidth

57
 30

Pout (dBm)
-20

-45

-70
-70 -55 -40 -25 -10 5 20
Pin (dBm)

Figure 49: 1dB compression point at 5 dBm LO

50

-25
Pout (dBm)

-100

-175

-250
-60 -40 -20 0 20
Pin (dBm)

Figure 50:IIP3 at 5 dBm LO

58
 20

10

dBm
1 dB CP
IIP3
0

-10
-5 0 5 10 15
LO (dBm)

Figure 51: 1dB CP and IIP3 with LO sweep

Parameters Quad Passive Mixer Reference Work[33]

Process 0.35 m 0.25 m
GC (dB) -6.45 -7
NF (dB) 6.35 7
P1dB (dBm) -0.45 2.9
IIP3 (dBm) 8.5 11.1
LO Power (dBm) 5 4

Table 9: 0.35 um passive mixer specifications

3.5. Summary
It is observed that CMOS transconductor mixer has highest linearity but
occupies an area of 6000 m 2 . Conversion gain is around 0 dB . Class AB
transconductor mixer and source degenerated mixer provide some conversion
gain but linearity is poor when compared with CMOS transconductor mixer or
passive mixer. Passive mixer has good linearity with advantage of zero dc power
consumption. By going for some higher process, the conversion loss can be
further reduced.
59
Table.10 summarizes and compares the results of four different mixer
architectures simulated in 0.35 um CMOS.

Parameters Sourced Class AB CMOS Passive

Degenerated Transconductor Transconductor Ring
Gilbert Mixer Mixer Mixer Mixer
Process 0.35 m
Input Frequency 60 MHz

LO Frequency 2.4 GHz

Output Frequency 2.46 GHz

Power Cons 16 8.25 6.25 -

(mW)
GC (dB) 1.5 2.12 -0.2 -6.5
NF (dB) 7.5 9.5 8.2 6.33
P1dB (dBm) -7.8 -0.5 3.3 -0.45
IIP3 (dBm) 1.8 8.5 13.5 8.5
LO Power (dBm) 0 5 5 5
Estimated 4000 6500 6000 500
Transistor Area
( m 2 )

Table 10: Spec comparison of linear mixers

3.6. Offset Mixer Placement Prospective

Different possible configurations of offset mixer placement in the main loop
were discussed in section1.3.4. Here we will focus on selection of a mixer for
the loopback setup, its required specifications and limitations in different
loopback configurations. Its obvious from the simulation results that passive
mixers are more area and power efficient when compared with active mixers.
Selection of an active or passive mixer for offset application in loopback setup
with their merits, demerits and limitations is as following.
60
3.6.1. Passive Offset Mixer

A passive mixer can be placed in the test loop in following four ways
TA follows offset mixer, LO port of the mixer is connected to PA output
and RF IN of the mixer is connected to the on-chip test generator. PA
output frequency is 2.4 GHz and power is typically 10 dBm. This power
is large enough to meet the LO swing requirement of passive mixer. IIP3
of the mixer is 8.5 dBm and 11.8 dBm at 5 dBm and 10 dBm LO power
respectively.
TA follows offset mixer, RF IN port is connected to PA output and LO
port is connected to test generator. A large on-chip swing is needed to
drive the LO port. The frequency at LO port is few MHz. IIP3 of the
mixer is measured with LO frequency of 60 MHz and RF input
frequency is 2.4 GHz. LO power is 5 dBm. This configuration results in
an IIP3 of 9.5 dBm. Swapping the LO and RF port increases mixers
IIP3 by 1 dB at the same LO power of 5 dBm. On the other hand,
conversion loss is degraded from -6.5 dB to -7.5 dB and noise figure is
raised from 6.33 dB to 7 dB.
Offset mixer follows TA, LO port is driven by PA output and RF IN is
connected to offset generator. As discussed in section.1.3.4(a). A too
week LO signal cant drive the mixer and this configuration is not
applicable.
Offset mixer follows TA, LO port is driven by on-chip test generator and
RF IN is connected to PA output. There is no effect on overall NF when
compared with first two cases, as both the mixer and TA are passive.

3.6.2. Active Offset Mixer

The four possible configurations are
TA follows active offset mixer, LO port of the mixer is driven by PA
output and RF IN of the mixer is connected to the on-chip test generator.
This loopback setup, as discussed in section.1.3.4, has lower overall
noise figure with active mixer in the loop. PA output frequency is 2.4
GHz and power is typically 10 dBm which is sufficient to drive
switching stage of an active mixer. However, PA output power greater
than 10 dBm will enhance the switching noise in the mixer.
61
 When TA follows active offset mixer, RF IN port is connected to PA
output and test generator drives LO port. A large on-chip swing is
needed to drive the LO port.
In this setup offset mixer follows TA, LO port is driven by PA output
and RF IN is connected to test generator. Like in passive offset mixer, as
discussed in section.1.3.4, a varying LO signal cant drive the mixer and
this configuration is not applicable.
Offset mixer follows TA, on-chip test generator drives LO port and RF
IN is connected to PA output. Overall NF of this configuration is higher
when compared with first two configurations for typical NF and GC
values. Therefore NF of the mixer is critical in case.

3.7. Conclusion
The offset mixer is an additional component required for loopback test. To
select suitable mixer architecture, power consumption and silicon area overhead
are also critical concerns other than linearity. Recalling the loopback test
configurations mentioned in Chapter1, the offset mixer could be placed in the
test loop with four different configurations. Active mixers consume dc power
and occupy large silicon area. In active mixers, when LO and RF ports are
swapped for loopback test, mixer becomes more nonlinear. This is due to the
fact that transconductance stage nonlinearity is enhanced at GHz frequencies.
When passive mixer is used as offset mixer then placement of the mixer doesnt
affect NFtotal. The passive mixer gives an IIP3 of 8.5 dBm at 2.4 GHz LO
frequency and an IIP3 of 9.5 dBm at 60 MHz LO frequency. Besides this high
linearity, active area is minimum and dc power consumption is almost zero. The
transistor area is at least ten times smaller than of active class AB and CMOS
transconductor mixer. It is decided to choose this architecture for the final
implementation. For higher process cut off frequency and improved conversion
loss, the offset mixer will be implemented in 0.13 um CMOS.

62
4. Proposed Mixer for Loopback Test

63
64
4.1. Passive Ring Mixer in 0.13 m CMOS
As described in Chapter 3, the two dominant sources of nonlinearity in CMOS
are third order input transconductance (gm3) and third-order output conductance
(gds3). As the gate length is reduced gm3 gets more linear but gds3 linearity
degrades. CMOS becomes more linear as the gate length is reduced at the
frequencies above 2 GHz, where capacitive element shunting effect is important.
The motive behind using 0.13 um process is the higher cut off frequency (fT),
improved conversion loss and reduced area consumption.

4.1.1. Design & Circuit Description

The design starts with the appropriate sizing of switching transistors. The width
of the transistor not only determines conversion loss and noise figure but the
circuit matching is also affected as described in section 3.1.4.1. Table.11
summarizes the effect of transistor width on parasitic capacitances and on-
resistance.
Width C gs ( fF ) C gd ( fF ) C db ( fF ) C sb ( fF ) g ds (mS )
10 m 6.2 7.35 0.5 0.5 1.38
25 m 15.5 18.5 0.7 0.7 3.45
55 m 34 40.5 1.35 1.34 7.5

Table 11: Parasitic capacitances with different widths

For 5 dBm of LO power and 500 impedance, LO voltage is 1.25 V. For a

transistor width of 25 um, the on-resistance can be approximately calculated by
1 L
Ron = = (4.1)
g ds eff C oxWV LO
Ron comes out to be 22.5 and source impedance is 500. For resistive quad
passive mixer, approximate conversion gain can be calculated using following
formula
2 RS
GC (dB ) 20 log (4.2)
RS + 2 Ron

65
GC (dB ) = -4.68
To calculate the conversion loss of quad passive mixer having equal source and
load resistance, an alternate method is reported in [30]. On and off impedances
of the switch is given by
1 1
Z ON RS + + RD (4.3)
n C ox (VLO + VGS Vth )
g ds W
L
where W =25 m nCox = 185 A /V 2
V LO = 1.25V VGS Vth =0
Z ON 22.5
1
Z OFF
j (C db + C gd )
(4.4)

For 25 um transistor width, Cgd and Cdb are 18.33 fF and 0.7 fF respectively,
whereas the output frequency is 2.46 GHz. Substituting these values in Eqn.4.4
yields
Z OFF 3400
Conversion loss is given by
GC = 3.92 + 20 log A0 (4.5)
and
n2 1
A0 = (4.6)
n
(1 + mn )1 +
m
Z OFF Z
whereas n= and m=
Z ON Z opt
For equal load and source impedance
Z = ZS = ZL (4.7)
and
Z opt = Z ON Z OFF (4.8)
Z ON and Z OFF are known, conversion loss for Z = Z S = Z L = 500 can be
calculated using Eqn.4.6, and GC - 5.4 dB

66
 Noise figure can be estimated by the following equation
2Z
NF (dB ) = GC (ideal ) 1 + ON (4.9)
ZS
NF (dB ) = 4.25 dB
Mixer is designed in 0.13 um AMS CMOS process. The transistor used has a cut
off frequency of 6 GHz. MIM capacitors for ac coupling and high resistivity
ploy resistors for biasing network is used.

Figure 52: Schematic diagram 0.13um CMOS passive mixer

4.1.2. Simulation Results

Simulation results are tabulated below. Conversion loss and noise figure is fairly
close to the calculated ones. Detailed results are given in section 4.3, where pre
and post layout simulation results are compared.
Parameters Quad Passive Mixer Reference Work [34]
Process 0.13 um 0.13um
GC (dB) -4.87 -5.5
NF (dB) 4.55 6.5
P1dB (dBm) -1.5 -
IIP3 (dBm) 7.65 10
LO Power (dBm) 5 5

Table 12: 0.13 um passive mixer specs

67
4.2. Layout Design
Layout of the fully differential quad ring passive mixer is carried out in 0.13 um
CMOS Austria Microsystems. This is six metal layer process.
The modular design strategy during the layout saves time and provides ease for
modification. The mixer is divided into cells and then integrated together to
form the complete mixer. Layout of the mixer is depicted in Fig.53.

Biasing
Network Mixer
Core

ac coupling
capacitor

Figure 53: Complete layout of mixer

A complete symmetrical layout has been drawn for differential operation. This
avoids mismatches in the differential circuit. The top metal layer (sixth layer) is
used for output interconnects to minimize the interconnect parasitic capacitance.
The low resistivity and maximum distance from the substrate results in low
parasitic effects. Guard ring has been placed around the mixer core to protect it
68
from noise coupling and provide effective isolation. DRC was run to validate the
design rules of the process and LVS to match the schematic of the mixer with
layout before RC extraction. The extraction includes the parasitic contributed by
via contacts also.

4.3. Pre & Post Layout Results Comparison

Simulations were carried out using Cadence RF Spectre to analyse the
mixer. First of all, S parameter test was run using PSS and PSP analysis.
Conversion loss is measured using PSS and PAC analysis. PSS and PNoise
are run to measure noise figure. Two-tone test is run to simulate the linearity
of the mixer. QPSS in conjunction with QPAC provides the most accurate
IIP3 is and 1dB compression point results for a mixer [35].

S21
0
PL-S21
S22
-5
PL-S22
dB

S33
-10
PL-S33
NF
-15
PL-NF

-20
2.4 2.425 2.45 2.475 2.5
Frequency (GHz)

Figure 54: Pre & post layout result comparison

Pre and post layout S parameters and noise figure simulation result is depicted in
Fig.54. Post layout S22 is degraded by 3 dB due to parasitic effects.
Fig.55 shows 1 dB compression point and IIP3 of the mixer is depicted in
Fig.56. IIP3 of the mixer is also measured with LO frequency of 60 MHz and
RF input frequency is 2.4 GHz. LO port is driven by 5 dBm signal power. This
69
configuration results in an IIP3 of 11.5 dBm as depicted in Fig.57. Swapping the
LO and RF port increases mixers IIP3 by 4 dB at the same LO power of 5 dBm.
On the other hand, conversion loss is degraded from -5.35 dB to -5.85 dB and
noise figure is raised from 4.7 dB to 5.15 dB.

20

0
Pout (dBm)
1st order
-20
1st order ref
-40

-60

-80
-60 -40 -20 0 20

Pin (dBm)

Figure 55: Post layout 1 dB CP at 5 dBm LO

50

0
Pout (dBm)

-50

-100

-150

-200
-70 -50 -30 -10 10 30
Pin (dBm)

Figure 56: Post layout IIP3 at 5 dBm LO

70
 0

Pout (dBm)
-50

-100

-150

-200
-60 -40 -20 0 20
Pin (dBm)

Figure 57: IIP3 for 60 MHz LO and 2.4 GHz RF in

Pre and post layout results are compared in Table.13.

Parameters Pre Layout Post Layout

GC (dB) -4.87 -5.35
NF (dB) 4.55 4.7
P1dB (dBm) -1.5 -1.2
IIP3 (dBm) 7.65 7.7
LO Power (dBm) 5 5

Table 13: Pre & post layout result comparison

71
72
5. Conclusions and Future Work

73
74
5.1. Conclusion:
The wireless communication integrated circuits are becoming more and more
complex and a high level of integration is needed for multifunction and
multistandard RF devices. This has made the testability of RF devices more
difficult. Traditional RF testing involves advanced test equipments and
instruments to carry out the sophisticated performance tests. On the other hand
on-chip testing reduces testing cost and the involved time. To implement on-
chip testing for IC RF transceivers, when the Tx and Rx are incompatible an
offset mixer is needed. This is an extra component incorporated on the chip to
enable on-chip test. The offset mixer is usually required to have a high linearity
in order to avoid the effect of masking the actual chip performance. On the other
hand, offset mixer power consumption must be possibly low with minimum
silicon area overhead to save the chip cost. Both active and passive linear mixer
architectures were studied and implemented in Cadence software. In active
mixers, both the transconductance stage and switching stage contribute to
nonlinearity. It was revealed that an active mixer can provide very high linearity
at the expense of very high power consumption (for example a source
degenerated Gilbert mixer in 0.35 um process, may provide an IIP3 of 30 dBm
with a power consumption of 100 mW) and high noise figure. The CMOS
transconductor mixer can achieve excellent linearity even with very low power
consumption but very large PMOS transistors are needed to guarantee the
conversion gain. This architecture has low noise figure as well.
When dc power consumption and silicon area is a concern, passive mixer proved
to the best candidate for this application. The double balanced passive quad
mixer with a high IIP3 and 1 dB compression point consumes no dc power and
the active transistor area is reduced at least by a factor of ten as compared to
active mixer architectures. Finally, the mixer is implemented in 0.13 um CMOS
process, taking advantage of its higher fT and reduced on-resistance in transistor
triode region. This results in improved conversion loss and noise figure as well.
On the other hand, IIP3 is slightly degraded as nonlinearity added by output
conductance is higher at shorter gate length. The post layout simulation results
IIP3 of 7.7 dBm, 1dB compression point of -1.2 dBm, conversion loss of -5.35
dB and noise figure of 4.7 dBm at LO power of 5 dBm.

75
5.2. Future Directions
A lot of research has been carried out on linearization of switching power
amplifiers but mixers linearization of different architectures still needs to be
explored, especially for passive mixer. Linearization techniques for
upconversion passive mixers may be investigated for further linearity
improvement.

76
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77
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81
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