Verilog VHDL Vlsi Final

XILINX ISE TOOLS
Introduction
Xilinx Tools is a suite of software tools used for the design of digital circuits implemented
using Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device
(CPLD).
The design procedure consists of
(a) Design entry

(b) Synthesis and implementation of the design
(c) Functional simulation
(d) Testing and verification.
Digital designs can be entered in various ways using the above CAD tools: using a
schematic
entry tool, using a hardware description language (HDL) Verilog or VHDL or a combination of
both.
The ISE software controls all aspects of the design flow. Through the Project Navigator
interface, we can access all of the design entry and design implementation tools. We can also
access
the files and documents associated with the project.
Project Navigator Interface

By default, the Project Navigator interface is divided into four panel sub-windows. On the
left aretop
the Start, Design, Files, and Libraries panels, which include display and access to the
source
files in the project as well as access to running processes for the currently selected source. The
Start
panel provides quick access to opening projects as well as frequently access reference material,
documentation and tutorials. At the bottom of the Project Navigator are the Console, Errors, and
Warnings panels, which display status messages, errors, and warnings. To the right is a multi-
document interface (MDI) window referred to as the Workspace. The Workspace enables us to view
design reports, text files, schematics, and simulation waveforms. Each window can be resized,
undocked from Project Navigator, moved to a new location within the main Project Navigator
window, tiled, layered, or closed.
We can use the View >Panels menu commands to open or close panels.
We can use the Layout > Load Default Layout to restore the default window layout.
Design Panel
The Design panel provides access to the View, Hierarchy, and Processes
panels.
View Panel
The View panel radio buttons enable us to view the source modules associated with the
Implementation or Simulation Design View in the Hierarchy panel. If we select Simulation,
we must select a simulation phase from the drop-down list.
Hierarchy Panel
The Hierarchy panel displays the project name, the target device, user documents,
design and
source files associated with the selected Design View. The View panel at the top of
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the Design panel allows us to view only those source files associated with the selected
Design
View, such as Implementation or Simulation.
Each file in the Hierarchy panel has an associated icon. The icon indicates the file
type (HDL file, schematic, core, or text file, for example). For a complete list of possible
source types and their associated icons, refer the Source File Types topic in the ISE Help.
From Project Navigator, select Help > Help Topics to view the ISE Help. If a file contains
lower levels of hierarchy, the icon has a plus symbol (+) to the left of the name. We can
expand the hierarchy by clicking the plus symbol (+). We can open a file for editing by
double-clicking on the filename. types and their associated icons, see the Source File
Types
topic in the ISE Help. From Project Navigator, select Help > Help Topics to view the ISE
Help.
If a file contains lower levels of hierarchy, the icon has a plus symbol (+) to the left
of We can expand the hierarchy by clicking the plus symbol (+). We can open a file
the name.
for editing by double-clicking on the filename.
Processes Panel
The Processes panel is context sensitive, and it changes based upon the source type
selected in the Sources panel and the top-level source in our project. From the Processes
panel, we can run the functions necessary to define, run, and analyze our
design.
The Processes panel provides access to the following functions:
Design Summary/Reports
Provides access to design reports, messages, and summary of results data. Message
filtering can also be performed.
Design Utilities
Provides access to symbol generation, instantiation templates, viewing command
history,line
and simulation library compilation.
User Constraints
Provides access to editing location and timing constraints.
Synthesis
Provides access to Check Syntax, Synthesis, View RTL or Technology Schematic,
and synthesis reports. Available processes vary depending on the synthesis tools we
use.
Implement Design
Provides access to implementation tools and post-implementation analysis
Generatetools.
Programming File
Provides access to bit stream generation.
Configure Target Device
Provides access to configuration tools for creating programming files and
programming the device.
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The Processes panel incorporates dependency management technology. The tools
keep track of which processes have been run and which processes need to be run.
Graphical
status indicators display the state of the flow at any given time. When we select a process
in
the flow, the software automatically runs the processes necessary to get to the desired
step.
For example, when we run the Implement Design process, Project Navigator also runs the
Synthesis process because implementation is dependent on up-to-date synthesis
results.
To view a running log of command line arguments used on the current project,
Designexpand
Utilities and select View Command Line Log File.
Files Panel
The Files panel provides a flat, sortable list of all the source files in the project. Files
can be sorted by any of the columns in the view. Properties for each file can be viewed and
modified by right-clicking on the file and selecting Source Properties.
Libraries Panel
The Libraries panel enables you to manage HDL libraries and their associated HDL
source files. You can create, view and edit libraries and their associated
sources.
Console Panel
The Console provides all standard output from processes run from Project Navigator.
It displays errors, warnings, and information messages. Errors are signified by a red X next
to
the message; while warnings have a yellow exclamation mark (!).
Errors Panel
The Errors panel displays only error messages. Other console messages are filtered
out.
Warnings Panel
The Warnings panel displays only warning messages. Other console messages are
filtered out.
Error Navigation to Source

We can navigate from a synthesis error or warning message in the Console, Errors, or
Warnings panel to the location of the error in a source HDL file. To do so, select the error or
warning
message, right-click the mouse, and select Go to Source from the right-click menu.The HDL source
file opens, and the cursor moves to the line with the error.
Error Navigation to Answer Record

To navigate to the Answer Record, select the error or warning message, right-click the
mouse, and select Go to Answer Record from the right-click menu. The default Web browser opens
and displays all Answer Records applicable to this message.
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Workspace
The Workspace is where design editors, viewers, and analysis tools open. These include ISE
Text Editor, Schematic Editor, Constraint Editor, Design Summary/Report Viewer, RTL and
Technology Viewers, and Timing Analyzer.Other tools such as the PlanAhead software for I/O
planning and floorplanning, ISim,third-party text editors, XPower Analyzer, and iMPACT open in
separate windows outside the main Project Navigator environment when
invoked.
Design Summary/Report Viewer
The Design Summary provides a summary of key design data as well as access to all of the
messages and detailed reports from the synthesis and implementation tools. The summary lists
high-
level information about our project, including overview information, a device utilization summary,
performance data gathered from the Place and Route (PAR) report, constraints information, and
summary information from all reports with links to the individual reports. A link to the System
Settings report provides information on environment variables and tool settings used during the
design implementation.
Steps to design a Project
1. Start Xilinx ISE Project Navigator.

2. Create a new project.
Click on File, and then choose New Project on the drop down menu
Enter the project name
Choose the project location
Leave the working directory entry blank
Choose HDL as the source type from the Top-Level Source Type menu
Click Next button
3. We will be asked to select the hardware and design flow for this project.
For Family, choose Spartan3E
For Device, choose XC3S500E
For Package, choose PQ 208
For Speed, choose -4
For Simulator, choose ISim (VHDL/Verilog)
Click Next button
4. A project summary will appear. Click on the Finish button.
5. Now we have a project by the name that we have given. Next we want to specify the files in
this project are for behavioral simulation.
Click on Simulation
6. Now we want to add a new file to our project.
Click on Project, choose New Source
Choose Verilog/VHDL Module as the file type
In the File name: box enter the desired file name
Click on the Next button
7. We will be asked for the modules port names/types. We can skip this step and click on the
Next button.
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8. A project summary will appear. Click on the Finish button.
9. The desired file has been added to our project.
10. Click on the desired Verilog file (.v) tab to show the file contents. We are now ready to
specify the desired modules functionality.
11. Notice that the ISE has already entered comments sections along with a couple of lines
of code for us.
The line `timescale 1ns/ 1ps is located at the top of the file. The Verilog language
uses dimensionless time units, and these time units are mapped to real time units
within the simulator. `Timescale is used to map to the real time values using the
statement `timescale <time1> / <time2>, where <time1> indicates the time units
associated with the #delay values, and the <time2> indicates the minimum step
time
used by the simulator
The desired module is also declared using module module_name(); and end
module, but the ports are left for us to define
We finish specifying the functionality of the desired module
12. We also want to add a test bench and again follow Steps 8 11. Then we add the
functionality of the test bench module.
13. After saving both file_name.v and file_name_tb.v, we want to check the syntax of both
files.
Expand the ISim Simulator menu, double click on Behavioral Check Syntax
If the syntax was correct, a checkmark appears beside the Check Syntax menu
If the syntax was incorrect, the window at the bottom will list the individual errors
14. Now its time to simulate the design

Double-click on the Simulate Behavioral Model icon
15. The ISim Simulator opens in a new windows displaying a waveform and run a default
simulation for some number of time units. We can now check the desired modules
functionality. Further, the $display statements included in the test bench appear in the
lower
window.
16. To view the beginning of simulation, click on the Go to Time 0 buttons.
17. We can now see the simulation waveform for the beginning of our simulation. Click on the
Zoom Out button until you see the waveform shown in the image below.
18. To control the simulation time, we can restart the simulation and simulate for a specific
length of time. Either click on the Restart button or select Restart from the Simulation
menu.
We will now have an empty waveform.
19. To simulate for a specific length of time, enter the desired simulation time and click on the
Run for the time specified in the toolbar button. In our case, we want to simulate for 10
20. ns.
We now want to synthesize the desired circuit onto the Spartan3E Starter
Board.
Expand the source file listing by click on the + to left of desired file (finalname_tb.v)
in the Hierarchy area
Choose Implementation as the view
Double-click on the filename.v in the Hierarchy area
21. Before we synthesize our design, we need to map the desired inputs and outputs to the
pins of
the FPGA that we before we synthesize our design.
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22. To create User Constraint File, In process window, click timing constraints, a file with
extension .ucf is listed in the view window.
Double click on the filename.ucf, an editor window will open in that type required
input and output pin locations and save the file
23. We can now synthesize our design.
Click on the filename.v in the Hierarchy area
24. Double-click on Synthesize XST. This step will synthesize our design to the basic logic
structures of the FPGA (LUTs). When completed, displays a message Process "Synthesize"
completed successfully. If not, please go back and make sure you followed the previous
steps
correctly.
25. Double-click on Implement Design. This step will create a final implementation for our
design. When completed,displays a message Process "Generate Post-Place & Route Static
Timing" completed successfully. If not, please go back and make sure you followed the
previous steps correctly.
26. Double-click on Generate Programming File. This step will create the bitstream needed to
program the FPGA on the Spartan3E Starter Board. When completed,displays a message
"Generate Programming File" completed successfully. If not, please go back and make sure
you followed the previous steps correctly.
27. We are now ready to program the Spartan3E Starter Board.
Plug the power supply into an appropriate wall socket
Plug the power supply into the Spartan3 starter board
Connect the Spartan3 Starter Board to the USB port of your computer using the
supplied programming cable
Connect the other end of the supplied cable to Spartan3 Starter Board
Make sure your board is ON, a light should illuminate by the power supply if the
board is on
28. We will run the Xilinx iMPACT tool utilized to program the FPGA.
Double-click on Configure Target Device. This will launch the iMPACT tool in a
separate window
Double-click on Boundary-Scan in the iMPACT Flows area
Right click on the opened window and select initialize chain option
We will be asked to attach an SPI or BPI PROM. Click No
29. Right click on the second block, window will open, select the corresponding filename.bit.
The required bit file is ready to implement.
30. Right click on the second block, select program option, and device 2 is enabled to the pulse
program and then click ok.
31. We have the message that program succeeded.
32. In CPLD/FPGA trainer kit, apply the inputs for verifying the outputs.
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SYSTEM
DESIGN USING
VERILOG HDL,
XILINX ISE TOOL
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EX.NO:06 DESIGN OF TRAFFIC LIGHT CONTROLLER
22.10.2013
AIM:
To design a traffic light controller in Verilog HDL and to simulate and synthesis the same by
using XILINX ISE tool.
SOFTWARE & APPARATUS REQUIRED:

XILINX ISE tool 13.2
THEORY:
Traffic congestion is a major concern for many cities throughout the world. Developing a
sophisticated traffic monitoring and control system would result in an effective solution to this
problem. In a conventional traffic light controller, the traffic lights change at constant cycle time.
Hence it does not provide an optimal solution. Many traffic light controllers implemented in current
practice, are based on the 'time-of-the-day' scheme, which use a limited number of predetermined
traffic light patterns and implement these patterns depending upon the time of the day. These
automated systems do not provide an optimal control for fluctuating traffic volumes. A traffic light
controller based on fuzzy logic can be used for optimum control of fluctuating traffic volumes such
as over saturated or unusual load conditions. The objective is to improve the vehicular throughput
and minimize delays. The rules of fuzzy logic controller are formulated by following the same
protocols that a human operator would use to control the time intervals of the traffic light. The
length
of the current green phase is extended or terminated depending upon the 'arrival' i.e. the number
of
vehicles approaching the green phase and the 'queue' that corresponds to the number of queuing
vehicles in red phases.
SOURCE CODE:
module tlc(north,south,west,east,clk);
output [2:0]north,south,east,west;
input clk;
reg [1:0]state;
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LOGIC DIAGRAM:
RTL SCHEMATIC:
82
reg [2:0]north,south,east,west;
integer t=0;
initial state=2'b00;
always @(posedge clk)
case(state)
2'b00:
if(t>10)
begin
north=3'b010;
t=t+1;
if(t==15)
begin
state=2'b01;
t=0;
end
end
else begin
north=3'b001;
south=3'b100;
east=3'b100;
west=3'b100;
t=t+1;
end
2'b01:
if(t>10)
begin
south=3'b010;
t=t+1;
if(t==15)
begin
state=2'b10;
t=0;
end
end
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TEST BENCH:
module tlctb;
// Inputs
reg clk;
// Outputs
wire [2:0] north;
wire [2:0] south;
wire [2:0] west;
wire [2:0] east;
// Instantiate the Unit Under Test (UUT)
tlc uut (
.north(north),
.south(south),
.west(west),
.east(east),
.clk(clk)
);
initial
// Initialize Inputs
clk = 0;
always #20 clk=~clk;
// Add stimulus here
endmodule
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else begin
north=3'b100;
south=3'b001;
east=3'b100;
west=3'b100;
t=t+1;
end
2'b10:
if(t>10)
begin
east=3'b010;
t=t+1;
if(t==15)
begin
state=2'b11;
t=0;
end
end
else begin
north=3'b100;
south=3'b100;
east=3'b001;
west=3'b100;
t=t+1;
end
2'b11:
if(t>10)
begin
west=3'b010;
t=t+1;
if(t==15)
begin
state=2'b00;
t=0;
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SIMULATION RESULT:
86
end
end
else begin
north=3'b100;
south=3'b100;
east=3'b100;
west=3'b001;
t=t+1;
end
endcase
endmodule
RESULT:
Thus the traffic light controller was designed in Verilog HDL and simulated and
synthesized by using XILINX ISE tool.
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BLOCK DIAGRAM:
RTL SCHEMATIC:
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EX.NO:07 DESIGN OF 8-TAP FIR FILTER
22.10.2013
AIM:
To design an 8 tap FIR filter in Verilog HDL and to simulate and synthesis the same by using
XILINX ISE tool.

THEORY:
A finite impulse response (FIR) filter is a filter whose impulse response (or response to any
finite length input) is of finite duration, because it settles to zero in finite time. This is in contrast
to infinite impulse response (IIR) filters, which may have internal feedback and may continue to
respond indefinitely (usually decaying).
The impulse response of an Nth-order discrete-time FIR filter (i.e., with a Kronecker
delta impulse input) lasts for N + 1 samples, and then settles to
zero.
For a discrete-time FIR filter, the output is a weighted sum of the current and a finite
number
of previous values of the input. The operation is described by the following equation, which defines
the output sequence y[n] in terms of its input sequence x[n]:
SOURCE CODE:
module fir(data_out,data_in,clock,reset);
parameter order=8;
parameter word_size_in=8;
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TEST BENCH:
module fir_tb;
// Inputs
reg [7:0] data_in;
reg clock;
reg reset;
// Outputs
wire [17:0] data_out;
fir uut (
.data_out(data_out),
.data_in(data_in),
.clock(clock),
.reset(reset)
);
initial
clock=1'b0;
always #50 clock=~clock;
initial begin
data_in = 8'b00000000;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
data_in = 8'b00000001;
reset = 1;
#100;
data_in = 8'b00000010;
reset = 1;
#100;
data_in = 8'b00000011;
reset = 1;
#100;
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parameter word_size_out=2*word_size_in+2;
parameter b0=8'd1;
parameter b1=8'd1;
parameter b2=8'd1;
parameter b3=8'd1;
parameter b4=8'd1;
parameter b5=8'd1;
parameter b6=8'd1;
parameter b7=8'd1;
parameter b8=8'd1;
output[word_size_out-1:0] data_out;
input[word_size_in-1:0] data_in;
input clock,reset;
reg[word_size_in-1:0] samples[0:order];
integer k;
assign
data_out=b0*samples[0]+b1*samples[1]+b2*samples[2]+b3*samples[3]+b4*samples[4]+b5*sa
mple
s[5]+b6*samples[6]+b7*samples[7]+b8*samples[8];
always@(posedge clock)
if(reset==0)
begin
for(k=0;k<=order;k=k+1)
samples[k]<=0;
end
else
begin
samples[0]<=data_in;
samples[k]<=samples[k-1];
end
endmodule
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data_in = 8'b00000100;
reset = 1;
#100;
data_in = 8'b00000101;
reset = 1;
#100;
data_in = 8'b00000110;
reset = 1;
#100;
data_in = 8'b00000111;
reset = 1;
#100;
end
endmodule
SIMULATION RESULT:
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RESULT:
Thus an 8 tap FIR filter was designed in Verilog HDL and simulated and synthesized
by using XILINX ISE tool.
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BLOCK DIAGRAM:
RTL SCHEMATIC:
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EX.NO:08 DESIGN OF 8-TAP IIR FILTER
29.10.2013
AIM:
To design an 8 tap IIR filter in Verilog HDL and to simulate and synthesis the same by using
XILINX ISE tool.

THEORY:
Infinite impulse response (IIR) is a property applying to many linear time-invariant systems.
Common examples of linear time-invariant systems are most electronic and digital filters. Systems
with this property are known as IIR systems or IIR filters, and are distinguished by having
an impulse response which does not become exactly zero past a certain point, but continues
indefinitely. This is in contrast to a finite impulse response in which the impulse
response h(t) does become exactly zero at times t > T for some finite T, thus being of finite
duration.
In practice, the impulse response even of IIR systems usually approaches zero and can be
neglected past a certain point. However the physical systems which give rise to IIR or FIR
responses
are dissimilar, and therein lies the importance of the distinction. For instance, analog electronic
filters
composed of resistors, capacitors, and/or inductors (and perhaps linear amplifiers) are generally
IIR
filters. On the other hand, discrete-time filters (usually digital filters) based on a tapped delay
line employing no feedback are necessarily FIR filters.
Digital filters are often described and implemented in terms of the difference equation that
defines how the output signal is related to the input signal:
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TEST BENCH:
module iir_filter_tb;
// Inputs
reg [7:0] data_in;
reg clock;
reg reset;
// Outputs
wire [17:0] data_out;
wire [17:0] data_feedback;
wire [17:0] data_feedforward;
iir_filter uut (
.data_out(data_out),
.data_in(data_in),
.clock(clock),
.reset(reset),
.data_feedback(data_feedback),
.data_feedforward(data_feedforward)
);
initial
clock=1'b0;
always
#50
clock=~clock;
initial begin
data_in = 8'b00000000;
reset = 0;
// Wait 100 ns for global reset to finis
#100;
data_in=8'b00000001;
reset=1;
end
endmodule
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SOURCE CODE:
module iir_filter(data_out,data_in,clock,reset,data_feedback,data_feedforward);
parameter order=8;
parameter word_size_in=8;
parameter word_size_out=2*word_size_in+2;
output[word_size_out-1:0]data_out;
input[word_size_in-1:0]data_in;
input clock,reset;
parameter b0=8'd1;
parameter b1=8'd1;
parameter b2=8'd1;
parameter b3=8'd1;
parameter b4=8'd1;
parameter b5=8'd1;
parameter b6=8'd1;
parameter b7=8'd1;
parameter b8=8'd1;
parameter a1=8'd1;
parameter a2=8'd1;
parameter a3=8'd1;
parameter a4=8'd1;
parameter a5=8'd1;
parameter a6=8'd1;
parameter a7=8'd1;
parameter a8=8'd1;
reg[word_size_in-1:0]samples_in[0:order];
reg[word_size_in-1:0]samples_out[1:order];
inout[word_size_out-1:0]data_feedforward;
inout[word_size_out-1:0]data_feedback;
integer k;
assign
data_feedforward=b0*samples_in[0]+b1*samples_in[1]+b2*samples_in[2]+b3*samples_in[3]+b4
*s
amples_in[4]+b5*samples_in[5]+b6*samples_in[6]+b7*samples_in[7]+b8*samples_in[8]
;
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SIMULATION RESULT:
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assign
data_feedback=a1*samples_out[1]+a2*samples_out[2]+a3*samples_out[3]+a4*samples_out[4]+
a5*
samples_out[5]+a6*samples_out[6]+a7*samples_out[7]+a8*samples_out[8]
;
assign data_out=data_feedforward+data_feedback;
always@(posedge clock)
if(reset==0)
begin
samples_in[0]<=0;
begin
samples_in[k]<=0;
samples_out[k]<=0;
end
end
else
begin
samples_in[0]<=data_in;
samples_in[1]<=samples_in[0];
samples_out[1]<=data_out;
begin
samples_in[k]<=samples_in[k-1];
samples_out[k]<=samples_out[k-1];
end
end
endmodule
RESULT:
Thus an 8 tap IIR filter was designed in Verilog HDL and simulated and synthesized
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ARITHMETIC AND LOGIC UNIT:
RTL SCHEMATIC:
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EX.NO:09 DESIGN AND IMPLEMENTATION OF ALU
05.11.2013
AIM:
To design an ALU in Verilog HDL and to simulate and synthesis the same by using XILINX
ISE tool and implement by using SPARTAN 3E FPGA KIT.

SPARTAN 3E FPGA KIT
THEORY:
In computing, ALU is a digital circuit that performs integer arithmetic and logical operations.
The ALU is a fundamental building block of the central processing unit of a computer, and even the
simplest microprocessors contain one for purposes such as maintaining timers. The processors
found
inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very
complex ALUs; a single component may contain a number of ALUs.
ALUs are designed to perform integer calculations. Therefore, besides adding and
subtracting
numbers, ALUs often handle the multiplication of two integers, since the result is also an integer.
However, ALUs typically do not perform division operations, since the result may be a fraction, or a
"floating point" number. Instead, division operations are usually handled by the floating-point unit
(FPU), which also performs other non-integer calculations.
SOURCE CODE:
module alu(s,in1,in2,sel,d,clk,reset);
input [1:0]in1,in2;
input [3:0]sel;
reg [3:0]d;
output [3:0]d;
input clk,reset;
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TEST BENCH:
module alu_tb;
// Inputs
reg [1:0] in1;
reg [1:0] in2;
reg [3:0] sel;
reg clk;
reg reset;
// Outputs
wire [8:0] s;
wire [3:0] d;
alu uut (
.s(s),
.in1(in1),
.in2(in2),
.sel(sel),
.d(d),
.clk(clk),
.reset(reset)
);
initial
clk = 1'b0;
always #50 clk = ~clk;
initial begin
in1 = 2'b00;
in2 = 2'b00;
sel = 0;
reset = 0;
#100;
in1 = 2'b01;
in2 = 2'b11;
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output[8:0]s;
reg [8:0]s;
case(sel)
4'b0000:d <= in1&in2;
4'b0001:d <= in1|in2;
4'b0010:d <= in1^in2;
4'b0011:d <= {00,(~(in1^in2))};
4'b0100:d <= in1-in2;
4'b0101:d <= in1+in2;
4'b0110:d <= in1*in2;
4'b0111:d <= {00,(~(in1))};
4'b1000:d <= {00,(~(in2))};
4'b1001:d <= {00,(in1>>1)};
4'b1010:d <= {00,(in1<<1)};
4'b1011:d <= {00,(in2>>1)};
4'b1100:d <= {00,(in2<<1)};
4'b1101:d <= {00,~(in1&in2)};
4'b1110:d <= {00,~(in1|in2)};
4'b1111:d <= {in1,in2};
endcase
case(d)
4'b0000: s <= 9'b000000011;
4'b0001: s <= 9'b010011111;
4'b0010: s <= 9'b000100101;
4'b0011: s <= 9'b000001101;
4'b0100: s <= 9'b010011001;
4'b0101: s <= 9'b001001001;
4'b0110: s <= 9'b001000001;
4'b0111: s <= 9'b000011111;
4'b1000: s <= 9'b000000001;
4'b1001: s <= 9'b000001001;
default: s <= 9'b000000000;
103
sel = 4'b0001;
reset = 1;
end
endmodule
PIN ASSIGNMENT:
NET "sel<0>" LOC="P72";
NET "s<0>" LOC="P19";
NET "s<1>" LOC="P18";
NET "s<2>" LOC="P16";
NET "s<3>" LOC="P15";
NET "s<4>" LOC="P12";
NET " s<5>" LOC="P11";
NET " s<6>" LOC="P9";
NET " s<7>" LOC="P8";
NET " s<8>" LOC="P4";
NET "in1<0>" LOC="P101";
NET "in1<1>" LOC="P91";
NET "in2<0>" LOC="P194";
NET "in2<1>" LOC="P204";
104
endcase
endmodule
105
SIMULATION RESULT:
IMPLEMENTATION RESULT:
106
RESULT:
Thus an ALU was designed in Verilog HDL and simulated and synthesized by using
XILINX ISE tool and implemented using SPARTAN 3E FPGA kit.
107
RTL SCHEMATIC:
TEST BENCH:
module booth_tb;
// Inputs
reg clk;
reg enable;
reg [3:0] multiplier;
reg [3:0] multiplicand;
// Outputs
wire [7:0] product;
booth_mul uut (
.clk(clk),
.enable(enable),
.multiplier(multiplier),
.multiplicand(multiplicand),
.product(product)
);
108
EX.NO:10 DESIGN OF BOOTH MULTIPLIER
28.11.2013
AIM:
To design a booth multiplier in Verilog HDL and to simulate and synthesis the same by
using
XILINX ISE tool and implement by using SPARTAN 3E FPGA KIT.

SPARTAN 3E FPGA KIT
THEORY:
BOOTH MULTIPLIER:
Booth's algorithm is a multiplication algorithm that multiplies two signed binary numbers
in two's complement notation.
ALGORITHM:
Booth's algorithm examines adjacent pairs of bits of the N-bit multiplier Y in signed two's
complement representation, including an implicit bit below the least significant bit, y -1 = 0. For
each
bit yi, for i running from 0 to N-1, the bits yi and yi-1 are considered. Where these two bits are equal,
the product accumulator P is left unchanged. Where yi = 0 and yi-1 = 1, the multiplicand times 2i is
added to P; and where yi = 1 and yi-1 = 0, the multiplicand times 2i is subtracted from P. The final
value of P is the signed product.
The representation of the multiplicand and product are not specified; typically, these are
both
also in two's complement representation, like the multiplier, but any number system that supports
addition and subtraction will work as well. As stated here, the order of the steps is not determined.
Typically, it proceeds from LSB to MSB, starting at i = 0; the multiplication by 2 i is then typically
replaced by incremental shifting of the P accumulator to the right between steps; low bits can be
shifted out, and subsequent additions and subtractions can then be done just on the highest N bits
of P.[1] There are many variations and optimizations on these details.
109
initial
clk=0;
always #1 clk=~clk;
initial begin
enable = 0;
multiplier = 0;
multiplicand = 0;
#100;
enable=1;
multiplier=0101;
multiplicand=0101;
#100;
enable=1;
multiplier=0111;
multiplicand=1101;
#100;
enable=1;
multiplier=0011;
multiplicand=1101;
#100;
enable=1;
multiplier=1100;
multiplicand=1111;
end
endmodule
PIN ASSIGNMENT:
NET "enable" LOC ="P6";
NET "multiplier<0>" LOC ="P101";
110
The algorithm is often described as converting strings of 1's in the multiplier to a high-order
+1 and a low-order 1 at the ends of the string. When a string runs through the MSB, there is no
high-order +1, and the net effect is interpretation as a negative of the appropriate
value.
SOURCE CODE:
module booth_mul #(parameter WIDTH=4)
(input clk,
input enable,
input [WIDTH-1:0]multiplier,
input [WIDTH-1:0]multiplicand,
output reg [2*WIDTH-1:0]product);
parameter IDLE = 2'b00,
ADD = 2'b01,
SHIFT = 2'b10,
OUTPUT = 2'b11;
reg [1:0]current_state, next_state;
reg [2*WIDTH+1:0]a_reg,s_reg,p_reg,sum_reg;
reg [WIDTH-1:0]iter_cnt;
wire [WIDTH:0]multiplier_neg;
if (!enable) current_state = IDLE;
else current_state = next_state;
always @* begin
next_state = 2'bx;
case(current_state)
IDLE: if (enable) next_state = ADD;
else next_state = IDLE;
ADD: next_state = SHIFT;
SHIFT: if (iter_cnt==WIDTH) next_state = OUTPUT;
else next_state = ADD;
OUTPUT: next_state = IDLE;
endcase
end
assign multiplier_neg = -{multiplier[WIDTH-1],multiplier};
111
NET "multiplicand<0>" LOC="P204";
NET "multiplicand<1>" LOC ="P194";
NET "product<7>" LOC ="P108";
NET "clk" LOC ="P80";
SIMULATION RESULT:
112
always @(posedge clk) begin
case (current_state)
IDLE :begin
a_reg <= {multiplier[WIDTH-1],multiplier,{(WIDTH+1){1'b0}}};
s_reg <= {multiplier_neg,{(WIDTH+1){1'b0}}};
p_reg <= {{(WIDTH+1){1'b0}},multiplicand,1'b0};
iter_cnt <= 0;
end
ADD : begin
case (p_reg[1:0])
2'b01 : sum_reg <= p_reg+a_reg;
2'b10 : sum_reg <= p_reg+s_reg;
2'b00,2'b11 : sum_reg <= p_reg ;
endcase
iter_cnt <= iter_cnt + 1;
end
SHIFT :begin
p_reg <= {sum_reg[2*WIDTH+1],sum_reg[2*WIDTH+1:1]};
end
OUTPUT: product = p_reg>>1;
endcase
end
endmodule
RESULT:
Thus the booth multiplier was designed in Verilog HDL and simulated and
synthesized by using XILINX ISE tool and implemented using SPARTAN 3E FPGA kit.
113
114
SYSTEM
DESIGN USING
VHDL,
XILINX ISE TOOL
115
BLOCK DIAGRAM:
a)Selection by XOR gate:
RTL SCHEMATIC:
116
EX.NO:11 FOUR BIT ASYNCHRONOUS UP DOWN COUNTER
05.12.2013
AIM:
To design a four bit asynchronous up down counter in VHDL and to simulate and
synthesis
the same by using XILINX ISE tool.

THEORY:
Four bit asynchronous up/down counter is the type of counter in which all the flip-flops
are
connected in the way that output of the first flip-flop drives the clock for next flip-flop. The
outputs
of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input
(UP
or DOWN). The direction of counting is determined by which count input is pulsed while the
other
count input is high.
All four counters are fully programmable; that is, each output may be preset to either level
by
placing a low on input and entering the desired data at the data inputs. This feature allows the
counters to be used as modulo-N divider simply by modifying the count length with the preset
inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high
level is applied. The clear function is independent of the count and inputs.This counter was
designed
to be cascaded without the need for external circuitry. The borrow output Producesa low-level
pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry output
produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counter then
can be cascaded easily by feeding the outputs to DOWN and UP, respectively, of the succeeding
counter.
For selection by Xor gate,
Sel =0 down counter
Sel = 1 up counter
117
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY udc_xorg_tb IS
END udc_xorg_tb;
ARCHITECTURE behavior OF udc_xorg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT udc_xorg
PORT(
clk : IN std_logic;
sel : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(3 downto 0);
qb : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal sel : std_logic := '0';
signal rst : std_logic := '0';
--BiDirs
signal q : std_logic_vector(3 downto 0);
signal qb : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: udc_xorg PORT MAP (
clk => clk,
sel => sel,
rst => rst,
q => q,
qb => qb
);
118
SOURCE CODE:
a)Counter by using XOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity udc_xorg is
port(clk,sel,rst:in std_logic;
q:inout std_logic_vector(3 downto 0);
qb:inout std_logic_vector(3 downto 0));
end udc_xorg;
architecture udc_arch of udc_xorg is
component xorg is
port(a,b:in std_logic;
c:out std_logic);
end component;
component tff is
port(t,clk,rst:in std_logic;
q,qb:inout std_logic);
end component;
signal s:std_logic_vector(0 to 2);
begin
t0: tff port map('1',clk,rst,q(0),qb(0));
x0: xorg port map(sel,q(0),s(0));
t1: tff port map('1',s(0),rst,q(1),qb(1));
end udc_arch;
library IEEE;
entity tff is
port(t,clk,rst:in STD_LOGIC;
q,qb:inout STD_LOGIC);
119
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
end process;
stim_proc: process
begin
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
rst<='0';
wait for 200 ns;
rst<='1';
sel<='0';
wait for 160 ns;
sel<='1';
wait;
end process;
END;
SIMULATION RESULT:
120
end tff;
architecture arch_tff of tff is
begin
process(clk)
begin
if(rst='0')
then q<='0';
elsif(clk'event and clk='1')
then if (t='1')
then q<=not q;
else q<=q;
end if;
end if;
end process;
qb<=not q;
end arch_tff;
library IEEE;
entity xorg is
c:out std_logic);
end xorg;
architecture xorg_arch of xorg is
begin
c<=a xor b;
end xorg_arch;
121
BLOCK DIAGRAM:
b)Selection by 2:1 MUX:
RTL SCHEMATIC:
122
b)Counter by using 2:1 MUX:
library IEEE;
entity udc_mux is
port(clk,sel,rst:in std_logic;
q:inout std_logic_vector(3 downto 0);
qb:inout std_logic_vector(3 downto 0));
end udc_mux;
architecture arch_udc_mux of udc_mux is
component mux is
port(i0,i1:in std_logic;
sel:in std_logic;
o:out std_logic);
end component;
component tff is
port(t,clk,rst:in std_logic;
q,qb:inout std_logic);
end component;
signal s:std_logic_vector(0 to 2);
begin
t0: tff port map('1',clk,rst,q(0),qb(0));
m0: mux port map(q(0),qb(0),sel,s(0));
end arch_udc_mux;
library IEEE;
entity tff is
port(t,clk,rst:in STD_LOGIC;
q,qb:inout STD_LOGIC);
123
TEST BENCH:
LIBRARY ieee;
ENTITY udc_mux_tb IS
END udc_mux_tb;
ARCHITECTURE behavior OF udc_mux_tb IS
COMPONENT udc_mux
PORT(
clk : IN std_logic;
sel : IN std_logic;
rst : IN std_logic;
);
END COMPONENT;
--Inputs
--BiDirs
BEGIN
uut: udc_mux PORT MAP (
clk => clk,
sel => sel,
rst => rst,
q => q,
qb => qb
);
124
end tff;
architecture arch_tff of tff is
begin
process(clk)
begin
if(rst='0')
then q<='0';
elsif(clk'event and clk='1')
then if (t='1')
then q<=not q;
else q<=q;
end if;
end if;
end process;
qb<=not q;
end arch_tff;
library IEEE;
entity mux is
sel:in std_logic;
o:out std_logic);
end mux;
architecture arch_mux of mux is
begin
o<= (i0 and (not sel)) or (i1 and sel);
end arch_mux;
125
begin
clk <= '0';
clk <= '1';
end process;
stim_proc: process
begin
wait for 100 ns;
rst<='0';
wait for 100 ns;
rst<='1';
sel<='0';
wait for 100 ns;
sel<='1';
wait;
end process;
END;
SIMULATION RESULT:
126
RESULT:
Thus a four bit asynchronous up down counter in VHDL and simulated and
127
BLOCK DIAGRAM:
a)Selection by XOR gate:
RTL SCHEMATIC:
128
EX.NO:12 FOUR BIT SYNCHRONOUS JOHNSON / RING COUNTER
05.12.2013
AIM:
To design a four bit synchronous Johnson/Ring counter in VHDL and to simulate and
synthesis the same by using XILINX ISE tool.

THEORY:
A Ring Counter is a type of counter composed of a circular shift register. The output of the last
shift register is fed to the input of the first register. There are two types of ring
counters:
A Straight Ring Counter or over beck counter connects the output of the last shift register to
the first shift register input and circulates a single one (or zero) bit around the ring. For
example, in a 4-register counter, with initial register values of 1000, the repeating pattern
is:
1000, 0100, 0010, 0001, 1000... . note that one of the registers must be pre-loaded with a 1
(or 0) in order to operate properly.
A Twisted Ring Counter, also called Johnson Counter, connects the complement of the output
of the last shift register to the input of the first register and circulates a stream of ones followed by
zeros around the ring. For example, in a 4-register counter, with initial register values of 0000, the
repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001,
0000... .
For selection by Xor gate,
Sel =0 Ring counter
Sel = 1 Johnson counter
129
TEST BENCH:
LIBRARY ieee;
ENTITY jrc_xorg_tb IS
END jrc_xorg_tb;
ARCHITECTURE behavior OF jrc_xorg_tb IS
COMPONENT jrc_xorg
PORT(
clk : IN std_logic;
rst : IN std_logic;
sel : IN std_logic;
);
END COMPONENT;
--Inputs
--BiDirs
BEGIN
uut: jrc_xorg PORT MAP(
clk => clk,
rst => rst,
sel => sel,
q => q,
qb => qb
);
130
a)Counter by using XOR gate:
SOURCE CODE:
library IEEE;
entity jrc_xorg is
port(clk,rst,sel:in std_logic;
q,qb:inout std_logic_vector(3 downto 0));
end jrc_xorg;
architecture arch_jrc_xorg of jrc_xorg is
component xor1g is
c:inout std_logic);
end component;
component jkff is
port(j,k,clk,rst:in std_logic;
q:inout std_logic;
qb:inout std_logic);
end component;
signal p:std_logic;
begin
x0:xor1g port map (q(3),sel,p);
f1:jkff port map(p,not p,clk,rst,q(0),qb(0));
f2:jkff port map(q(0),qb(0),clk,rst,q(1),qb(1));
end arch_jrc_xorg;
library IEEE;
entity xor1g is
c:inout std_logic);
end xor1g;
architecture arch_xor1g of xor1g is
131
begin
clk <= '0';
clk <= '1';
end process;
stim_proc: process
begin
wait for 100 ns;
rst<='0';
wait for 100 ns;
rst<='1';
sel<='1';
wait for 110 ns;
sel<='0';
wait;
end process;
END;
SIMULATION RESULT:
132
begin
c<=a xor b;
end arch_xor1g;
library IEEE;
entity jkff is
q:inout std_logic;
end jkff;
architecture arch_jkff of jkff is
begin
process(clk,rst)
begin
if(rst='0') then
q<='0';
elsif(rst='1') then
if(clk='1' and clk'event) then
if(j='0' and k='0') then
q<=q;
elsif(j='0' and k='1')then
q<='0';
q<='1';
else q<=not(q);
end if;
end if;
end if;
end process;
qb<=not(q);
end arch_jkff;
133
BLOCK DIAGRAM:
b)Selection by 2:1 MUX:
RTL SCHEMATIC:
134
b)Counter by using 2:1 MUX:
SOURCE CODE:
library IEEE;
entity jrc_mux is
port(clk,rst,sel:in std_logic;
q,qb:inout std_logic_vector(3 downto 0));
end jrc_mux;
architecture arch_jrc_mux of jrc_mux is
component mux is
sel:in std_logic;
o:out std_logic);
end component;
component jkff is
q:inout std_logic;
end component;
signal p:std_logic;
begin
m0:mux port map (q(3),qb(3),sel,p);
f1:jkff port map(p,not p,clk,rst,q(0),qb(0));
end arch_jrc_mux;
library IEEE;
entity mux is
sel:in std_logic;
o:out std_logic);
135
TEST BENCH:
LIBRARY ieee;
ENTITY jrc_mux_tb IS
END jrc_mux_tb;
ARCHITECTURE behavior OF jrc_mux_tb IS
COMPONENT jrc_mux
PORT(
clk : IN std_logic;
rst : IN std_logic;
sel : IN std_logic;
);
END COMPONENT;
--Inputs
--BiDirs
BEGIN
uut: jrc_mux PORT MAP(
clk => clk,
rst => rst,
sel => sel,
q => q,
qb => qb
);
136
end mux;
architecture mux_arch of mux is
begin
o<= (i0 and (not sel)) or (i1 and sel);
end mux_arch;
library IEEE;
entity jkff is
q:inout std_logic;
end jkff;
architecture arch_jkff of jkff is
begin
process(clk,rst)
begin
if(rst='0') then
q<='0';
elsif(rst='1') then
if(clk='1' and clk'event) then
if(j='0' and k='0') then
q<=q;
q<='0';
q<='1';
else q<=not(q);
end if;
end if;
end if;
end process;
qb<=not(q);
end arch_jkff;
137
begin
clk <= '0';
clk <= '1';
end process;
stim_proc: process
begin
wait for 100 ns;
rst<='0';
wait for 100 ns;
rst<='1';
sel<='1';
wait for 100 ns;
sel<='0';
wait;
end process;
END;
SIMULATION RESULT:
138
RESULT:
Thus a four bit synchronous Johnson/Ring counter in VHDL and simulated and
139
BLOCK DIAGRAM:
RTL SCHEMATIC:
140
EX.NO:13 FOUR BIT MAGNITUDE COMPARATOR
05.12.2013
AIM:
To design a four bit magnitude comparator in VHDL and to simulate and synthesis the
same

THEORY:
The comparison of two numbers is an operator that determines one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers A and B and determines their relative magnitude. The outcome of the
comparator is specified by three binary variables that indicate whether A>B, A=B (or)
A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers, A and B, is displayed in a combinational circuit by an
output binary variable that we designate by the symbol (A=B).This binary variable is equal to 1 if
the
input numbers, A and B, are equal, and to 0 otherwise. This dictates an AND operation of all
variables:
( ) ()()()()
To determine if A is greater than or less than B, we inspect the relative magnitudes of pairs
of
significant digits starting from the most significant position. If the two digits are equal, we compare
the next lower significant pair of digits. This comparison continues until a pair of unequal digits is
reached. If the corresponding digit of A is 1 and that of B is 0, we conclude that A>B. If the
corresponding digit of A is 0 and that of B is 1, we have that A<B. The sequential comparison can
be
by the two Boolean functions.
141
TEST BENCH:
LIBRARY ieee;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY comp_4b_tb IS
END comp_4b_tb;
ARCHITECTURE behavior OF comp_4b_tb IS
COMPONENT comp_4b
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
g : INOUT std_logic;
l : INOUT std_logic;
e : INOUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--BiDirs
signal g : std_logic;
signal l : std_logic;
signal e : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
uut: comp_4b PORT MAP (
a => a,
b => b,
g => g,
142
SOURCE CODE:
library IEEE;
entity comp_strm is
port(a,b:in std_logic_vector(3 downto 0);
g,l,e:inout std_logic);
end comp_strm;
architecture arch_comp_strm of comp_strm is
component and3g is
port(a,b,c:in std_logic;
z:out std_logic);
end component;
component and4g is
port(a,b,c,d:in std_logic;
z:out std_logic);
end component;
component and5g is
port(a,b,c,d,e:in std_logic;
z:out std_logic);
end component;
component or4g is
z:out std_logic);
end component;
signal s:std_logic_vector(11 downto 0);
begin
s(0)<=a(3) xnor b(3);
s(1)<=a(2) xnor b(2);
s(2)<=a(1) xnor b(1);
s(3)<=a(0) xnor b(0);
s(4)<=not b(3);
s(5)<=not b(2);
s(6)<=not b(1);
s(7)<=not b(0);
143
l => l,
e => e
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a<="1010";
b<="0000";
wait for 100 ns;
a<="1010";
b<="1010";
wait for 100 ns;
a<="0000";
b<="1010";
wait;
end process;
END;
SIMULATION RESULT:
144
s(8)<=a(3) and s(4);
a1:and4g port map(s(0),s(1),s(2),s(3),e);
a3:and3g port map(s(0),s(5),a(2),s(9));
a4:and4g port map(s(0),s(1),s(6),a(1),s(10));
a5:and5g port map(s(0),s(1),s(2),s(7),a(0),s(11));
o1:or4g port map(s(8),s(9),s(10),s(11),g);
l<= e nor g;
end arch_comp_strm ;
library IEEE;
entity and3g is
port(a,b,c:in std_logic;
z:out std_logic);
end and3g;
architecture arch_and3g of and3g is
begin
z<=a and b and c;
end arch_and3g;
library IEEE;
entity and4g is
z:out std_logic);
end and4g;
begin
z<=a and b and c and d;
end arch_and4g;
library IEEE;
entity and5g is
145
146
port(a,b,c,d,e:in std_logic;
z:out std_logic);
end and5g;
begin
z<=a and b and c and d and e;
end arch_and5g;
library IEEE;
entity or4g is
z:out std_logic);
end or4g;
architecture arch_or4g of or4g is
begin
z<=a or b or c or d;
end arch_or4g;
RESULT:
Thus a four bit magnitude comparator in VHDL and simulated and synthesized by
using XILINX ISE tool.
147
RTL SCHEMATIC:
TEST BENCH:
LIBRARY ieee;
ENTITY bram_tb IS
END bram_tb;
ARCHITECTURE behavior OF bram_tb IS
COMPONENT bram
PORT(
clk : IN std_logic;
addr : IN integer;
we : IN std_logic;
148
EX.NO:14 BLOCK RAM and FIFO
19.12.2013
AIM:
To design a block RAM and FIFO in VHDL and to simulate and synthesis the same by using
XILINX ISE tool.

THEORY:
BLOCK RAM:
In FPGAs a block RAM is a dedicated two port network containing several kilobits of
RAM. The FPGA contains several of these blocks .Inside of each logic blocks is a configurable
lookup table. It is normally used for logic functions but one can reconfigure it as a few bits of RAM.
One can combine several of them into a larger RAM. This is distributed RAM.
FIFO:
FIFO is an acronym for First In First Out which is an abstraction related to ways of organizing
and manipulation of data relative to time and prioritization. This expression describes the principle
of
a queue processing technique or servicing conflicting demands by ordering process by First-Come,
First-Served behaviour where the persons leave the queue in the order they arrived or waiting
ones
turn at a traffic control signal.
SOURCE CODE:
BLOCK RAM:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
entity bram is
port(clk:in std_logic;
149
d_in : IN std_logic_vector(7 downto 0);
d_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal addr : integer := 0;
signal we : std_logic := '0';
signal d_in : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal d_out : std_logic_vector(7 downto 0);
BEGIN
uut: bram PORT MAP (
clk => clk,
addr => addr,
we => we,
d_in => d_in,
d_out => d_out
);
-- Clock process definitions
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
150
addr:in integer;
we:in std_logic;
d_in:in std_logic_vector(7 downto 0);
d_out:out std_logic_vector(7 downto 0));
end bram;
architecture arch_bram of bram is
type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
signal r:ram_t:=(others=>(others=>'0'));
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we='1') then
r(addr)<=d_in;
else
d_out<=r(addr);
end if;
end if;
end process;
end arch_bram;
151
wait for 100 ns;
we<='1';
addr<=26;
d_in<="10001111";
wait for 100 ns;
we<='0';
addr<=26;
wait;
end process;
END;
SIMULATION RESULT:
152
153
RTL SCHEMATIC:
TEST BENCH:
LIBRARY ieee;
ENTITY fifo_tb IS
END fifo_tb;
ARCHITECTURE behavior OF fifo_tb IS
COMPONENT fifo
PORT(
clk : IN std_logic;
enr : IN std_logic;
enw : IN std_logic;
154
SOURCE CODE:
FIFO:
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo is
port(clk,enr,enw:in std_logic;
datain:in std_logic_vector(7 downto 0);
dataout:out std_logic_vector(7 downto 0);
empty,full:out std_logic);
end fifo;
architecture arch_fifo of fifo is
type memory_type is array(0 to 255)of std_logic_vector(7 downto 0);
signal memory:memory_type:=(others=> (others=>'0'));
signal readptr,writeptr:std_logic_vector(7 downto 0):="00000000";
begin
process(clk)
begin
if(clk'event and clk='1' and enr='1') then
dataout<=memory(conv_integer(readptr));
readptr<=readptr + '1';
end if;
if(clk'event and clk='1' and enw='1') then
memory(conv_integer(writeptr))<=datain;
writeptr<=writeptr +'1';
end if;
if(readptr="11111111") then
readptr<="00000000";
end if;
if(writeptr="11111111") then
full<='1';
writeptr<="00000000";
else
155
datain : IN std_logic_vector(7 downto 0);
dataout : OUT std_logic_vector(7 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
END COMPONENT;
--Inputs
signal enr : std_logic := '0';
signal enw : std_logic := '0';
signal datain : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal dataout : std_logic_vector(7 downto 0);
signal empty : std_logic;
signal full : std_logic;
BEGIN
uut: fifo PORT MAP (
clk => clk,
enr => enr,
enw => enw,
datain => datain,
dataout => dataout,
empty => empty,
full => full
);
-- Clock process definitions
begin
clk <= '0';
clk <= '1';
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full<='0';
end if;
if(writeptr="00000000") then
empty<='1';
else
empty<='0';
end if;
end process;
end arch_fifo;
157
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
enw<='1';
datain<="00001111";
wait for 100 ns;
datain<="00110011";
wait for 100 ns;
datain<="01010101";
wait for 100 ns;
enr<='1';
wait;
end process;
END;
SIMULATION RESULT:
158
RESULT:
Thus a block RAM and FIFO in VHDL and simulated and synthesized by using
XILINX ISE tool.
159
LOGIC DIAGRAM:
RTL SCHEMATIC:
160
EX.NO:15 TRUNCATED MULTIPLIER
19.12.2013
AIM:
To design a truncated multiplier in VHDL and to simulate and synthesis the same by using

THEORY:
MULTIPLICATION is one of the most area consuming arithmetic operations in high-

performance circuits. As a consequence many research works deal with low power design of high
speed multipliers. Multiplication involves two basic operations adding and shifting, performed
using
two kinds of multiplication algorithms, serial and parallel. Serial multiplication algorithms use
sequential circuits with feedbacks: inner products are sequentially produced and computed.
Parallel
multiplication algorithms often use combinational circuits and do not contain feedback
structures.
Multiplication of two bits produces an output which is twice that of the original bit. It is
usually needed to truncate the partial product bits to the required precision to reduce area cost.
Fixed-
width multipliers, a subset of truncated multipliers, compute only on most significant bits (MSBs)
of
the 2n-bit product for n n multiplication and use extra correction/compensation circuits to
reduce
truncation errors. Truncated multiplication can be used to significantly reduce the power
dissipation
for applications that do not require correctly-rounded results.
SOURCE CODE:
library IEEE;
entity trunc_mult is
Port(a,b:in STD_LOGIC_VECTOR (7 downto 0);
161
TEST BENCH:
LIBRARY ieee;
ENTITY trunc_mult_tb IS
END trunc_mult_tb;
ARCHITECTURE behavior OF trunc_mult_tb IS
COMPONENT trunc_mult
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
o : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal o : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
uut: trunc_mult PORT MAP (
a => a,
b => b,
o => o
);
-- Stimulus process
stim_proc: process
begin
162
o:inout STD_LOGIC_VECTOR (15 downto 0));
end trunc_mult;
architecture arch_trunc_mult of trunc_mult is
signal f:std_logic_vector(28 downto 1);
signal i,i1,i2,i3,i4,i5,i6:std_logic_vector(7 downto 0);
signal w1,w2,w3,w4,w5,w6:std_logic_vector(7 downto 0);
component eadder is
Port(a:in STD_LOGIC_VECTOR (7 downto 0);
b:in STD_LOGIC_VECTOR (7 downto 0);
c:in STD_LOGIC;
sum:inout STD_LOGIC_VECTOR (7 downto 0);
cin:inout STD_LOGIC);
end component;
component andg is
Port(a,b:in STD_LOGIC;
c:out STD_LOGIC);
end component;
begin
d1:andg port map(a(1),b(7),f(1));
163
wait for 100 ns;
a<="11111111";
b<="11111111";
wait;
end process;
END;
PIN ASSIGNMENT:
NET "a<7>" LOC="P101";
NET "a<6>" LOC="P91";
NET "a<5>" LOC="P39";
NET "a<4>" LOC="P72";
NET "a<3>" LOC="P71";
NET "a<2>" LOC="P58";
NET "a<1>" LOC="P57";
NET "a<0>" LOC="P54";
NET "b<7>" LOC="P204";
NET "b<6>" LOC="P194";
NET "b<5>" LOC="P184";
NET "b<4>" LOC="P183";
NET "b<3>" LOC="P175";
NET "b<2>" LOC="P174";
NET "b<1>" LOC="P169";
NET "b<0>" LOC="P159";
NET "o<15>" LOC="P133";
NET "o<14>" LOC="P129";
NET "o<13>" LOC="P127";
NET "o<12>" LOC="P122";
NET "o<11>" LOC="P119";
NET "o<10>" LOC="P115";
NET "o<9>" LOC="P112";
NET "o<8>" LOC="P108";
164
i(7)<='0';i(6)<='0';i(5)<='0';i(4)<='0';
i(3)<='0';i(2)<='0';i(1)<='0';i(0)<=f(1);
i1(7)<='0';i1(6)<='0';i1(5)<='0';i1(4)<='0';
i1(3)<='0';i1(2)<='0';i1(1)<=f(8);i1(0)<=f(2);
i2(7)<='0';i2(6)<='0';i2(5)<='0';i2(4)<='0';
i2(3)<='0';i2(2)<=f(14);i2(1)<=f(9);i2(0)<=f(3);
i3(7)<='0';i3(6)<='0';i3(5)<='0';i3(4)<='0';
i3(3)<=f(19);i3(2)<=f(15);i3(1)<=f(10);
i3(0)<=f(4);i4(7)<='0';i4(6)<='0';i4(5)<='0';
i4(4)<=f(23);i4(3)<=f(20);i4(2)<=f(16);
i4(1)<=f(1);i4(0)<=f(5);i5(7)<='0';
i5(6)<='0';i5(5)<=f(26);i5(4)<=f(24);
i5(3)<=f(21);i5(2)<=f(17);i5(1)<=f(12);
i5(0)<=f(6);i6(7)<='0';i6(6)<=f(28);
i6(5)<=f(27);i6(4)<=f(25);i6(3)<=f(22);
i6(2)<=f(18);i6(1)<=f(13);i6(0)<=f(7);
r1:eadder port map(i,i1,'0',w1);
r11:eadder port map(i2,w1,'0',w2);
165
NET "o<7>" LOC="P106";
NET "o<6>" LOC="P36";
NET "o<5>" LOC="P99";
NET "o<4>" LOC="P97";
NET "o<3>" LOC="P94";
NET "o<2>" LOC="P90";
NET "o<1>" LOC="P89";
NET "o<0>" LOC="P77";
SIMULATION RESULT:
166
o(7 downto 0)<="00000000";
o(15 downto 8)<=w6;
end arch_trunc_mult;
library IEEE;
entity andg is
Port (a,b:in STD_LOGIC;
c:out STD_LOGIC);
end andg;
architecture arch_andg of andg is
begin
c<=a and b;
end arch_andg;
library IEEE;
entity eadder is
Port(a:in STD_LOGIC_VECTOR (7 downto 0);
b:in STD_LOGIC_VECTOR (7 downto 0);
c:in STD_LOGIC;
sum:inout STD_LOGIC_VECTOR (7 downto 0);
cin:inout STD_LOGIC);
end eadder;
architecture arch_eadder of eadder is
signal s:std_logic_vector(6 downto 0);
component adder is
Port(x,y,z:in STD_LOGIC;
p,q:inout STD_LOGIC);
end component;
begin
d1: adder port map(a(0),b(0),c,sum(0),s(0));
d2: adder port map(a(1),b(1),s(0),sum(1),s(1));
167
168
d8: adder port map(a(7),b(7),s(6),sum(7),cin);
end arch_eadder;
library IEEE;
entity adder is
Port(x,y,z:in STD_LOGIC;
p,q:inout STD_LOGIC);
end adder;
architecture arch_adder of adder is
begin
p<= x xor y xor z;
q<= ((x xor y) and z) or (x and y);
end arch_adder;
RESULT:
Thus a truncated multiplier in VHDL and simulated and synthesized by using

170
169

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XILINX ISE TOOLS

(a) Design entry

Project Navigator Interface

Error Navigation to Source

Error Navigation to Answer Record

Steps to design a Project

1. Start Xilinx ISE Project Navigator.

14. Now its time to simulate the design

XILINX ISE TOOL

SOFTWARE & APPARATUS REQUIRED:

SOFTWARE & APPARATUS REQUIRED:

SOFTWARE & APPARATUS REQUIRED:

SOFTWARE & APPARATUS REQUIRED:

SOFTWARE & APPARATUS REQUIRED:

value of P is the signed product.

XILINX ISE TOOL

a)Selection by XOR gate:

SOFTWARE & APPARATUS REQUIRED:

b)Selection by 2:1 MUX:

a)Selection by XOR gate:

SOFTWARE & APPARATUS REQUIRED:

b)Selection by 2:1 MUX:

SOFTWARE & APPARATUS REQUIRED:

SOFTWARE & APPARATUS REQUIRED:

SOFTWARE & APPARATUS REQUIRED:

MULTIPLICATION is one of the most area consuming arithmetic operations in high-

Thus a truncated multiplier in VHDL and simulated and synthesized by using

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