You are on page 1of 19

Maha George Zia

Assistant Professor
Electrical Engineering Department
Outline
JFET Basic structure
Basic operation
JFET characteristic and parameters
JFET universal transfer characteristic
JFET Biasing
Q-point of self biased FET.
Comparison between BJT and FET
JFET Basic structure
Fig. 1(a) shows the basic structure of an n-channel JFET (junction field-effect
transistor).Wire leads are connected to each end of the n-channel; the drain is at
the upper end, and the source is at the lower end. Two p-type regions are
diffused in the n-type material to form a channel, and both p-type regions are
connected to the gate lead. For simplicity, the gate lead is shown connected to
only one of the p regions. A p-channel JFET is shown in Fig. 1(b). The symbols
of JFET types are shown in Fig.2.

Fig. 2 JFET Symbols


Fig.1 structure of JFET
Basic operation
The figure below shows dc bias voltages applied to an n-
channel device. VDD provides a drain-to-source voltage and
supplies current from drain to source. VGG sets the reverse-bias
voltage between the gate and the source, as shown.
The JFET is always operated with the gate-source pn junction
reverse-biased

The JFET operates as


a voltage-controlled,
constant-current device.
JFET characteristic and parameters
Consider the case when the gate-to-source voltage is zero
(VGS= 0 V). This is produced by shorting the gate to the source,
as in Fig.3(a) where both are grounded.

Fig.3 The drain characteristic curve of a JFET for VGS = 0V showing pinch-off
voltage Vp.
As VDD (and thus VDS) is increased from 0V, ID will increase
proportionally, as shown in the graph of Fig. 3(b) between points
A and B. In this area, the channel resistance is essentially
constant because the depletion region is not large enough to have
significant effect. This is called the ohmic region because VDS
and ID are related by Ohms law.

At point B in Fig.3 (b), the curve levels off and enters the active
region where ID becomes essentially constant. As VDS increases
from point B to point C, the reverse-bias voltage from gate to
drain (VGD) produces a depletion region large enough to offset
the increase in VDS, thus keeping ID relatively constant
Pinch-Off Voltage For VGS= 0 V, the value of VDS at which ID becomes
essentially constant (point B on the curve in Fig. 3(b)) is the pinch-off
voltage, VP. For a given JFET, VP has a fixed value. A continued increase in
VDS above the pinch-off voltage produces an almost constant drain current.
This value of drain current is IDSS (Drain to Source current with gate
Shorted) and is always specified on JFET datasheets.

IDSS is the maximum drain current that a specific JFET can


produce regardless of the external circuit, and it is always
specified for the condition, VGS = 0 V.

Breakdown As shown in the graph in Fig.3(b), breakdown occurs at point C.


when ID begins to increase very rapidly with any further increase in VDS.
Breakdown can result in irreversible damage to the device, so JFETs are
always operated below breakdown and within the active region (constant
current) (between points B and C on the graph).
Lets connect a bias voltage, VGG, from gate to source as shown in Fig. 4(a). As
VGS is set to increasingly more negative values by adjusting VGG, a family of
drain characteristic curves is produced, as shown in Fig.4 (b). Notice that ID
decreases as the magnitude of VGS is increased to larger negative values
because of the narrowing of the channel So VGS controls ID. Also notice that,
for each increase in VGS, the JFET reaches pinch-off (where constant current
begins) at values of VDS less than VP.

The value of VGS that makes ID approximately zero is the cutoff voltage, VGS(off)
The pinch-off voltage VP is the value of VDS at which the drain current
becomes constant and equal to IDSS and is always measured at VGS = 0 V.
VGS(off) and VP are always equal in magnitude but opposite
in sign.
Q1. For the JFET in Fig. below , VGS(off) = -4 V and IDSS = 12 mA
Determine the minimum value of VDD required to put the device in the
constant-current region of operation when VGS = 0 V.
JFET universal transfer characteristic
The range of VGS values from zero to VGS(off) controls the amount of drain
current. For an n-channel JFET, VGS(off) is negative, and for a p-channel JFET,
VGS(off) is positive. Because VGS does control ID, the relationship between these
two quantities is very important. Fig.4 is a general transfer characteristic curve
that illustrates graphically the relationship between VGS and ID. This curve is also
known as a transconductance curve
ID = 0 when VGS = VGS(cutoff)
ID = IDSS when VGS = 0 Fig.4

The forward transconductance


(transfer conductance = gfs), gm is:

unit is Siemens (S).


Also

Where gm0 is gfs measured at VGS = 0V

Q.2 A) For JFET, if IDSS = 9 mA and VGS(cutoff)= - 8V


(maximum). Using these values, determine the drain current
for VGS = 0V and -1V.
B) For JFET if IDSS = 3mA and VGS(cutoff)= - 6V
(maximum), gfs(max) = 5000 S. Using these values,
determine the forward transconductance for VGS = -4V and find ID
at this point.
Solution:
A) For VGS = 0V , ID = IDSS = 9 mA, and for VGS = -1V

B)
JFET Biasing
The purpose of biasing is to select the proper dc gate-to-source voltage to
establish a desired value of drain current and, thus, a proper Q-point
In self bias JFET must be operated such that the gate-source
junction is always reverse-biased. This condition requires a
negative VGS for an n-channel JFET and a positive VGS for a p-
channel JFET as shown
In fig.5 below

Fig.5
Self-biased JFETs (IS =ID in all FETs)
For the n-channel JFET in Fig.5(a), IS produces a voltage drop
across RS and makes the source positive with respect to ground.
Since IS=ID and VG= 0, then VS= IDRS. The gate-to-source voltage

Then

For p-channel, fig. 5 (b):


In the following example, the n-channel JFET in Fig. 5(a) is used for
illustration. The drain voltage with respect to ground is determined as follows

But VS = ID RS

Keep in mind that analysis of the p-channel JFET is the same except for
opposite-polarity voltages
Q3. Find VDS and VGS in Fig. below. For this JFET, the
parameter values such as gm, VGS(off), and IDSS are such that
a drain current (ID) of approximately 5 mA is produced.
Q-point of self biased FET
The basic approach to establishing a JFET bias point is to determine
ID for a desired value of VGS or vice versa. Then calculate the
required value of RS using:

Q4. Determine the value of RS required to self-bias a p-channel


JFET with datasheet values of IDSS =25 mA and VGS(off) = 15 V.
VGS is to be 5 V.
The transfer characteristic curve can be plotted using the equation
below, where IDSS and VGS are taken from the data sheet.

Consider the circuit with the transfer characteristic curve shown in


fig.6 (a) and (b) respectively:

Fig.6
To determine the Q-point of the circuit in Fig.6(a), a self-bias dc load line is
established on the graph in part (b) as follows.
First, calculate VGS when ID is zero.
This establishes a point at the origin on the graph (ID= 0, VGS= 0)

Next, calculate VGS when ID= IDSS. From the curve in Fig. 6(b), IDSS =10 mA

This establishes a second point on the graph


(ID=10 mA, VGS= -4.7V)

Now, with two points, the load line can be


drawn on the transfer characteristic curve
as shown in Figure. The point where the
load line intersects the transfer
characteristic curve is the Q-point of the
circuit as shown, where ID = 5.07 mA and
VGS = -2.3 V.
Comparison between BJT and FET

1. BJT is basically a current driven device, though FET is


considered as a voltage controlled device.
2. Terminals of BJT are known as emitter, collector and base,
whereas FET is made of gate, source and drain.
3. In most of the new applications, FETs are used than BJTs.
4. BJT uses both electrons and holes for conduction (bipolar
transistor), whereas FET uses only one of them and hence
referred to as unipolar transistors.
5. FETs are power efficient than BJTs.

You might also like