Differential Pair Layout

MOS DIFFERENTIAL PAIR AND GAIN STAGE

Circuit explanation section 3.8 & page:135 of Analog Integrated Circuit Design-
Tony Chan Carusone
http://www.te.kmutnb.ac.th/msn/225303report55.pdf

Section 4.2 (page 103) of Analog circuit design by Razavi.

1. In differential pair, The transistors Q1 and Q2 and are sized identically and
are biased with the same dc gate voltage.
2. For best simulation results, Both the transistors should be protected from all
the types of stresses, proximity effects and other LDE (Layout Dependent
Effects). In practical Scenario, we cannot avoid these effects. So in layout, we
need to add dummy transistors and dummy poly at OD (oxide definition)
break points.
3. Why matching? The absolute sizes and electrical parameters of integrated
circuit components can seldom be accurately determined. For best accuracy,
larger objects are made out of several unit-sized components connected
 together, and the boundary conditions around all objects should be
matched, even when this means adding extra unused components.
When integrated circuits are manufactured, PVT variations and and
mismatches (systematic & Random) will occur. So we need matching
(provide same environment in process, circuit connections).

See section 12.4 page 426 of Art of Analog Layout by Alan Hastings (second
edition).

4. common centroid layout: Any linear gradient in electrical properties across

the chip effects two or more devices equally. This is achieved by dividing each
device into smaller equal-sized units (fingers), and arranging the units so that
all devices have the same mean position (centroid).
5. The interconnect wires which carrying the drain currents (ID1, ID2) should
be having similar electrical characteristics (same metal layer, same width,
 same length. These are achieved by using the following layout techniques.
Do Shielding techniques if any aggressor/noisy nets coming near to the
matched nets. (id1 , id2 nets in case of differential pair>>either parallel
shielding or Co-axial shielding depends upon the frequency of
victim/aggressor/area availability/parasitic capacitance
1. symmetric layout
2.Balance Layout
3.Physical Compensation techniques.

Symmetrical Layout
In many analog, RF, or sensitive digital designs, two halves of a particular
design are electrically equivalent, and it is desired that each half perform
identically. A differential amplifier is an example where the circuits function is to
distinguish signal differences between two input signals.

A very simple technique to achieve almost perfectly symmetrical layout is to

use one cell twice. The minor differences between the two cells should be
implemented on top of the cell. Figure 1. Illustrates this approach. Advantages and
disadvantages of this approach are as follows:
Symmetry is guaranteed and easy to implement
The benefits of cell-based layout come into play. Changes to both halves are done
in one cell.
The cell planning is a little more complicated because the symmetry point has to
be understood and the layout implemented with this in mind.
There may be some area or routing overhead because of the symmetry, but
polygons along the line of symmetry are usually shared.
Balanced Layout
We define a balanced layout as a design that has symmetrical performance as a
result of intelligent connectivity within its structure as well as a symmetrical layout.
Often, implementing balanced circuitry has the following effects:
Reduced power in a world where designers are dealing with the large power
Consumption of todays chips and are trying to avoid needing fans to cool chips
down to the optimum working temperature.
Timing symmetry. This is especially important in analog and RF designs, where
the timing of each switching device is critical.
Definition of more detailed connectivity models to accurately capture the
balanced nature of the design. Analog design technique is the father of balanced
layout, where a very old method called balanced devices is applied to IC design.

Physical Compensation
Physical compensation is the term we use to describe the concept of layout
symmetry applied to signals. Signal symmetry is achieved by designing two signals
to have the same length, width, load, and coupling environment. Designing signal
and clock paths to meet flip-flop setup and hold times is an exercise in matching
signal paths to the clock path. In some cases where the timing margins are
extremely small, physical compensation techniques are used. Synchronous DRAMs
(SDRAM) are an application where input setup and hold times are required to be
very well defined. Circuit performance needs to be guaranteed under all voltage,
temperature, and process conditions. Physical compensation is appropriate in this
case. As we have mentioned, signal symmetry can be achieved by mirroring many
Structural features of the signals among the group to be compensated. This should
Include numbers of vias; matching of routing layer(s) and the length of the sections
in each layer; and shielding each signal equally. A short list of steps to implement
physical compensation among a group of signals might be as follows:

1. Route signals as you would any other signal, and reserve space for length
Compensation and shielding lines. Route all lines using a single width of line.
2. Determine the longest line among the group to be compensated and increase
the length of all other signals to match. Serpentining signal lines is appropriate as
long as adequate shielding is maintained.
3. If different routing layers are used, match the length of interconnect on each
layer for each signal. It is not necessary to place the different layer routing in the
same place along the line, but it is important to use the same number of vias within
each signal. Match the relative transistor loading or fanout for each line. This means
that the ratio of the size of the transistor load relative to the driver should be the
same for every line. Additional transistor loads should be added to the appropriate
signal to match the fanout ratio.
4. Run layout extraction tools to verify the results and adjust the layout if necessary.

References:
1. Art of Analog Layout by Alan Hastings (second edition).
2. Analog Integrated Circuit Design-Tony Chan Carusone
3. Design of Analog CMOS Integrated circuit Behzad Razavi