Putting Signal Integrity in its Place

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Modied by on 12-Nov-2013

In the past, tracks on a circuit board could be eectively considered as simple connections. Newer
logic families and faster clock speeds have undermined this basic assumption.

Fast signal edge rates in modern digital designs and the introduction of electromagnetic compliance
(EMC) regulations in many countries have been increasingly focusing the spotlight on signal integrity
issues in board design. Where fast rise times are present, signal reections along the board's tracks
need to be carefully monitored and controlled to ensure both the proper functioning of the circuit and
the minimization of electromagnetic interference (EMI). What's more, signal integrity issues need be
addressed early in the design process to avoid signicant rework of the nal board.

In high-speed digital designs, board tracks cannot be considered as simple interconnections. When
signal edge rates become comparable to the round trip delay time of the signal traveling along a
track, transmission line eects come into play that can signicantly alter a circuit's behavior. As a
rule-of-thumb, transmission line behavior becomes important in a digital circuit when the track
connection length in centimeters is greater than about eight-times the maximum rise (or fall) time in
nanoseconds of the signal.
For typical TTL circuits, which have rise times of around 3ns, transmission line eects really don't
come into play for track length under 24cm. However, the situation changes dramatically when we
look at designs which use some of the fast logic families available today.

Consider a design that uses Emitter-Coupled Logic (ECL) devices. Regardless of clock speed, these
devices can produce edge rise times of below one nanosecond. With these transients, track lengths of
as little as 8cm can produce transmission line eects. GaAs devices can exhibit problems on track
lengths less than 1cm!
As higher speed devices become more common, the need for distributed circuit analysis at the board
design stage becomes crucial. Where fast edge rates are present in a design, careful analysis of board
impedances is necessary to ensure proper termination of signal lines in order to minimize reections
and EMI, and to ensure signal integrity throughout the board.

Addressing Signal Integrity Early in the

Design Process
To help designers cope with the added complexity of transmission line analysis on a PCB, EDA
vendors are starting to include signal integrity analysis software as part of the standard board design
toolset. Unlike circuit simulation, signal integrity analysis does not concern itself with the functional
operation of the circuit - components are only modeled in terms of the I/O characteristics of their pins,
without regard to the component's function. Connections between component pins are modeled using
transmission line techniques that factor in the length of the trace, the characteristic impedance of the
trace at the stimulus frequency, and the termination characteristics at each end of the connection.
Traditionally, signal integrity tools are designed to work with a fully routed board. While this gives
accurate results because each individual trace length is known, it does mean that the analysis is
performed quite late in the design cycle. One of the most common signal integrity issues that arises is
signal degradation resulting from reection caused by mismatched impedances of the pins at either
end of a connection. The solution to this problem usually involves the addition of a termination
resistor or R/C network to match the termination impedances and minimize reections.

Figure 1. Output from a reection simulation for a problem net on a board.

Figure 2. Same net after the insertion of an appropriate series termination resistor.

Using signal integrity simulation to uncover problems in a completed board design before any
prototyping is undertaken can reduce the number of prototype iterations needed to complete a
project. However, the addition of new components late in the board design stage can be a major
problem, particularly on dense boards. The rework involved can be time consuming, partially negating
the time saved in the prototype/test phase.
What's needed is the ability to detect and rectify potential signal integrity problems, particularly
impedance mismatches, early in the design cycle.

Pre-layout Signal Integrity Analysis

Altium Designer includes a signal integrity simulator that can be accessed during both the design
capture and board layout phases of a design. This allows both pre- and post-layout signal integrity
analysis to be performed.
The signal integrity simulator models the behavior of the routed board by using the calculated
characteristic impedance of the traces combined with I/O buer macro-model information as input for
the simulations. The simulator is based on a Fast Reection and Crosstalk Simulator, which produces
very accurate simulations using industry-proven algorithms.
Because both design capture and board-level design environments use an integrated component
library system that links schematic symbols to relevant PCB footprints, SPICE simulation models and
signal integrity macro-models, signal integrity analysis can be run at the schematic capture stage
prior to the creation of the board design. When no board design is present, the system allows you set
up the physical characteristics of the design, such as the desired characteristic trace impedance, from
within the signal integrity simulator.
At this stage of the design process the signal integrity simulator cannot determine the actual length
of particular connections, so it uses a user-denable average connection length to make its
transmission line calculations.
By carefully choosing this default length to reect the dimensions of the intended board, you can gain
a fairly accurate picture of the likely signal integrity performance of the design. Potential reection
problems can then be identied and any additional termination components added to the schematic
before proceeding to board layout.
As signal integrity issues become more prominent in board design, the ability to detect and correct
potential problems before committing to board layout is becoming essential to minimize rework time
and keep up with increasing "time-to-market" pressures.

Integrating Signal Integrity into Board Design Flows

Picking up potential signal integrity problems before layout is important in minimizing overall design
time, but it needs to be used in conjunction with post-layout analysis to make sure a board is ready
for manufacture. Extensive checking must be done on the nished board to ensure that the physical
layout has not introduced problems of its own. Because exact trace lengths are known and the
connection path, including vias and direction changes, can be analyzed in detail, post-layout signal
integrity analysis can be used to not only examine reections due to impedance mismatches, but also
the interaction, or crosstalk, between physically adjacent tracks.
Figure 4. Interference from an adjacent net - crosstalk.

To be truly useful to a board designer, however, post-layout signal integrity must be integrated into
the board design environment. If substantial time and eort is needed to export a design to a
separate analysis tool, then the cost of the analysis needs to be weighed against the benets. To
reduce the costs, signal integrity needs to made part of the natural design and verication process.
With respect to board layout, signal integrity analysis is integrated directly into the PCB editor as an
addition to the standard set of design rules. A board design can also be viewed and analyzed from
within the design capture environment. Designers can set threshold limits for parameters such as
undershoot and overshoot, edge slope, signal levels, and impedance values. Potential problem nets
are then highlighted as part of a normal design rule check. If a signal integrity problem is detected,
the designer can examine problem nets in more detail by performing reection or crosstalk analysis
to produce accurate waveform modeling of the problem nets.
In this way, setting up acceptable signal integrity parameters becomes part of the normal board
denition process, much the same as dening minimum track clearances and widths. Identifying
signal integrity problems caused by the physical layout then becomes a natural part of performing a
complete design rule check on the nished board. This level of integration is necessary if the full
benets oered by signal integrity analysis are to be eectively and practically realized.

Realizing the Benets

In designs that include high-speed logic elements, thorough signal integrity checking both before and
after board layout can save signicant time and money in the overall product design cycle. The
benets are twofold. Firstly, taking proper account of transmission line eects in signal traces at both
the design capture and the board layout stage can increase circuit reliability by minimizing distortion
along the signal path, thereby minimizing potential signal "glitches". Tracking down such problems
after a board has been prototyped can be dicult and time consuming, and problems not detected
during design could lead to low yield rates during construction.
A second benet is that correct termination of high-speed signal lines not only ensures correct
operation of the circuit, but it also minimizes the potential for board-level EMI and susceptibility
problems. Apart from the direct costs associated with EMC testing and certication, the time and
money costs of redesigning products that fail initial testing can be devastating, particularly if the
failure results from poor board design.
Time-to-market pressures, stricter EMC rules and tighter circuit requirements are increasing the
demands on board designers, making signal integrity analysis a necessity rather than a luxury in
board design today. To fully realize the benets that signal integrity analysis has to oer, however,
the tools used and the process of performing the analysis must be fully integrated with and in line
with existing board design ows, rather than being seen as separate additional stages to the current
board design process.
Source URL: http://techdocs.altium.com/display/ASIAE/Putting+Signal+Integrity+in+its+Place