Structural and electrical characterization of the 4H-
SiC based Junction Field Effect Transistor (JFET)
K. Shili1, M. Ben Karoui1,2, R. Gharbi1 and M.
Fathallah1
1
. Laboratoire des Semi-conducteurs et Dispositifs
Electroniques. C3S. Ecole Suprieure des Sciences et
Techniques de Tunis. 05 Av. Taha Hussein 1008
Montfleury . Tunis, TUNISIA.
2
. Centre des Recherches et des Technologies de l'Energie.
Technopole Borj Cdria B.P N95- 2050 Hammam Lif-
Tunisia.
e-mail : rached.gharbi@esstt.rnu.tn
shilikhaoula18@yahoo.fr
Abstract The main focus of our work is the characterization
and structural study of 4H-silicon carbide (SiC) normally-off
vertical junction field effect transistor (JFET). We will determine
the experimental static Ids-Vds characteristics under temperature
variation. In order to achieve a better description of SiC and
metal interface properties, many interesting parameters related
to the material and to the device performance have been obtained
from these measurements. Simulation has been used to correlate
obtained results to physical parameters. When the temperature
increases to 300C, the RDS(ON) increase to 700 m and the
saturation drain source current decreases up to 14A.
KeywordsJFET-SiC; 4H-SiC; normally-off; electrical
behavior.
I. INTRODUCTION
Junction Field Effect Transistor (JFET) has been widely
studied by many research groups from the end of the90s, and
nowadays has entered the commercial market.
This is a semiconductor device based on a control of the drain
current with the aid of an electric field generated by a bias
between gate and source [1]. It is based on the conductive
channel of which the conductance can be modulated by means
of applied voltage to the gate. This type of semiconductor
component has the advantage to involve only one type of
carriers in the current conduction process and for this is said
unipolar transistor. For N-channel JFET, it is electrons.
The normally-off trench SiC power JFETs are compatible
with standard gate drive circuitry and feature a positive
U.S. Government work not protected by U.S. copyright
S. Ferrero3
3
.Politecnico di Torino, c.so Duca Degli Abruzzi,
10129 Torino (ITALY).
temperature coefficient for paralleling use. The voltage-
controlled devices also have a low Rds(on)max, low gate charge
and low intrinsic capacitance [2]. In this paper we studied a
JFET SiC transistor. Characterization of SiC JFET is an
essential step in order to know static and dynamic behavior.
This knowledge will enable us to establish a model to simulate
operation in a converter.
II. DEVICE STRUCTURE
SemiSouths SiC VJFET (normally on or normally off) is
based on a patented vertical-channel, trench structure, as given
in Figure 1.
This structure with a ntype channel can be described as
follows:
- Substrate: a semiconductor layer n+ doped.
- Channel: n type layer located above the substrate.
- p+ - n junction: fabricated in the channel by means of ion
implantation.
- Gate contact (ohmic): formed on the p+ - n junction.
- Source and gate contact (both ohmic): formed on the n type
region, or channel.
The structure is built in a 4H-SiC epitaxial wafer with a 12m-
thick layer doped to n- = 7*1015 cm-3 capped by a heavily doped
n+ > 1*1019 cm-3 layer. Deep trenches are dry-etched to
facilitate implementation of the gating structure and blocking
junction through three-step aluminum (Al) implantation.
 For a JFET, the channel conductance GDS is defined as:
, this parameter represents the slope of the IDS

VDS curve for a prefixed value of VGS.

In the linear region we have for the GDS the following
expression (if we choose for VDS a negligible value in
comparison to the other two terms VGS and VP):

2. . 1 (2)

In this way, the JFET behaves like a resistor, with a resistance

that can be controlled by varying VGS.
In a similar way we obtain another important parameter, the
IDS
transconductance Gm. It can be expressed as , and
Fig.1: Cross-section of SemiSouths VJFET [3]. VGS V
DS
represents the slope of the transcharacteristic curve IDS VGS,
As seen in Fig. 1, the gate regions are created on the side walls for a prefixed value of VDS. In the linear region, Gm increases
of the trenches, resulting in 2.1 m vertical junction gates and a with VDS.
designed channel opening of 0.55 m. Furthermore, the p+
body regions are created under the trenches providing the p+-n- From the ohmic zone of the current-voltage characteristics of
blocking junction at the depth of ~ 1m from the trench the JFET, we can deduce the resistance in on state who
bottom, yielding a blocking layer thickness of 9.4 m when the represents the slope of the current of drain with weak VDS.
p+ implantation tail is considered. In addition, shallow, high From definition this resistance is given by [5]:
concentration p++ regions are created at the trench bottoms to
facilitate the p-type gate contacts, which are placed at the
(3)
centers of the trench bottoms. As seen in Fig. 1, the n-type ,
source contacts are placed at the top surfaces of the mesa, and
the drain contact on the substrate. The side walls of the - Saturation region.
trenches are passivated by a thermal oxide and silicon nitride, In the saturation region, the dependence of the drain current
and the trenches are filled with a planarizing polyimide. The IDS on VGS can be written as:
source contacts are connected by a metal overlay, which runs
over the polyimide. In addition, the gate fingers are connected
to a large bonding pad at one side of the device. . 1 (4)

III. CHARACTERIZATION OF JFET-SIC IDS is not depending on VDS, but the current increases for
decreasing |VGS|.

A. I V characteristics of a n channel JFET.

1 IDS VDS characteristic.

We observed two regions in the IDS VDS plot (fig.2). This

implies that we have an expression relating IDS and VDS for
each region, depending on the VDS values.
- Linear region:
The IDS VDS characteristic can be writing as [4]: Fig.2: The linear and saturation region in the IDS VDS plot.

For this reason, the conductance GDS is equal to zero in the

2. . (1)
saturation region, in the ideal case.
The transconductance can be expressed as:
Where VP is the pinch off voltage and IDSSAT is the drain
source saturation current.
2. . 1 (5)

In the saturation region Gm is equal to GDS in the linear region.

It is worth to note that in the real IDS vs. VDS characteristics, IDS
shows a slight increase in the saturation zone, even if

2
VDS>VDSSAT (voltage drain-source in saturation). This implies
that in the saturation zone GDS is not equal to zero, as in the
ideal case discussed above.

2 IGS VGS Characteristic.

The current IGS flows across the p+ n junction formed by the

p+ gate region and the n doped channel.
If this junction is reverse biased (VGS<0 if the depleted
channel is ntype), the IGS represents the junction reverse
current, equals to zero in the ideal case.
In the real case, if we apply a VGS value higher than the
junction breakdown voltage VBD, we can have an uncontrolled
current flowing across the junction.
Fig.4: The curves VDS and IDS as function of time.
If the breakdown is irreversible, the JFET cannot be anymore
utilized, due to the failure of the gate channel p+ n junction.
17
Experiment
16
B. Electrical characterization of JFET-SiC 15 Simulation Vg=3V
14
13
12
The studied transistor has an RDS(ON) of 300m, enables 11
extremely fast switching with no tail current up to its
IDS(A)
10
9
maximum operating temperature of 175C. He is offer a 8 Vg=2V
blocking voltage of 1200V and exhibit temperature- 7
6
independent switching behavior. We performed an electrical 5
characterization by using the circuit shown in Fig.3 (a). The 4
3
used spice model [6, 7] was illustrated in Fig.3 (b). The JFET 2
can be modeled as a gate controlled current source, with two 1
0 Vg=1V
pn junctions across gate-source and gate-drain, respectively. -1
The ohmic resistances of the drain and source regions of the 0 1 2 3 4 5 6

JFET are modeled by the two linear resistors RD and RS. VDS (V)
Charge storage in the JFET occurs in the two gate junctions.
Since neither gate junction normally is forward-biased, there is Fig.5: Experimental and simulation curves of drain current IDS
no minority-carrier storage, so the capacitances involved are versus drain voltage VDS at different VGS (noted in fig.:Vg) of
just those due to the ionic space charge in the depletion the studied Normally-off JFET-SiC.
regions [8]. This charge storage is modeled by two capacitors
CGD and CGS, respectively. TABLE I. EXTRACTED PARAMETERS OF STUDIED SIC JFET
Parameter Description Value
Vp Pinch-off voltage -2V
Transconductance Parameter 4 AV-2
Channel-length Modulation 0.03 V-1
Parameter
IS Gate Junction 0.310-3A
Saturation Current
RD Drain Ohmic Resistance 0.01
RS Source Ohmic Resistance 0.01
CGS Zero-Bias G-S Junction 670pF
Capacitance
(a) (b)
CGD Zero-Bias G-D Junction 97pF
Fig.3: (a) circuit used for the static characterization, (b) Capacitance
Equivalent schematic model of the normally-off SiC JFET. CDS Zero-Bias D-S Junction 103pF
Capacitance

The figure 4 shows the characteristics VDS and IDS as function Table I summarizes the most important parameters of SiC
of time, and from these curves we have been extracted point JFET used in simulation and some of them are extracted based
by point the static characteristics (VDS, IDS) given in figure 5 on the device characterization.
with the simulation curves at different VGS.

3
 IV. CONCLUSION
0,8
RDS(ON),Drain-Source On-resistance (ohm)

Drain-Source On-resistance
0,7 RDS(ON) = f(T) In this work, we have presented the experimental
characterizations and a correlation of results with the
0,6
simulation parameters obtained from developed JFET model.
The study of 1200V-4H-SiC normally-off Trench silicon
0,5 carbide JFET showed possibility of his use in power system
applications. The device has demonstrated a specific on-
0,4 resistance of 300m at 25C who increases to 700 m at
300C. The IDSSAT decreases with increasing temperature. This
0,3 JFET is a strong candidate for the future development of SiC-
0 50 100 150 200 250 300
based unipolar power switching devices.
Temperature T(C)

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Fig.6: Drain-Source On-resistance versus temperature
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Fig. 7: Variation of saturation current versus temperature.