A computer consists of a set of components or modules of three basic types that communicate with each other.

1. Processor
2. Memory
3. I/O

In effect, a computer is a network of basic modules, thus there must be paths for connecting the modules. This is called the interconnection structure.

Memory typically a memory module will consist of N words of equal length. Each word is assigned a unique numerical address. A word of data can be read from or written
into the memory. The nature of the operation is indicated by read and write control signals. The location for the operation is specified by an address.
I/O module from an internal point of view, I/O is functionally similar to memory. There are two operations, read and write. Further, an I/O module may control more than
one external device. We can refer to each of the interfaces to an external device as a port and give each a unique address. In addition, there are external data paths for the
input and output of data with an external device. Finally an I/O module may be able to send interrupt signals to the processor.
Processor the processor reads in instructions and data, writes out data after processing and uses control signals to control the overall operation of the system. It also
receives interrupt signals.

Q: identify and list types of exchanges

The above list defines the data to be exchanged. The interconnection structure must support the following types of transistors

Memory to processor
Processor to memory
I/O to processor
Processor to I/O
I/O to or from memory

Many different interconnection structures have been tried, but by far the most common has been the bus and various multiple bus structures.

Q: Elemetns of bus design

Elements of Bus Design

Bus Types

Bus lines can be separated into two generic types, dedicated and multiplexed.
Dedicated bus line - is permanently assigned either to one function or to a physical subset of
computer components

Methods of Arbitration

More than one module may need control of the bus. Because only one unit at a time can
successfully transmit over the bus, some method of arbitration is needed. These roughly fall into
two categories, centralized or distributed
In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is
responsible for allocating time on the bus.
In a distributed scheme, there is no central controller, each module contains access control
logic and the modules act together to share the bus
With both approaches, the purpose is to designate one device, either the processor or an I/O
module, as master

Timing

Timing refers to the way in which events are coordinated on the bus
 Buses use either synchronous timing or asynchronous timing
Synchronous timing the occurrence of events on the bus is determine by a clock. The bus
includes a clock line which transmits a regular sequence of alternating 1s and 0s of equal
duration. All the devices on the bus can read the clock line, and all events start at the beginning
of a clock cycle
Asynchronous timing the occurrence of one event on a bus follows and depends on the
occurrence of a previous event. In the simple read example, the processor places address and
status signals on the bus. After pausing for these signals to stabilize, it issues a read command,
indicating the presence of valid address and control signals. The appropriate memory decodes
the address and responds by placing the data on the data line. Once the data lines have
stabilized, the memory module asserts the acknowledged line to signal the processor that the
data is available. Once the master has read the data from the data lines, it de-asserts the read
signal. This causes the memory module to drop the data and acknowledge lines. Finally, once
the acknowledge line is dropped, the master removes the address information.

Synchronous timing is simpler to implement and test, however it is less flexible than asynchronous
timing. With Asynchronous timing, a mixture of slow and fast devices, using older and newer
technology can share a bus.
Data Transfer Type
A bus supports various data transfer types. All buses support both write (master to slave) and read
(slave to master) transfers as well as a number of other transfer types including

Read-modify-write operation
Read-after-write operation
Block data transfer
Write (multiplexed) operation
Read (multiplexed) operation

Posted on Wednesday, February 8, 2012 5:41 AM UNISA COS 2621 Computer Organization | Back to top
Biased exponent:
Biasing is done because exponents have to be signed values in order to be able to represent both tiny and huge values, but two's complement, the usual representation for
signed values, would make comparison harder.

To solve this problem the exponent is biased before being stored, by adjusting its value to put it within an unsigned range suitable for comparison.

By arranging the fields so that the sign bit is in the most significant bit position, the biased exponent in the middle, then the mantissa in the least significant bits, the resulting
value will be ordered properly, whether it's interpreted as a floating point or integer value. This allows high speed comparisons of floating point numbers using fixed point
hardware.

To calculate the bias for an arbitrarily sized floating point number apply the formula 2 k1 1 where k is the number of bits in the exponent. [1]

When interpreting the floating-point number, the bias is subtracted to retrieve the actual exponent.

For a single-precision number, an exponent in the range 126 .. +127 is biased by adding 127 to exponent to get a value in the range 1 .. 254 (0 and 255 have special
meanings).

For a double-precision number, an exponent in the range 1022 .. +1023 is biased by adding 1023 to exponent to get a value in the range 1 .. 2046 (0 and 2047 have
special meanings).

For a quad-precision number, an exponent in the range 16382 .. +16383 is biased by adding 16383 to exponent to get a value in the range 1 .. 32766 (0 and 32767
have special meanings).