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4/14/2017 Parity

Parity
Feb92014



Parity

UsingAssign

1//
2//DesignName:parity_using_assign
3//FileName:parity_using_assign.v
4//Function:Parityusingassign
5//Coder:DeepakKumarTala
6//
7moduleparity_using_assign(
8data_in,//8bitdatain
9parity_out//1bitparityout
10);
11outputparity_out;
12input[7:0]data_in;
13
14wireparity_out;
15
16assignparity_out=(data_in[0]^data_in[1])^
17(data_in[2]^data_in[3])^
18(data_in[4]^data_in[5])^
19(data_in[6]^data_in[7]);
20
21endmodule

Youcoulddownloadfileparity_using_assign.vhere


UsingfunctionI

1//
2//DesignName:parity_using_function
3//FileName:parity_using_function.v
4//Function:Parityusingfunction
5//Coder:DeepakKumarTala
6//
7moduleparity_using_function(
8data_in,//8bitdatain
9parity_out//1bitparityout
10);
11outputparity_out;
12input[7:0]data_in;
13

http://www.asicworld.com/examples/verilog/parity.html 1/3
4/14/2017 Parity

14wireparity_out;
15
16functionparity;
17input[31:0]data;
18begin
19parity=(data_in[0]^data_in[1])^
20(data_in[2]^data_in[3])^
21(data_in[4]^data_in[5])^
22(data_in[6]^data_in[7]);
23end
24endfunction
25
26
27assignparity_out=parity(data_in);
28
29endmodule

Youcoulddownloadfileparity_using_function.vhere

UsingfunctionII

1//
2//DesignName:parity_using_function2
3//FileName:parity_using_function2.v
4//Function:Parityusingfunction
5//Coder:DeepakKumarTala
6//
7moduleparity_using_function2(
8data_in,//8bitdatain
9parity_out//1bitparityout
10);
11outputparity_out;
12input[7:0]data_in;
13
14wireparity_out;
15functionparity;
16input[31:0]data;
17integeri;
18begin
19parity=0;
20for(i=0;i<32;i=i+1)begin
21parity=parity^data[i];
22end
23end
24endfunction
25
26always@(data_in)
27begin
28parity_out=parity(data_in);
29end
30
31endmodule

Youcoulddownloadfileparity_using_function2.vhere

AndthePracticalOne
http://www.asicworld.com/examples/verilog/parity.html 2/3
4/14/2017 Parity

1//
2//DesignName:parity_using_bitwise
3//FileName:parity_using_bitwise.v
4//Function:Parityusingbitwisexor
5//Coder:DeepakKumarTala
6//
7moduleparity_using_bitwise(
8data_in,//8bitdatain
9parity_out//1bitparityout
10);
11outputparity_out;
12input[7:0]data_in;
13
14assignparity_out=^data_in;
15
16endmodule

Youcoulddownloadfileparity_using_bitwise.vhere




Copyright19982014
DeepakKumarTalaAllrightsreserved
DoyouhaveanyComment?mailmeat:deepak@asicworld.com

http://www.asicworld.com/examples/verilog/parity.html 3/3

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