Unit-V BJT & FET AMPLIFIERS PDF

Dept of EEE VFSTR University
UNIT- 5
SINGLE STAGE AMPLIFIERS
BJT amplifiers: Small signal low frequency transistor amplifier circuits: h
parameter representation of a transistor, Analysis of single stage transistor
amplifier using h-parameters: voltage gain, current gain, Input impedance and
Output impedance. Comparison of transistor configurations in terms of Ai , Ri , Av,
Ro, Frequency response of Common Emitter Amplifier, Common Base Amplifier,
Common Collector Amplifier.
FET amplifiers: FET amplifiers at low frequencies, CS / CD / CG configurations
at low frequencies, Gain Band Width Product.
OBJECTIVES
To familiarize the students about the amplifiers (BJT & FET).
To familiarize the students about the frequency response.
OUTCOMES
After the completion of the unit the students will be able to
Connect amplifier.
Calcuate band width product.
TEXTBOOKS
1. J.Millman and CC Halkias, Electronic Devices and Circuits, 2nd ed.,
Tata McGraw-Hill, , 2007.
2. S.Salivahanan, Electronic Devices and Circuits , 5th ed.,Tata McGraw-
Hill, 2010.
REFERENCES
1. R.L.Boylestad and Lovis Nashelsky, Electronic Devices and Circuits
Theory, 10th ed., Pearson Education, 2010.
2. N.N.Bhargava, Basic Electronics and Linear Circuits, 1st ed.,Tata
McGraw-Hill, 2009.
Single Stage Amplifiers Page 1 K Rachananjali
TWO PORT NETWORK:
A transistor can be treated as a 2-port network as shown below.
Fig1: Two port network
Actually a 2 port network requires 4 terminals, 2 for input port and 2 for
output port; but transistor has only 3 terminals. So by taking a terminal common to
input and output ports we can consider a transistor as a 2 port network.
In 2 port network shown in Fig1,
v1=input port voltage
i1=input port current
v2=output port voltage
i2=output port current
Out of these 4 variables 2 are considered as independent variables and the

remaining two are considered as dependent variables.
Case1: Open circuit impedance or z-parameters: -
v1 and v2 as dependent parameters
& i1 and i2 as independent parameters.
v1=z11i1+z12i2
v2=z21i1+z22i2
v
z11= 1 i 2 =0 open circuit input impedance ()
i1

v
z12= 1 i 1 =0 open circuit reverse transfer impedance ()
i2
v
z21= 2 i 2 =0 open circuit forward transfer impedance ()
i1
v
z22= 2 i 1 =0 open circuit output impedance ()
i2
These are called open circuit impedance parameters or z-parameters as they

are calculated under open circuit condition and all are representing voltage to
current ratios.
Case2: Short circuit admittance or y-parameters:
i1, i2 as dependent parameters
& v1, v2 as independent parameters.
i1=y11v1+y12v2
i2=y21v1+y22v2
i
y11= 1 v 2 =0 short circuit input admittance ( )
v1
i
y12= 1 v 1 =0 short circuit transfer reverse admittance ( )
v2
i
y21= 2 v 2 =0 short circuit transfer forward admittance ( )
v1
i
y22= 2 v 1 =0 short circuit output admittance ( )
v2
These are called short circuit admittance parameters or y-parameters

as they are calculated under short circuit condition and all are representing current
to voltage ratios.

Case3: hybrid or h-parameters: -
v1, i2 as dependent parameters
& i1, v2 as independent parameters
v1=h11i1+h12v2
i2=h21i1+h22v2
v
h11= 1 v 2 =0 short circuit input impedance ()= hi
i1
v
h12= 1 i 1 =0 open circuit reverse voltage gain=hr (no units)
v2
i
h21= 2 V 2 =0 short circuit forward current gain=hf (no units)
i1
i2
h22= i 1 =0 open circuit output admittance=h0 ( )
V2
These are not having same units, so called as hybrid or h-parameters.
Like wise
Case 4, Case 5etc.
In transistor characteristics (studied in unit-3), we learn that input current

and output voltage are independent parameters. So we can use h-parameters model
to represent transistor.
How to represent a transistor using h-parameter model? :
h-parameter equations are
v1=hii1+hrv2 --------------> (1)
i2=hfi1+hov2 ----------------> (2)
Each term in equation (1) represents a voltage so we have to form a

mesh such that whose Kirchhoffs voltage law (KVL) should be equation (1). Each
term in equation (2) represents a current so we have to form a node such that
whose Kirchhoffs current law (KCL) should be equation (2).

Step: -1
Consider a two port network as shown in Fig 2(a)
Fig 2(a) : Initiation to represent transistor in h-parameter model
Step:-2
+ 1 2

2 1
Fig 2(b): h- parameter model of transistor
hrv2 and hfi1 cannot be directly related to input port and output ports respectively.
So, indicated as dependent sources in Fig 2(b).
How the h-parameter model help in analysis? :
nothing but linear (

BJT (Bipolar junction transistor) is a non-linear device. h-parameter model is
linear equations), so by considering a transistors
characteristics piece wise linearly, we can find voltage gain, current gain, power
gain, input impedance, output impedance, ..etc.
Analysis of single stage transistor amplifier using h-parameters:
Consider h-parameter equivalent circuit of general amplifier.

i1 hi i2
<
RS + +
v iL
1 2
vS ~ 2
1 _ ZL
-
Fig 3: transistor amplifier h-parameter representation

Current gain( ): It is defined as the ratio of load current (iL) to input current
(i1). So
iL i 2
AI = = (from Fig3, iL=-i2)
i1 i1
From equation (2)
i2=hfi1+hov2
=hfi1+hoiL.zL ( from Fig3, v2=iLzL)
= hfi1- hoi2.zL ( iL=-i2 from Fig3)
i2 (1+hozL)=hfi1
i2 hf
=> =
i1 1+h o z L
i 2 h f
Ai = =
i1 1 +h o z L
Input impedance (zi): It is defined as the ratio of input voltage (v1) to input
current(i1).
v1
zi =
i1
From equation (1)
v1=hii1+hrv2
=hii1+hr (-i2zL) ( v2=iL zL =-i2zL)
2
= hii1+hr.i1.AI.zL =
1
=i1 (hi + AI zL )

zi = 1 =hi + AI zL
1
Voltage gain (AV): It is defined as the ratio of output voltage (v0) to input voltage
(vi).
vo v2 i 2 .z L
AV= = =
vi v1 i 1 .z i
zL
AV = AI.
zi

Output admittance (yo): It is defined as the ratio of output current (i2) to output
voltage (v2)with input supply voltage vs = 0.
i
yo = 2 v S =0
v2
From equation (2) i2=hfi1+hov2
Dividing the equation with v2

i2 h f i1 h0v2
= +
v2 v2 v2
i2 h f i1
=> = + ho ---------------> (3)
v2 v2
i1
Now let us find when vS=0
v2
Applying KVL to the input loop with vS=0 of Fig 3
(RS + hi) i1 + hrv2=0

i1
=> = ------------------> (4)
v2 +
Substitute (4) in (3)

i2
v S =0 = + ho
v2 +

yo = h o -
+
Output impedance (zo):
It is defined as the ratio of output voltage (v2) to output current (i2) with input
supply voltage vs = 0.
v
z0 = 2 v S =0
i2
1
z0 =
yo

Overall voltage gain (AvS): - It is defined as the ratio of output voltage (vo ) to
supply voltage(vs ).
vo v2
A vs = =
vs vs
v2 v1
= .
v1 vs
v1
=AV. -------------------> (5)
vs
Considering input circuit of Fig 3

Rs R1 RS
+
vs ~ + = vs ~ v1 R i
v1 -
Ri -
Ri
v 1 = vs .
R i +R S
v1 Ri
=> = ----------------------> (6)
vs R i +R S
Substituting equation (6) in equation (5)

Ri
A vs =AV.
R i +R S
If RS=0, Avs =Av as vs =v1
Overall current gain (AIS): - It is defined as the ratio of output current (iL) to
supply current (is).
Consider input circuit of Fig 3 and applying source transformation
i1
iS RS Ri
2
AIS = =


2 1
= . ---------------------> (7)
1
From the above circuit,

RS
i1=iS. -------------------> (8)
R S +R i
Substituting (8) in (7)

RS
AIS=AI.
R S +R i
Power gain (AP): -It is defined as the ratio of output power (P0) to input power (Pi).
Po i L .v L i 2 v2
AP = = = .
Pi i 1 .v 1 i1 v1
AP=AI.AV
What is an amplifier?
An amplifier is a device which strengthens the amplitude of the input signal and
there should not be any change in its shape and frequency.
Transistor configurations:
A. Common base: Base is common for input and output ports.
Emitter as input & collector as output.
B. Common emitter: Emitter is common for input and output ports.
Base as input & collector as output.

C. Common collector: Collector is common for input and output ports.
Base as input & emitter as output.
Common Emitter amplifier:
vcc
R1 Rc
CC
vo
A CC
RL
RS
R2
RE CE
vS ~
B
Common Emitter amplifier
Description:
For a.c analysis, capacitors are treated as short circuit as they offer very small
resistance i.e.emitter will be connected to ground, so acts common to input and
output.
vcc , R1, R2 and RE forms the self biasing to fix the operating point in the
active region.
CCs are coupling capacitors to block d.c signals from one stage to next
stage so as not to change the operating point of next stages.
CE is a bypass capacitor to provide low reactance path to a.c signals and
hence avoids negative feedback for a.c signals.
For proper operation of the circuit, polarities of the capacitors must be
connected correctly. The curve bar, which indicates negative terminal must always
be connected to a d,c voltage less than or equal to the d.c level of positive terminal,
straight bar.
Operation:
During the positive half cycle of input, A is positive with respect to B. Due to this
two voltages a.c and d.c will be added, increasing the forward bias of the emitter-
base junction. This increases base current. As collector current is times base
current, ic also increases.
From figure4,
vo = vcc c - ic R c
So vo decreases.
Therefore, we get a negative half-cycle of output for positive half-cycle

of input.
During the negative half-cycle of input B is positive with respect to A.

So a.c will be subtracted from d.c and net forward bias of emitter-base junction
will be decreased. This decreases the base current and hence collector current.
From figure, we can write
vo = vcc c - ic R c
So vo increases. Therefore, we get a positive half-cycle of output for negative

half-cycle of input.
The phase difference between

input and output is 180.
Fig 5: Input and output waveforms of Common Emitter amplifier

Common base amplifier:

C1 C2
RS
RE RC RL vo
vS ~ vEE vcc
Fig 6: Common Base Amplifier
Description :
Base is grounded so common for both input and output. Vcc, vEE , RC and RE
are used to bias the transistor in active region. C1 and C2 are coupling capacitors
used to pass only a.c signals and block d.c signals from one stage to the next stage
to maintain stable operating point.
Operation: During the positive half-cycle of input, a.c is subtracted from

d.c and net forward bias on emitter-base junction will be reduced, so base current
will be reduced and hence collector current will be reduced.
From fig6, vo = vcc c - ic R c So vo will be increased.
During the negative half-cycle of input a.c is added to d.c as they are in the
same polarity and net forward bias on emitter-base junction will be increased, so
base current will be increased and hence collector current will be increased.
As vo = vcc c - ic R c , vo will be decreased. Therefore output is in phase with

the input.
Fig7: Input and output waveforms of Common Base amplifier

Common Collector amplifier:
During the a.c analysis d.c supplies must be made 0. i.e. vcc
becomes zero i.e. ground i.e. collector is common.

vcc
R1
C1
C2
R2
vS ~ RE RL
Fig 8: Common Collector Amplifier
Description : Vcc, R1, R2, and RE form the biasing for transistor to operate in the
active region. C1 and C2 are coupling capacitors used to couple only a.c signals
from one stage to the next stage.
Operation: During the positive half-cycle of input, net forward bias on emitter-
bias junction will be increased, so base current and hence collector current will be
increased.
From figure8, vo =ie ic So output will be increased.
During the negative half cycle of input, net forward bias on emitter-base
junction will be decreased, so base current and hence collector current will be
decreased and output also will be decreased. So output is in phase with the input.
Fig9: Input and output waveforms of Common Base amplifier

Analysis of transistor using h-parameter model:
Guidelines to draw the equivalent circuit:
1. Replace the BJT by its h-parameter equivalent.

2. Make d.c sources to zero.
3. Replace the capacitors by short circuit.
Analysis problems:
1. Find Ai,R i , Av, Avs , AIS and Ro for the following circuit. Given hje =1.1k,
hoe=25A/v, hfe =50 and hre =2.510-7
vCC = 12v
RC
1K 1K
0.1f
v0
0.1f cc
50=
cc 1.2K
1K
2K
0.1f RL
vin ~ 470 Ce
Based on the guidelines draw the equivalent circuit.
B ib C
hie
Equivalent of BJT hre vcc +- hoe
hfe ib
This is a.c analysis, so vcc =0 =>ground.

So RC should be connected from collector to ground. All capacitors are
short circuited so RL should be connected from collector to ground. Emitter
is directly connected to ground. At the input R1 is connected from base to

ground ( vcc =0=ground) and R2 is connected from base to ground and vss in
series with RS is also connected from base to ground.
ib B hie C
+ +
1K 1.2K +
RS +_ hre vce
R L vo
R2 R1 v1 hfe ib hoe v2
RC _
vS ~
_ E _
Ri Ri
From the above figure,

Effective load RL =RC||RL
=1K||1.2K
=545.45
IL h fe
Current gain (AI) = =
I1 1+h oe R L
50
=
1+2510 6 545.45
= -49.32
Vi
Input resistance (R i ) = = hie + AI hre RL
Ii
= 1.1K + (-49.32)(2.510-4)545.45
= 1.093K
V0 R L RS
Voltage gain (AV) = = AI.
V1 Ri
545.45
= -49.32 vs Ri
1093 ~
=-24.6
Ri = R1||R2||Ri = 1K||2K||1.093K
=0.414K
Vo R i
Overall voltage gain AvS = = AV.
VS R i +R S
0.414K
= -24.6
0.414K+1K
= -7.2

Negative sign in AV and AvS indicates 180 phase difference between input and
output.
h fe h re
Output admittance yo = hoe -
h ie +R s
Where Rs =RS||R1||R2 = 1K||1K||2K = 0.4K

502.510 4
yo= 2510-6 -
1100 +0.4K
= 16.6710-6 A/V
1 1
Output resistance Ro= = = 59.98K
0 16.6710 6
iL iL iC ib
Overall current gain AIS= =
iS iC ib iS
R C R S ||R 1 ||R 2
= (-AI)
R C +R L R S ||R 1 ||R 2 +R i
=0.45(49.32) 0.2679 = 5.946
2. For the common collector configuration, the transistor parameters are

hic=1.2K, hfc =-101, hrc =1 and hoc=25A/V. calculate Ri, Ai, AV, Avs , Ro
for the circuit.
vcc = 12v
R1
10K
CC
R S 1K 10f
R2 ovo
100K 5K
vS ~ 20K

The h- parameters equivalent circuit is

i1 B hic ie E iL
+
RS
R2 R1
1K
100K
hrc vec +_ hoc 5K 20K
10K hfc ib
vS ~ vo
C _
Ri Ri Ro R0
iL h fc
Current gain AI= =
i1 1+h oc R L
Where RL = effective load=5K||20K
= 4K
(101)
AI = = 91.8
1+2510 6 410 3
Vi
Input resistance R i =
Ii
=hic +AI.hrc.RL =1.2K+91.814K =368.4K

V0 R L
Voltage gain (AV) = =AI.
V1 Ri
4K
= 91.8 = 0.996
368.4K
Vo Vo V1
Overall voltage gain Avs = = .
VS V1 VS
V1
=AV.
VS
RS
+ R i
v1 R
Avs =AV.
vs ~ R i +R S
i
_ 8.87K
= 0.996
8.87K+1K
=0.895

Ri =R1||R2||Ri
=10K||100K||368.4K
=8.87K
h fc h rc
Output admittance (yo) = hoc -
R S +h ic
101 (1)
=2510-6
1k+1.2K
=25 106 - 4590910-6

A
=-4588410-6 v
i ie ib
Overall Current gain (AIS) = L . .
ie ib iS
5K R S ||R 1 ||R 2
= (-AI).
5K+20K R S ||R 1 ||R 2 +R i
= (-0.2) (91.8) (2.43910-3)
=0.04478
1
Output resistance (Ro)= =21.79

Ro =Ro||RE = 21.79||5k = 21.69
3. For the common base circuit, the transistor parameters are hib=22, hfb=-
0.98, hob=0.49A/V, hrb =2.910-4. Calculate the values of R i , Ro, AI, AV,
Avs , Ro and Ro .
CC CC
R S 1K RE RC RL
5K 10K 12K
vS ~ vE
vCC
The h-parameters equivalent circuit is
i1 E hie C iL
R S 1K +
5K hrb vcb _ ho b R C RL
hfb ie 10K 12K
vS ~
B
Effective load (RL ) = RC||RL

=10K||12K
=5.45K
iL h fc
(1.) Current gain (AI) = =
i1 1+h ob R L
0.98
=
1+0.4910 6 5.4510 3
=0.977
Vi
(2.) Input resistance (R i ) = = hib +AI.hrb.RL
Ii
= 22+0.9772.910-45.45103
=23.544
V0 R L
(3.) Voltage gain (AV) = =AI.
V1 Ri
5.45K
= 0.977
23.544
=226
Vo Vo V1
Overall voltage gain (Avs ) = Avs = = .
VS V1 VS
V1
RS =AV.
VS
+
v1 R
vs ~ i R i
Avs =AV.
_ R i +R S
Ri = R1||RE = 23.54||5K
= 23.42

23.42
Avs =226
23.42+1K
=5.17
h fb h rb
Output admittance ( yo ) = hob -
R S +h ib
0.982.910 4
=0.4910-6 -
1K+22
=0.768 ( )
1 1
Output resistance Ro= = = 1.3M
yo 0.768
R0 =Ro||RC = 1.3M||10k= 9.923k

iL i iC ie
Overall current gain (AIS) = =L . .
iS iC ie iS
iL R C 10K
= = = -0.45
iC R C +R L 10K+12K
iC
=-AI=-0.977
ie
ie R S ||R E 1K||5K
= =
iS R S ||R E +R i 1K||5K+23.54
0.833K
=
0.833K+23.54
=0.9725
AIS = (-0.45) (-0.977) (0.9725)
= 0.4725
Comparison of CB, CE, and CC amplifiers:
S.No Parameter Common base Common emitter Common collector

1. Input Resistance Low High Very high
2. Output Resistance Very high Moderate Low
3. Voltage gain High High Low
4. Current gain Low High High
5. Power gain Moderate Very High Moderate
Frequency response of an amplifier:
The performance of an amplifier can be judged by its frequency response

curve. This curve describes the amount of gain offered by the amplifier for various
frequencies. Frequency is taken on x-axis and gain is taken on y-axis. Logarithmic
scale is taken for frequencies to cover maximum range, so gain should be
converted to decibels as follows.
AV = 20log10 AV , AI = log10 AI
and AP = log10 AP
Typical frequency response curve is

AV db
AVmax

2
0 f
fL fH
B.W
Fig 10: Frequency response of an amplifier
AV max is maximum voltage gain of the amplifier fL and fH are lower and upper
cutoff frequencies respectively.
1
Cutoff frequency is defined as the frequency at which gain is times the
2
maximum gain.
Bandwidth is defined as the range of frequencies over which gain is greater than
1
or equal to times the maximum gain.
2
Bandwidth=fH - fL

Frequency response of common emitter amplifier:
vCC
3.3K R1 RC
1.2K CC
vo
CC 10f
1K 10f RL
RS
100f 1K
R2
vs 6.8K Ce
1mv ~ 1K R e
Fig 11: A typical Common Emitter Amplifier
If we connect the circuit as shown above and take the output for various input
Vo
VS
frequencies and then compute gain in dB as 20log10 .

S.NO f VO
20
1
2
.
.
Now if we plot frequencies Vs gain, it will be like this.

gain
0 f
Fig 12: Typical frequency of an amplifier

From the plot, we can say that gain at low frequencies is increasing, gain at high
frequencies is decreasing and gain at mid frequencies is constant as frequency is
increasing. The reasons for gain fall at low and high frequencies is as follows.
Reasons to get low gain at low frequencies:

1
1. Coupling capacitors: We know that XC = . At low frequencies,
2f C
coupling capacitors offer very large reactance, which results in maximum
drop across coupling capacitor and in turn reduces the amount of coupling
from one stage to the next stage. So final output decreases and hence gain
decreases. As frequency is increasing, capacitive reactance decreases, drop
decreases, coupling increases, vo increases and hence gain increases.
2. Bypass capacitors: At low frequencies, bypass capacitors also offer high
reactance and cannot stop negative feedback offered by Re.
As frequency is increasing, XC decreases, and bypasses the feedback signals
and hence gain increases.
Practically the value of bypass capacitors is very high so the effect of bypass
capacitor is low compared to coupling capacitor.
Reasons to get low gain at high frequencies:
1. : As frequency is increasing, decreases so output voltage and hence gain

decreases.
2. Shunt capacitors:
Emitter, Base and collector are conducting materials separated by

forbidden gap, which acts like dielectric and hence behave like capacitors called
shunt capacitors.
E B C C
B
E
3. Stray capacitors: When two conducting wires separated by air then it

results in capacitance, called stray capacitance.
RS
~ vS
Ri
CStray
At high frequencies, capacitive reactance XC stray will be small and most

of the signal will be passed through cstray compared to input of the amplifier and
hence gain decreases.
Corollary: For common base and common collector amplifiers coupling

capacitors cause diminished gain at low frequencies and , shunt capacitances &
stray capacitances cause diminished gain at high frequencies.
FET amplifiers: From the operation of FETs studied in second unit, we know 2
d.c supplies vgs and Vds are required. So current is due to both vgs and vds . From
the super position theorem,
a) id due to voltage source vgs is

id 1 = g m Vgs
Where gm is transconductance.
b) id due to voltage source vds is
V ds
id 2 =
rd
V ds
id = id 1 + id 2 = g m Vgs + --------------> (9)
rd
Constructing the equation (9) as a 2 port network results in small signal
model of FET as shown below.
g d
+ vds +
rd
vgs g m vgs rd vds
- _
s
Fig 13: Small signal model of FET

Analysis of common source FET amplifier using small signal model:
(a) Fixed bias: -

vDD
RD
cc
cc
)|
RG v0
vi
vgs
Fig 14: FET amplifier with fixed bias
To draw the a.c equivalent circuit
(i.) FET should be replaced by small signal model

(ii.) Capacitors should be short circuited.
(iii.) d.c sources should be made zeros.
So a.c equivalent circuit is
I1 G id D
+
vi ~ RG g m vgs rd RD
vgs v0
_ S
zi Z0 Z0
Fig 15: AC equivalent of FET amplifier with fixed bias
Vi
(i) Input impedance (zi ) = = RG
Ii
(ii)Output impedance (zo ) = rd

and zo = rd||RD
(iii) Voltage gain
vo = -id R D
Applying KVL to output loop
id R D + rd (id -g m vgs ) = 0
g m V gs r d g m V gs r d
=>id = = vo = RD
r d +R D r d +R D
Vo g m R D r d
AV= =
V gs r d +R D
Self-bias:
vDD
RD
c2
c1 v0
vi
RG
RS cS
Fig 16: FET amplifier with self bias
a.c equivalent circuit is
v0
+
vi RG vgs g m vgs rd RD
Zi z0 z0
Fig 17: AC equivalent of FET amplifier with self bias

z0
Input impedance (zi ) = RG
Output impedance (zo ) =rd and zo =RD||rd

g m R D r d
Voltage gain= = g m (rd||RD)
r d +R D
(b) Self bias with un bypassed RS:
vDD
RD
v0
vi
c1
RG
RS
Fig 18: FET amplifier with self bias and un bypassed Rs
S
o
id D
G +
vgs g m vgs rd RD
vi RG - v0
RS
Zi z0 z0
Fig 19: AC equivalent of FET amplifier with self bias and un bypassed Rs

Input impedance (zi ) = RG

Output impedance (zo ) = V i =0
0
Applying KVLs at output and input
vo = (id-g m vgs )rd + id R S ----------------> (10)
vi = vgs + id R S => 0= vgs + id R S
=> vgs = -id R S ----------------> (11)
vo = id g m id R S rd + id R S
=id rd + g m R S rd + R S

zo = = rd + RS+ g m R S rd

zo =zo||RD.

Voltage gain (AV) =

Applying KVL vo = id.RD -------------> (12)
idRD+(id- g m Vgs)rd+idRS=0
idRD+ id g m Vi id R S rd+idRS=0
gm v i rd
id=
R D +r d +g m R S r d +R S
gm vi rd

id=
R D +r d +R S +R S
g m v i r d R D
vo=-idRD= ( =g m rd )
R D +r d +R S 1+
vo g m r d R D
AV = =
vi R D +r d +R S 1+
Note: - With un bypassed RS gain will be reduced due to negative feedback

provided by RS.

Common drain amplifier: -
vDD
vi
RG v0
c2
RS
Fig 20: FET Common drain amplifier
vi G D
+
vgs g m vgs rd
_ S
RG
ov
0
RS
R0
Ri
Fig 21: AC equivalent of FET Common drain amplifier
Input Resistance (Ri)= RG

Output resistance Ro= V i =0


G S v0
+ id
RG g m vgs rd RS
vi
i d g m vS
_ D
id
Ri R0 R0
Fig 22: Modified AC equivalent of FET Common drain amplifier
Applying KVL to outer loop
-Vi +Vgs +Vo=0
Condition for Ro is vi=0 so
-O+Vgs+vo=0 => Vgs=-vo---------------> (13)
From the circuit,
vo=idRS=-(id-gmVgs)rd
=-(id+gmvo)rd ( from (13))
vo(1+gmrd) = - idrd
vo r d
=
id 1+g m r d
r d
=
1+
r d
As 1 Ro= V i =0 =

r d 1
= =-
1+g m r d gm
1
Ro =Ro || RS = ||RS
gm
vo
Voltage gain (AV) =
vi

vo=idRS -------------------> (14)
Applying KVL to output loop
idRS+(id-gmVgs)rd=0 -----------------> (15)
Applying KVL for outer loop
-vi+Vgs+ idRS=0
=>Vgs= vi- idRS---------------> (16)
idRS+(id-gm(vi- idRS))rd=0
id(RS+rd+gmrdRS)=gmvird
v i
=>id= ----------------> (17)
R S +r d +R S

v i
vo= .RS
R S +r d +R S
vo R S
AV= =
vi R S +r d +R S
As rdRS(1+)
R S
AV= =
R S (1+) 1+
Note 1: CD amplifiers voltage gain is slightly less than unity.
Note 2: Positive sign of AV indicates 0 phase shift between input and output.

Common gate amplifier: -
c1 S D c2
RS RD
vi v0
vDD
Fig 23: Common gate amplifier
Equivalent circuit
i+g m vgs
rd
S i id D
+ +
vi RS g m vgs
v0
RD
G _
-
Zi Zi
Fig 24: AC equivalent of FET Common gate amplifier

vi
Input impedance (zi) =
i
From figure 24,
Current flowing through rd(Ird)=i+gmVgs
=> i = ird- gmVgs

v i iR D
= - gmVgs
rd
=
v i iR D
rd

- gm(-vi) ( Vgs=-vi)

vi 1
i= 1 + = + gmvi = vi +
rd
R
1+ D
vi rd r d +R D
=> zi= = 1 =
i +g m 1+g m r d
rd
zi =zi||RS

Output impedance (zo) = V i =0

i.e impedance seen from output port when input port is short circuited.
zo=rd||RD

Voltage gain (AV) =

vo= -iDRD
vi=-Vgs
Applying KVL to outer loop
-vi+(i+gmVgs)rd+iRD=0
As Vgs=-vi, we get
-vi+(i-gmvi)rd+iRD=0
=> i(rD+RD)=vi(1+gmrd)
v i (1+g m r d )
=> i=
r d +R D
v i R D (1+g m r d )
=> vo= iRD=
r d +R D
vo R D (1+g m r d )
=> AV= =
vi r d +R D

Gain bandwidth product (GBWP):
This quantity allows circuit designers to determine the maximum gain that can be
extracted from the device for a given frequency and vice-versa.
IF GBWP of an amplifier is 10KHz, it means that the gain of the device falls
to unity at 10KHz.
GBWP is constant for a given amplifier. That is even we add some more
circuitry to increase (or decrease) gain then bandwidth will be decreased (or
increased) and GBWP is constant.
For transistors, the current gain bandwidth product is known as fT or transition

frequency. It is calculated from the low frequency current gain under specified test
conditions.

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Dept of EEE VFSTR University

TWO PORT NETWORK:

A transistor can be treated as a 2-port network as shown below.

Fig1: Two port network

In 2 port network shown in Fig1,

v1=input port voltage

i1=input port current

v2=output port voltage

i2=output port current

Out of these 4 variables 2 are considered as independent variables and the

Case1: Open circuit impedance or z-parameters: -

v1 and v2 as dependent parameters

& i1 and i2 as independent parameters.

Single Stage Amplifiers Page 2 K Rachananjali

These are called open circuit impedance parameters or z-parameters as they

Case2: Short circuit admittance or y-parameters:

i1, i2 as dependent parameters

& v1, v2 as independent parameters.

These are called short circuit admittance parameters or y-parameters

Single Stage Amplifiers Page 3 K Rachananjali

Case3: hybrid or h-parameters: -

v1, i2 as dependent parameters

& i1, v2 as independent parameters

These are not having same units, so called as hybrid or h-parameters.

Case 4, Case 5etc.

In transistor characteristics (studied in unit-3), we learn that input current

How to represent a transistor using h-parameter model? :

h-parameter equations are

v1=hii1+hrv2 --------------> (1)

i2=hfi1+hov2 ----------------> (2)

Each term in equation (1) represents a voltage so we have to form a

Single Stage Amplifiers Page 4 K Rachananjali

Consider a two port network as shown in Fig 2(a)

Fig 2(a) : Initiation to represent transistor in h-parameter model

Fig 2(b): h- parameter model of transistor

How the h-parameter model help in analysis? :

nothing but linear (

Analysis of single stage transistor amplifier using h-parameters:

Consider h-parameter equivalent circuit of general amplifier.

Fig 3: transistor amplifier h-parameter representation

Single Stage Amplifiers Page 5 K Rachananjali

Single Stage Amplifiers Page 6 K Rachananjali

From equation (2) i2=hfi1+hov2

Dividing the equation with v2

Applying KVL to the input loop with vS=0 of Fig 3

(RS + hi) i1 + hrv2=0

Substitute (4) in (3)

Output impedance (zo):

Single Stage Amplifiers Page 7 K Rachananjali

Considering input circuit of Fig 3

Substituting equation (6) in equation (5)

If RS=0, Avs =Av as vs =v1

Single Stage Amplifiers Page 8 K Rachananjali

From the above circuit,

Substituting (8) in (7)

A. Common base: Base is common for input and output ports.

Emitter as input & collector as output.

B. Common emitter: Emitter is common for input and output ports.

Base as input & collector as output.

Single Stage Amplifiers Page 9 K Rachananjali

C. Common collector: Collector is common for input and output ports.

Base as input & emitter as output.

Common Emitter amplifier: