Increasing Resolution in Three-Phase Cascaded
Asymmetrical Multilevel Inverters
Sumit K. Chattopadhyay Student Member IEEE,
Department of Electrical Engineering
Indian Institute of Technology Kharagpur
Kharagpur, INDIA
E-mail: sumitkc1981@gmail.com
AbstractAsymmetrical cascaded multilevel converters can
generate more number of voltage levels for the same number of
switching devices. Binary, Trinary and other different forms are
available in literature. This paper has critically investigated such
converters from the point of view of optimizing the number of
levels. A mathematical tool to analyze the possibility of any
asymmetric ratio for various three-phase topological
configurations is developed. This mathematical tool is then used
to find the ratio of asymmetry for three phase cascaded
multilevel converters. Operation of the identified asymmetry is
validated through simulation and experimental results using
laboratory prototype.
KeywordsAsymmetric multilevel inverter, Three phase multilevel
inverter topology, power quality, efficient converter topology.
I. INTRODUCTION
Multilevel converters (MLC) are presently one of the most
researched topics in the field of power electronic converters.
MLCs are presently used in many different applications with
different purposes. Initially MLCs were used for building
high-voltage power converters with medium voltage power
semiconductors. This is also utilized for maintaining power
quality at input side as well as output side. Out of all the MLC
topologies, cascaded H-bridge MLC (CHBMLC) was the
earliest known (first observed in an US patent in 1978) and
most popular topology due to its simple structure and easy
control requirement. All other topologies are having floating
capacitors. This makes the control of those topologies difficult
due to capacitor balancing problem except the hybrid
topological concept introduced in [1] and [2]. Modular
multilevel converter (MMC) was first introduced in [3]. This
topology also suffers from circulating current problem and
fully depends on close loop control with extremely
complicated control algorithm to balance the sub-module
capacitors. Moreover, the arm inductances are not of very
small value compare to the per unit impedance. As a result,
practical application of MMC is limited to HVDC application
[4] only, because it shares a common dc-bus for all phases:
this is a significant advantage for HVDC transmission.
As a result of above disadvantages, CHBMLCs is taking a
leading role in industry. Another significant advantage of
CHBMLCs and their hybrid topologies is that, they can be
developed with asymmetric structure to increase the number
of levels/resolution of output voltage. A major disadvantage of
k,(((
Chandan Chakraborty Senior Member IEEE
Department of Electrical Engineering
Indian Institute of Technology Kharagpur
Kharagpur, INDIA
E-mail: chakraborty@ieee.org
these asymmetric CHBMLC structure is that, the various
power sources will be different amount of power. Power
distribution ratio (PDR) of these different sources is highly
non linear function of modulation index: as shown in [5] for
trinary voltage ratio. Auxiliary sources (sources with lower
voltage) are fed by higher voltage source through high-
frequency-link. About 19% of total power is handled by high
frequency link at near unity modulation index. High frequency
link (HFL) power handling is a major contributor for losses in
this converter. To reduce the high frequency link power, the
same converter topology is operated in a fixed modulation
index in [5], where the HFL will be handling about 2% of the
total power. This is achieved at the cost of slightly reducing
the number of levels (from 27 levels at phase voltage to
23levels at phase voltage) and placing a buck converter
between the DC power supply and the inverter. This converter
handles the entire input power at higher frequency. To solve
these issues, a complex control of non linear model predictive
controller is used in [6]. This control mechanism is used to
superpose a reasonable common mode voltage in all phases,
such that, the lower voltage cells will not contribute any active
power. This is also at the cost of compromising with the
number of levels and complex algorithm. Such algorithms are
not possible to implement beyond trinary asymmetry in case
of three phase CHBMLC [7]. Algorithms suggested in [6] and
[7] can be absolutely difficult to utilize with fastest
computational tools, if the number of H-bridges cascaded per
phase exceeds two. So, the number of levels at the output
phase voltage cannot exceed 9 levels (considering two
cascaded bridges per phase with trinary asymmetry) at any
condition. Hence the above mentioned works will not be able
to operate the inverter in staircase modulation in large range of
modulation index. This paper investigates the possibilities to
enhance the output voltage resolution with higher overall
efficiency by introducing very low capacity auxiliary power
sources, which will allow the inverter to be operated by stair
case modulation in much larger range with much higher
resolution.
The paper is organized as follows: Section-I has briefly
reviewed the limitations of prospective high-resolution
multilevel inverters reported in literature. Section-II
investigates the possible asymmetric configurations for three
phase inverters. A mathematical tool is developed to find the
possibility to use a given ratio of asymmetry in three-phase

inverters. Section-III illustrates the simulation results. Section-
IV provides the hardware results. Finally, section-V concludes
the work.
II. ASYMMETRIC RATIO FOR THREE PHASE
MULTILEVEL INVERTERS

The work is targeted to achieve highest number of levels in

line-to-line voltage with given number of switches and with
minimum rating of isolated sources and its components. It is
required maintain fixed and highest possible asymmetry
between the bridges to achieve the goal. Most of the
asymmetric CHBMLCs reported in literature use binary (1: 2 :
: 2N) or trinary (1: 3 : : 3N) ratio for the dc buses of the
cascaded bridges. If the ratio of asymmetry goes beyond
trinary, the converter will not be able to generate few levels in
between its maximum and minimum output voltage. This is
given as:

(1)
Fig. 2. Space vectors of sector 1 for an N level inverter

Where, Lu is the number of levels not possible achieve, m is (2)

the number of H-bridges cascaded with a ratio of asymmetry r.
This is illustrated in Fig.1 with 2 cascaded cells maintaining a

ratio of asymmetry given by r.

If a three phase MLI is considered, a given space vector can

be generated by several alternate ways. This is possible by

adding a common mode voltage to each phase. Number of
alternative ways to generate a space vector is reduced if the r

is increased. When r exceeds 3, there will be some

unreachable levels between maximum and minimum output
voltage of the converter. The source of these unreachable
levels is non-uniform distance between adjacent levels, as
illustrated in Fig. 1. If a three phase MLI is considered, a (3)
given space vector can be generated by several alternate ways.
This is possible by adding a common mode voltage to each

phase. Number of alternative ways to generate a space vector
(4)
is reduced if r is increased. When r is 4, there will be some
unachievable space vectors observed at the periphery of the

space vector plane. This will effectively reduce the number of

levels of an asymmetric multilevel inverter. If the ratio is

increased further then there will be unachievable space vectors
at the internal part of the space vector plane along with the (5)
unachievable vectors at the periphery of the space vector
plane. Equation (2) helps to analyze the number of possible
ways achieve a given space vector within sector-1. So, this

will also valid for other sectors too.
The matrix in equation (2) is an upper-triangular square (6)
matrix. Each non zero elements in this matrix indicates the
number of ways to achieve a given space-vector.
Location of the space-vectors in this matrix is clearly indicated
in Fig. 2. The matrixes, and in equation (2) is
expanded in equation (4), (5) and (6) respectively. In these
equations, - , - , and - , are the number of ways to
achieve nth level in the phase voltage. This may be noted that,
Fig. 1. Location of unreachable levels of a CHBMLC with two cascaded cells since identical phases are considered in this work, equation (7)
maintaining a voltage ratio a:b= r will be satisfied:

(7)



Vector locus
corresponding to unity
modulation index
Vector locus
corresponding to 0.9
modulation index
Fig. 3. Ways to generate space-vectors of sector 1 for three-phase asymmetric CHBMLC with 3 H-bridges per phase with 16:4:1 ratio
(proposed asymmetry).
These sets of equations may be used to analyze the feasibility
of any given asymmetry.
Equation 2 is used to find the number of ways to generate a
space vector for different asymmetric configurations. Using
this equation, it is found that, 1:4::4N is the highest known
ratio to generate a space-vectors with uniform distance
between adjacent space-vectors within its boundary. The
boundary will not be perfect hexagon (as in case of trinary
asymmetry) Fig. 3. indicate the ways to generate the space-
vectors of sector-1 for a three phase CHBMLC with three H-
bridges per phase with a ratio 16:4:1. This is found by using
equation (2). This shows that, there is less redundancy in
higher modulation index, and higher redundancy to achieve a
space-vector in case of lower modulation index. Power
handled by lower voltage cells can be optimized by using
these redundancies. However, if it is targeted to operate the
inverter in staircase-modulation, it is essential to operate the
inverter with higher number of levels. With lower modulation
index, numbers of levels in output voltages are reduced: this
increases the output filter requirement compare to higher
modulation index. With that reasonable increase of output
filter capacity, it is reasonable to operate the inverter in higher
modulation index such that the rotating vector locus will pass
through discontinuous zones at the periphery as shown in Fig.
3. How the THD is changed with increasing the number of
levels is illustrated in Fig. 4. It is possible to observe minimum
THD in output voltage (below 1.25%) when it is operating
with 77 levels at the output voltage, as the locus of the rotating
vector is just touching the boundary of space vector plane, up-

Possible ways to
achieve a vector
Unreachable vector
zones
to which there is no unreachable-vector-zone as indicated in
Fig. 3. When this inverter is operated with highest possible
levels (85 levels), the rotating vector locus will pass through
unachievable-space-vector-zone as indicated in Fig. 3.: this is
going to increase the THD in line-to-line voltage as indicated
in Fig. 4. This highest levels in line-to-line voltage is
considered as unity modulation index. This results a higher
range of modulation index, where stair-case modulation will
be ood enough to keep rhe harmonic content of the output
voltage within limit. This will allow the designer to minimize
switching losses. Apart from device losses, filter inductor size
will be minimized and specific core loss will be very close to
the specific core losses corresponding to ideal sinusoidal
voltage. A brief estimation of specific eddy current loss
reduction can be obtained from [8]. Also, this may be noted
that, there will be no minor/local hysteresis loops in case of
staircase modulation. As the output voltage will be
monotonically increasing from its minima to maxima, and vice
versa.
The lowest voltage cells will be operating in high frequency.
Power MOSFETs will be a good choice for lowest voltage
bridges. It is well known that, the on-state-resistance
drastically reduces with reduction of breakdown voltage BV,
as given in equation (8).
 (8)
Where, x varies from 2 to 2.7 depending on device. This will
optimize conduction and switching losses.
Fig. 4. Percentage THD as a of numb of levels in output voltage, while
operating in stair-case modulation.

Line-to-line voltage
Voltage

Phase voltage
Fig.6. Scaled-down laboratory prototype circuit diagram.

level jump in the line-to-line voltage. When the modulation

index is reduced to 0.9 the corresponding space-vector circle
in Fig. 3 does not pass through unachievable zone. So, there is
Time in second
(a) no level-jump observed in corresponding line voltage as
shown in Fig. 5. (b). Number of levels are reduced to 17 at a
modulation index of 0.2 as shown in Fig. 5. (c).
Voltage

Corresponding THD may be observed in Fig. 4. There is

always level-jump in phase voltage even if there is no level
jump observed in line voltage in Fig. 5. This is because the
unachievable levels in the phase voltage are skipped by the
modulation technique. It may be noted that, the phase voltage
retains half wave symmetry without any dc offset. This is
because the space vectors generated by bridges of different dc
Time in second
(b)
bus voltage becomes equal and opposite, when an equal and
opposite vector appears in reference (which is obvious for a
rotating vector following a circular locus).
Voltage

IV. EXPERIMENAL RESULTS

Time in second
(c)
Fig. 5. Line-to-line voltage and corresponding phase voltage for given
asymmetry at different modulation index (operating at stair-case modulation)
(a) Modulation index of 1 (85 level in line-to-line voltage), (b) Modulation
index of 0.9 (77 levels in line-to-line voltage) , (c) Modulation index of 0.2
(17 levels in line-to-line voltage).
III. SIMULATION RESULTS AND DISCUSSION
Fig.5. shows the line-to-line voltage and corresponding
phase voltages of the proposed converter at different
modulation indexes. Starting with unity modulation index at
Fig.13.(a), 85 level line-to-line voltage is observed. It is
important to note that, there is level-jump in regular interval of
nearly 30. This may be understood by interpreting the space-
vectors corresponding to this converter drawn in Fig. 3. This is
due to unachievable-space-vector at the periphery; causing
Experimental results are obtained using scaled-down
laboratory prototype as shown in Fig. 6. This is controlled by
dSPACE1103 controller. Hardware parameters of the
laboratory prototype is provided in TABLE-I.
An induction motor with 190V line-to-line voltage at 50Hz
(Marathon Electric make) is used as load. Fig.7. Shows one
of the line-to-line voltage and corresponding phase voltages
obtained by stare-case modulation at (a): unit modulation
index and (b): modulation index of 0.9. Following points may
be noted in these waveforms:
i. Line voltage is having level-jumps when the
inverter is operating at unity modulation index.
This matches well with the theory and simulation
results shown in previous section.
ii. Phase voltages are skipping the unachievable
levels, but it does not affect the line-to-line
voltage at modulation index of 0.9.


 iii. Spikes are observed at the transition of levels
(unlike simulation), as there is few micro-second
delay between necessary switching for level
transition.
iv. Voltage THD of these line voltage is found
negligible. This is matching with the harmonic
spectrum provided for these waves in Fig. 4.
TABLE-I
HARDWARE SETUP DETAILS FOR THREE PHASE CASCADED
H-BRIDGE INVERTER
Experimental Parameters Details
Number of H-Bridge Per Phase 3
Number of Phases at Output 3
DC bus voltages of cascaded bridges 80V, 20V, 5V
H-Bridge DC-Bus Capacitances 11,000 F Fig. 8. Expanded view of the spikes observed in line-to-line voltage
IGBT Modules (Semikron Make) SKM75GB12T4 waveforms.
IGBT Gate Drivers (Semikron Make) SKHI 22AR
Cooling Forced Air
Heat Sink (P3 type Semikron Make) 0.14Kelvin/Watt
Controller dSPACE1103

components, 10db per division

Magnitude of harmonic

Frequency of the harmonic components 50Hz/division

Fig. 9. Harmonic components of line-to-line voltage waveform at unity
modulation index.

All the voltage waveforms observed are containing spikes.

This is due to switching time mismatch. For all practical
(a) considerations, this has no effect on current waveform. This
may be understood from the waveform captured in Fig. 8.:
Duration of these spikes are typically below 3 micro-seconds.
So, this does not require any additional power filter. Fig.9.
shows the harmonic spectrum at unity modulation index(with
85 levels in line-to-line voltage). All harmonic components are
found below 40db: all harmonic components are less than 1%
of fundamental. Three-phase balanced line-to-line voltage is
shown in Fig. 10.
Total power handled by the auxiliary bridges is found much
lower than trinary or binary. This will reduce the size of
isolated power supplies to feed the auxiliary bridges: results in
higher efficiency, and becomes more suitable to use with
single dc supply.

(b)
Fig. 7. Line-to-line voltage and corresponding phase voltages at, (a) Unity
modulation index and (b) at a modulation index of 0.9.


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(b)
Fig. 10. Line-to-line voltage of three phases voltages at, (a) Unity modulation
index and (b) at a modulation index of 0.9.

V. CONCLUSIONS
A mathematical tool is developed in this work to study the
possibility to use various ratios of asymmetry for Three-phase
asymmetric CHBMLC. Ratio of asymmetry given by 1:4:
...:4m is identified as the highest asymmetry to operate at wide
modulation index range with stair-case modulation.
Unreachable-vector-zones exist only at periphery. 85 levels
are obtained in line-to-line voltage with only three H-bridges
per phase. Such configuration is capable to reduce filtering
requirement and corresponding losses. Therefore, the size of
auxiliary power supply is reduced paving way for optimization
of device losses. It is expected to be very useful for many
three-phase converter applications with the requirement of
operation in a wide modulation index range. Since the rating
of the auxiliary power converters are reduced, this is also
expected to be useful for multilevel inverter fed from single dc
source. Experimental results obtained from laboratory
prototype match well with the simulation results validating the
proposed topological alternatives.