Digital Logic Design

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Table of Contents
Digital Logic Circuits................................................................................................................................5
Types of Digital Circuits..............................................................................................................5
Combinational Circuits................................................................................................................5
Sequential Circuits.......................................................................................................................5
Logic Gates..................................................................................................................................5
Demorgans Theorems.................................................................................................................6
Canonical forms of Boolean Expressions....................................................................................8
Sum of Products...........................................................................................................................8
Product of Sums...........................................................................................................................8
Procedure to obtain a fully developed SOP and POS..................................................................9
Reduction/Minimization of Boolean Expressions (Verify)......................................................10
Karnaugh Map Method..............................................................................................................11
Minimization Procedure using Karnaugh Maps........................................................................12
Universal Gates..........................................................................................................................19
Realization (Construction) procedure using NAND gates........................................................20
Realization (Construction) procedure using NOR gates...........................................................20
Problems and Solutions.............................................................................................................20
Combinational Circuits..............................................................................................................26
Half Adder.................................................................................................................................26
Half Subtractor..........................................................................................................................26
Full Adder..................................................................................................................................27
Full Subtractor...........................................................................................................................28
Full Adder using 2 Half Adders.................................................................................................29
Full Subtractor using 2 Half Subtractors...................................................................................30
Multiplexer................................................................................................................................30
o 4 X 1 Multiplexer...............................................................................................30
o 8 X 1 Multiplexer...............................................................................................31
Demultiplexer............................................................................................................................33
o 1 X 4 Demultiplexer...........................................................................................33

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 o 1 X 8 Demultiplexer...........................................................................................34
Decoder......................................................................................................................................36
Sequential Circuits.....................................................................................................................36
Flip Flops...................................................................................................................................36
o Introduction........................................................................................................36
o RS Latch (Unclocked RS Flip Flop)..................................................................37
o RST (Clocked RS Flip Flop)..............................................................................38
o Clocked D Flip Flop...........................................................................................40
Edge Triggered D Flip Flop......................................................................41
o Clocked JK Flip Flop.........................................................................................43
Edge Triggered JK Flip Flop.....................................................................44
o Master Slave Flip Flop.......................................................................................45
Registers....................................................................................................................................46
o Shift Left Register..............................................................................................46
o Shift Right Register............................................................................................47
Counters.....................................................................................................................................48
o Ripple Counter (Asynchronous Counter)...........................................................49
o Synchronous Counter.........................................................................................51
o Mod Counter.......................................................................................................52
MOD-10 Counter......................................................................................52
MOD-6 Counter........................................................................................54
MOD-12 Counter......................................................................................56
o Ring Counter......................................................................................................57

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Page 4 of 58
 Digital Logic Circuits
Types of Digital Circuits
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 Combinational Circuits
In a combinational circuit the output changes whenever there is a change in the input.
The output always depends upon the present combination of inputs.
Eg. Gates
Block Diagram

Sequential Circuits
In the sequential circuit the output depends not only on the present combination of inputs but also on the past
history of the circuit.
To retain the past history of the circuit a memory element is used in sequential circuits.
Eg., FLIP-FLOPs, REGISTERs and COUNTERs.
Block Diagram

Logic Gates
LOGIC
GaTE SYMBOL RESULT
EXPR

a f
NOT f=a 0 1
1 0

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 a b f
0 0 0
AND f=a.b 0 1 0
1 0 0
1 1 1

a b f
0 0 0
OR f=a+b 0 1 1
1 0 1
1 1 1

a b f
NAND __ 0 0 1
(Opp of 0 1 1
f =a.b
AND) 1 0 1
1 1 0

a b f
___
NOR 0 0 1
(Opp of f =a+b 0 1 0
OR) 1 0 0
1 1 0

a b f
X-OR 0 0 0
(Exclusive _ _ 0 1 1
OR) f=a.b+a.b 1 0 1
1 1 0

a b f
X-NOR 0 0 1
(Exclusive 0 1 0
__
NOR) 1 0 0
f=a .b+a.b
1 1 1

Demorgans Theorems
State and prove demorgans theorems.
__ __ __ __
o A+B=A .B
__ __ __ __
o A .B=A +B

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 __ __ __ __
o A+B=A .B
__ __ _____ __ __
A B A B A +B A +B A . B

0 0 1 1 0 1 1
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0

__ __ __ __
o A .B=A +B
__ __ _____ __ __
A B A B A.B A .B A + B

0 0 1 1 0 1 1
0 1 1 0 0 1 1
1 0 0 1 0 1 1
1 1 0 0 1 0 0

Construct a truth table for the following expression :

_
o f = abc+ab+ac
__ _
a b c abc b a .b ac f
0 0 0 0 1 0 0 0
0 0 1 0 1 0 0 0
0 1 0 0 0 0 0 0
0 1 1 0 0 0 0 0
1 0 0 0 1 1 0 1
1 0 1 0 1 1 1 1
1 1 0 0 0 0 0 0
1 1 1 1 0 0 1 1

Construct a truth table for the following expression :

_
o f = abc+bcd+ad

_ _
a b c d abc bcd d a.d f
0 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0
0 0 1 0 0 0 1 0 0
0 0 1 1 0 0 0 0 0
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 0 0 0

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0 1 1 0 0 0 1 0 0
0 1 1 1 0 1 0 0 1
1 0 0 0 0 0 1 1 1
1 0 0 1 0 0 0 0 0
1 0 1 0 0 0 1 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 0 1 1 1
1 1 0 1 0 0 0 0 0
1 1 1 0 1 0 1 1 1
1 1 1 1 1 1 0 0 1

Canonical forms of Boolean Expressions

The Boolean expressions can exist in 2 forms. They are
o SOP (Sum of Products)
o POS (Product of Sums)

Sum of Products
o An expression is said to be in SOP form, if it is formed with product terms combined
with a sum.
o Eg.,
_
1. f = a.b + ac + ad
_ __ _ _ _
2. f = a.b.c + a.b.c + a . b . c + a.b.c
_ _
3. f = a.b + a

4. f = abcd

o If every term contains all the variables either in the direct form or in an indirect form
then such an SOP is said to be fully developed or expanded SOP.
o Examples 2 and 4 are in fully developed form.
Product of Sums
o An expression is said to be in POS form, if it is formed with sum terms combined with a
porduct.
o Eg.,
_ _ _ _ _
1. f = (a+b) (a+c)(a+d)
_ _ _ _ _ _
2. f = (a+b+c)( a+b+c)( a+b+c)( a+b+c)
_
3. f = (a + b) . a

4. f = (a+b+c+d)

o If every term contains all the variables either in the direct form or in an indirect form
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 then such an POS is said to be fully developed or expanded SOP.
o Examples 2 and 4 are in fully developed form.

Procedure to obtain a fully developed SOP and

POS.
Procedure (Verify)
1. Construct a truth table.
2. From the truth table wherever the function output is 1, the corresponding input variables
yield the result in SOP form with 0 Indirect and 1- Direct.
3. From the truth table wherever the function output is 0, the corresponding input variables
yield the result in POS form with 1- Indirect and 0 Direct.
Simplify the following expressions into fully developed SOP and POS forms.
_ _
o f = a.b + a
_ _
a b a b f
0 0 1 1 0(1) + 1 = 1 SOP
0 1 1 0 0(0) + 1 = 1 SOP
1 0 0 1 1(1) + 0 = 1 SOP
1 1 0 0 1(0) + 0 = 0 POS
__ _ _
fsop = a.b + a.b + a.b
_ _
fpos = (a+.b)

__ _
o f = a.b + b
_ _ _ _
a b a b a .b f
0 0 1 1 1 1 SOP
0 1 1 0 0 0 POS
1 0 0 1 0 1 SOP
1 1 0 0 0 0 POS
__ _
fsop = a.b + a.b
_ _ _
fpos = (a+.b) (a + b)

o f = a.b + ac
a b c ab ac f
0 0 0 0 0 0 POS
0 0 1 0 0 0 POS
0 1 0 0 0 0 POS
0 1 1 0 0 0 POS
1 0 0 0 0 0 POS
1 0 1 0 1 1 SOP

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 1 1 0 1 0 1 SOP
1 1 1 1 1 1 SOP
_ _
fsop = a.b.c + a.b.c + a.b.c
_ _ _ _ _
fpos = (a +.b + c) (a + b + c) (a + b + c) (a + b + c) (a + b + c)

_ _
o f = a.b + c . d
_ _ _ _
a b c d c d ab c . d f
0 0 0 0 1 1 0 1 1 SOP
0 0 0 1 1 0 0 0 0 POS
0 0 1 0 0 1 0 0 0 POS
0 0 1 1 0 0 0 0 0 POS
0 1 0 0 1 1 0 1 1 SOP
0 1 0 1 1 0 0 0 0 POS
0 1 1 0 0 1 0 0 0 POS
0 1 1 1 0 0 0 0 0 POS
1 0 0 0 1 1 0 1 1 SOP
1 0 0 1 1 0 0 0 0 POS
1 0 1 0 0 1 0 0 0 POS
1 0 1 1 0 0 0 0 0 POS
1 1 0 0 1 1 1 1 1 SOP
1 1 0 1 1 0 1 0 0 POS
1 1 1 0 0 1 1 0 0 POS
1 1 1 1 0 0 1 0 0 POS
____ _ __ ___ __
fsop = a.b.c.d + a.b.c.d + a.b.c.d + a.b.c.d
_ _ _ _ _ _ _ _
fpos = (a +.b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
_ _ _ _ _ _ _ _ _ _ _ _ _
(a +.b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d) (a + b + c + d)
_ _ _ _ _ _ _
(a +.b + c + d) (a + b + c + d)
Reduction/Minimization of Boolean Expressions (Verify)
The Boolean expressions can be minimized using any of the following methods.
o Algebraic Method or Mathematical Method.
o Karnaugh Map Method or Graphical Method
o Tabular Method
Problems.
_
o f = ab + a
_
a b a ab f
0 0 1 0 1 SOP
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 0 1 1 0 1 SOP
1 0 0 0 0 POS
1 1 0 1 1 SOP

__ _
fsop = a.b + a.b + a.b
= E 00, 01, 11
= E 0, 1, 3

o f = E 0, 1, 3, 4, 7
= E 000, 001, 011, 100, 111
___ __ _ __
= a.b.c + a.b.c + a.b.c + a.b.c + a.b.c

o f = E 0, 1, 14, 15
= E 0000, 0001, 1110, 1111
____ ___ _
= a.b.c.d + a.b.c.d + a.b.c.d + a.b.c.d

Karnaugh Map Method

It is also known as Graphical Method.
This method is seldom used for minimization of Boolean expressions when the number of variables are more
than 5.
Two Variable Karnaugh Map
o Expression Form and Numeric Form

Three Variable Karnaugh Map
o Expression Form and Numeric Form

Four Variable Karnaugh Map

o Expression Form and Numeric Form
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 o
Adjacent Cells
o Two cells are said to be adjacent when we go from one cell to another cell only one variable changes and
the other variable remains constant.
o The horizontal cells, vertical cells and corner cells are examples of adjacent cells.

Minimization Procedure using Karnaugh Maps

o The process consists of 2 parts.
Combination of adjacent cells.
Reduction
Combination of Adjacent Cells
o Procedure
a) Combine adjacent cells with value one among them.
b) Combine 2n cells in each combination.
c) Always try to combine as many cells as possible in each combination.
d) Every cell can be considered any number of times. But each combination should include atleast one
cell which is uncombined.
Reduction
o Procedure
a) Each combination yields the result by dropping some of the variables.
b) When 2 cells are combined one variable is dropped, when 4 cells are combined 2 variables are
dropped, when 2n cells are combined n variables are dropped.
c) The variables to be dropped are the variables whose value changes within the combination.
Simplification into SOP
o f= (0, 1, 3)

o f= (0, 2, 3)

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o f= (1, 2, 3)

o f= (0, 1, 2, 4, 5)

o f= (0, 1, 2, 3, 4, 5)

o f= (1, 2, 3, 4, 5, 7)

o f= (0, 1, 3, 4, 6, 7)

o f= (0, 1, 2, 4, 5, 6)

o f= (0, 1, 2, 3, 6, 7)

o f= (0, 1, 2, 4, 7)

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o f= (0, 2, 3, 4, 6, 7)

o f= (0, 1, 2, 3, 4, 5, 8, 9, 10, 11, 14, 15)

o f= (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15)

o f= (0, 1, 2, 3, 6, 7, 8, 9, 12, 13)

o f= (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)

o f= (0, 1, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15)

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o f= (0, 1, 3, 4, 5, 7, 8, 9, 14, 15)

o f= (0, 1, 3, 4, 5, 7, 8, 9, 11, 14, 15)

o f= (0, 1, 3, 4, 5, 7, 8, 9, 11)

o f= (0, 1, 2, 4, 5, 8, 10)

o f= (0, 1, 2, 3, 4, 5, 8, 10, 12)

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Develop a truth table from the following expressions and simplify.

__ __
o f=ab+ac+ab+abc

_ ___
o f=ab+ac+bd+abc+abc+abc

o f=a +b+c+d

_ _ _ _
o f=a+b+c+d

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___ ___ _
o f=abc +abc+bcd+bcd+abc

Simplification into POS

o f= (0, 1, 2, 3, 6, 7, 8, 9, 12, 13)

o f= (0, 1, 4, 5, 6, 7, 10, 11, 14, 15)

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 o f= (0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 13)

o f= (2, 3, 4, 5, 8, 9, 10, 11, 14, 15)

o f= (0, 2, 4, 6, 8, 9, 10, 14, 15)

Simplification into SOP and POS

o f= (0, 1, 4, 5, 6, 7, 8, 10, 13, 15)

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Dont Care Conditions in Karnaugh Maps

o A dont care cells are marked as X in the karnaugh maps.
o They can take a value of 0 or 1 at the time of combination of cells
o In order to get the best possible combination the dont care cells are given values.

o f= (0, 1, 2, 3, 8, 9) + d(10, 11, 12, 15)

o f= (0, 1, 4, 5, 6, 7, 8) + d(2, 3, 10, 11)

Universal Gates
NAND and NOR gates are known as Universal gates.
Because any other gate can be obtained using only NAND or NOR gate.
NOT, AND and OR Gates using NAND and NOR Gates only.
Gate Truth Using NAND Gate Using NOR Gate
Table
NOT A f
0 1
1 0

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AND A B f
0 0 0
0 1 0
1 0 0
1 1 1

OR A B f
0 0 0
0 1 1
1 0 1
1 1 1

Realization (Construction) procedure using

NAND gates
a) Obtain the expression in SOP form (need not be fully developed).
b) Double negate the expression.
_____ _ _
c) To the inner negation apply Demorgans Theorem a + b = a . b
d) The result obtained is the NAND gate equivalent.

Realization (Construction) procedure using

NOR gates
a) Obtain the expression in POS form (need not be fully developed).
b) Double negate the expression.
_____ _ _
c) To the inner negation apply Demorgans Theorem a . b = a + b
d) The result obtained is the NOR gate equivalent.

Problems and Solutions

Construct circuits using only NAND gates.
o Realize X-OR Gate using only NAND gates

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o Realize X-NOR Gate using only NAND gates

o Realize the following expression using only NAND gates.

f= (0, 1, 2, 3, 4, 5, 8, 9, 14, 15)

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o Realize the following expression using only NAND gates.
f= (0, 1, 4, 5, 6, 7, 10, 11, 12, 13)

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 Construct circuits using only NOR gates.
o Realize X-OR Gate using only NOR gates

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o Realize X-NOR Gate using only NOR gates

o Realize the following expression using only NOR gates

f= (0, 1, 2, 3, 4, 5, 8, 9)

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o Realize the following expression using only NOR gates
f= (0, 1, 2, 3, 4, 5, 8, 9, 12, 13, 14 15)

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Combinational Circuits
Half Adder
A half adder is a digital circuit which takes 2 binary bits as inputs, adds them and produces 2 outputs Sum (S) and
Carry (C or Co).
The Block Diagram and Truth Table of a Half Adder are shown below
Block Diagram Truth Table

o
From the Truth Table, the logical expressions for the half adder can be obtained as follows ::-

Circuit Diagram

Half Subtractor
A half subtractor is a digital circuit which takes 2 binary bits as inputs, performs the subtraction and produces 2
outputs Difference (D) and Borrow (Bo).
The Block Diagram and Truth Table of a Half Subtractor are shown below.
Block Diagram Truth Table

From the Truth Table, the logical expressions for the half subtractor can be obtained as follows

Circuit Diagram

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 o

Full Adder
A full adder is a digital circuit which takes
o 3 binary digits (2 binary bits to be added with a carry-in bit) as inputs, and
o Produces 2 outputs, the Sum and the Carry-out
The Block Diagram and Truth Table of a Full Adder are shown below.
Block Diagram Truth Table

From the Truth Table, the logical expressions for the Full Adder can be obtained as follows ::-

Simplification of both the expressions

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 Circuit Diagram

Full Subtractor
A full subtractor is a digital circuit which takes
o 3 binary digits (2 binary bits to be subtracted with a borrow-in bit) as inputs, and
o Performs subtraction and produces 2 outputs, the Difference and the Borrow-out
The Block Diagram and Truth Table of a Full Subtractor are shown below.
Block Diagram Truth Table

From the Truth Table, the logical expressions for the Full Subtractor can be obtained as follows ::-

Simplification of both the expressions

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 Circuit Diagram

Full Adder using 2 Half Adders

The logical expressions of a half adder are as follows ::-

The logical expressions of a full adder are as follows ::-

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 A full adder can be constructed using 2 half adders as shown below ::-

Full Subtractor using 2 Half Subtractors

The logical expressions of a half subtractor are as follows ::-

The logical expressions of a full subtractor are as follows ::-

A full subtractor can be constructed using 2 half subtractors as shown below ::-

Multiplexer
A multiplexer is a combinational circuit which takes 2n input lines and a single output line.
It will have n select lines.
The n select lines are used to select which out of the 2n input lines are to be allowed onto the single output line.

o 4 X 1 Multiplexer
o The Block Diagram and Truth Table of a 4 X 1 Multiplexer are shown below.

Block Diagram Truth Table

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 S0 S1 O

0 0 I0
0 1 I1
1 0 I2
1 1 I3

Circuit Diagram
A 4 X1 multiplexer can be realized using 4 AND gates and a single OR gate as shown
below.

o
Theory
When S0, S1 are (0, 0) then the input line I0 will be selected and whatever is its value is
passed onto the output line.
Similarly when S0, S1 are (0, 1) then the input line I1 will be selected and whatever is its
value is passed onto the output line, etc.

o 8 X 1 Multiplexer
The Block Diagram and Truth Table of a 4 X 1 Multiplexer are shown below.

Block Diagram Truth Table

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 S0 S1 Ss O

0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Circuit Diagram
A 8 X1 multiplexer can be realized using 8 AND gates and a single OR gate as shown
below.

Theory
When S0, S1, S2 are (0, 0, 0) then the input line I0 will be selected and whatever is its
value is passed onto the output line.
Similarly when S0, S1, S2 are (0, 0, 1) then the input line I1 will be selected and whatever
is its value is passed onto the output line, etc.

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 Demultiplexer
A demultiplexer is a combinational circuit with one input line and 2n output lines and n select lines.
The select lines are used to select one of the output lines onto which the input is to be allowed.

o 1 X 4 Demultiplexer

The Block Diagram and Truth Table of a 1 X 4 Demultiplexer are shown below.
Block Diagram Truth Table

S0 S1 O0 O1 O2 O3

0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I

Circuit Diagram
A 1 X4 demultiplexer can be realized using four AND gates as shown below.

Theory
When S0, S1 are (0, 0) the output line O0 will be selected and the input I is allowed
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 onto the output line O0.
If I = 0 output line O0 gets zero and if I = 1 then O0 gets one, etc.

o 1 X 8 Demultiplexer

The Block Diagram and Truth Table of a 1 X 8 Demultiplexer are shown below.
Block Diagram Truth Table

S0 S1 S2 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0
0 0 1 0 I 0 0 0 0 0 0
0 1 0 0 0 I 0 0 0 0 0
0 1 1 0 0 0 I 0 0 0 0
1 0 0 0 0 0 0 I 0 0 0
1 0 1 0 0 0 0 0 I 0 0
1 1 0 0 0 0 0 0 0 I 0
1 1 1 0 0 0 0 0 0 0 I

Circuit Diagram
A 1 X8 demultiplexer can be realized using 8 AND gates as shown below.

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 Decoder
A decoder is also known as a code converter.
In a demultiplexer if the input line is taken as enable line and the select lines are taken as input then a
demultiplexer becomes a decoder.

o 2 X 4 Decoder
Circuit Diagram

Theory
When the enable line is equal to zero the circuit does not function.
When the enable line is high (E=1) then the circuit functions and acts as a code
converter.
The Block Diagram and Truth Table of a 2 X 4 Decoder are shown below.
Block Diagram Truth Table

E I0 I1 Output
0 X X --
1 0 0 O0
1 0 1 O1
1 1 0 O2
1 1 1 O3

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Sequential Circuits
Flip Flops

o Introduction

A flip flop is a memory cell capable of storing one bit of information.

When more than one flip is connected in series then it is called a register.
A flip flop can have only two stable states (0, 1).
It always tries to be in only one of these 2 states unless the inputs vary and affect the final state
of flip flop. _
A flip flop has two outputs (Q, Q) which are compliment of each other.
The state of flip flop is always referred by means of its normal output.
The following are the different types of flip-flops.
RS flip flop
RST flip flop
D flip flop
JK flip flop
T flip flop
Master Slave flip flop
The difference between the various types of flip flops can be looked at based on the number of
inputs and how these inputs can affect the final state Q of the flip flop.

o RS Latch (Unclocked RS Flip Flop)

An RS LATCH is also known as Unclocked flip flop.
It can be realized using two NAND or two NOR gates.
The block diagram and circuit diagram of RS LATCH are as follows
Block Diagram Circuit Diagram

The 2 inputs R, S stand for Reset and Set.

When the R, S are low (0, 0) then there is no change in the output then the flip flop
remains in its last state.
When R is low and S is high (0, 1) the circuit sets and the output Q becomes high (Q =
1)
When R is high and S is low (1, 0) the circuit resets and the output Q becomes low (Q =
0)
When R is high and S is high (1, 1) the circuit the output does not behave properly and
such an input combination is invalid. This condition is also known as the RACE
condition and it leads to unpredictable result.
The truth table of an RS Latch is given below

R S Q Comment

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 0 0 NC No change
0 1 1 Set
1 0 0 Reset
1 1 * RACE
The reason for racing may be explained as follows.
o When the inputs of R, S are low (0, 0) then the transistors of both these gates
gets desaturated. When these inputs are returned back to high (1, 1) then these
transistors try to get back into saturation state then there will be a race to see
which one saturates first, in the mass production of transistors either side of the
transistors can be faster.
o If the faster transistor is on the side of R then the output Q becomes low (Q=0).
On the other hand if the faster transistor is on the side of S then the output Q
becomes high (Q=1). Hence the result is unpredictable and it is the reason why
a RACE condition must be avoided.
The timing diagram of RS Latch is given below

o RST (Clocked RS Flip Flop)

In an RST flip flop there is an additional input known as a clock.
When the clock input is present in a flip flop then they are known as clocked flip flops or
synchronized.
The block diagram and circuit diagram of RST flip flop are as follows
Block Diagram Circuit Diagram

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 A clock is a digital circuit which produces square wave signals of constant pulse width.
The clocking is of 2 types
o Positive clocking
o Negative clocking
In the case of positive clocking the output can change only when the clock is high,
where as in the case of negative clocking the output can change only when the clock is
low.
The following is the working of an RST flip flop with positive clocking.
o According to positive clocking when the clock is low the inputs R, S cannot
change the output of the flip flop.
o When the clock is high and R, S are (1, 0) then the output is reset (Q = 0)
o When the clock is high and R, S are (0, 1) then the output of the flip flop is set
(Q=1)
o When the clock is high and R, S are (1, 1) then the RACE condition occurs
which leads to unpredictable result.
The following is the truth table of a positively clocked RST flip flop.
Negative Clock Positive Clock R S Q Comment
1 0 X X NC No change
0 1 0 0 NC No change
0 1 0 1 1 Set
0 1 1 0 0 Reset
0 1 1 1 * RACE

The timing diagram of a positively clocked RST flip flop is shown below

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o Clocked D Flip Flop

In an RS flip flop there is a drawback of racing.

In the case of D flip flop the idea is to modify the design of an RS flip flop so that the race
condition may be eliminated.
The block diagram and circuit diagram of a clocked D flip flop are shown below.
Block Diagram Circuit Diagram

In clocking there are two types

o Positive clocking
o Negative clocking
In positive clocking a high value of clock controls the output whereas in negative
clocking a low value of clock controls the output.
According to positive clocking when the clock is high a high value of D sets the flip
flop and a low value of D resets the flip flop.
The truth table of a positively clocked D flip flop is shown below
Negative Clock Positive Clock D Q Comment
1 0 X NC No change
0 1 1 1 Set
0 1 0 0 Reset

The timing diagram of a positively clocked D flip flop is shown below.

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 Edge Triggered D Flip Flop
In the case of edge triggering an RC circuit will be used in the input signal of the clock.
The block diagram and circuit diagram of an edge triggered D flip flop are as shown
below
Block Diagram Circuit Diagram

o The edge triggering are of two types

Positive triggering
Negative triggering
o In the case of positive triggering the output changes only during the raising
edge of the clock, whereas in the case of negative triggering the output changes
only during the falling edge of the clock.
The truth table of a positively edge triggered D flip flow is shown below

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 The timing diagram of a positively edge triggered D flip flop is shown below

o Clocked JK Flip Flop

In a clocked JK flip flop there is a clock input along with the normal inputs J, K.
The circuit diagram of a clocked JK flip flop is shown below.

A clock is a digital circuit which produces square wave signals.

The clocking is of two types
o Positive clocking
o Negative clocking
In positive clocking a high value of the clock controls the output whereas in negative
clocking a low value of clock controls the output.
The truth table of a positively clocked JK flip flop is given below
CLK J K Q Comment
0 X X NC No Change
1 0 0 NC No Change
1 0 1 0 Reset
1 1 0 1 Set
1 0 1 * RACE
The race can be explained as follows
o When J,K are both high (1, 1) a high clock toggles the output.
o But the drawback is that toggling may occur more than once during a clock
cycle, which is called racing.
o The racing in a JK flip flop is eliminated by 2 methods
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 Edge triggered JK flip flop
Master-Slave flip flop

Edge Triggered JK Flip Flop

In an edge triggered JK flip flop an RC circuit is used along with the input signal of a
clock.
The circuit diagram of an edge triggered JK flip flop is shown below

o The edge triggering is of two types

Positive edge triggering
Negative edge triggering
o According to positive edge triggering the outputs can change only during the
raising edge of the clock, whereas in negative edge triggering the outputs can
change only during the falling edge of the clock.
The truth table of a positive edge triggered JK flip flop is given below

o When J is low, K is high at the raising edge of the clock the output resets
(Q=0).
o When J is high and K is low at the raising edge of the clock the output sets
(Q=1)
o When J is high, K is high the output toggles.
o Toggling means changing to opposite state on every clock edge. But toggling
occurs only once per clock cycle in an edge triggered JK flip flop and thus it
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 eliminates unpredictable result.
The timing diagram of an edge triggered JK flip flop is given below.

o Master Slave Flip Flop

A MASTER-SLAVE flip flop is a complete solution to eliminate the problem of racing.
It is a combination of two clocked flip flops.
The first one is called MASTER and the second one is called the SLAVE.
The MASTER is positively clocked and the SLAVE is negatively clocked.
The circuit diagram of a MASTER-SLAVE JK flip flop is shown below

Combination of clocked JK (MASTER) and clocked RS (SLAVE) flip flops.

o When the clock is high, the Master will be active and the Slave will be
inactive, When the clock become low, Master becomes inactive and the Slave
becomes active.
o When J is high and K is low a high clock sets the Master (S=1) but nothing
happens to the final output Q because the Slave is inactive when the clock is
high. When the clock becomes low the high value of S and low value of R sets
the final output Q (Q=1)
o When J is low, K is high a high clock resets the Master (S=0) but nothing
happens to the final output Q. When the clock becomes low, the low value of S
and high value of R resets the final output of Q.
o When (J, K) are both high, the Master toggles once when the clock is high and
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 the Slave toggles once when the clock is low. Hence the final output Q toggles
only once in a clock cycle and thereby the problem of racing is eliminated.
The truth table of a MASTER-SLAVE flip flop is shown below.

The timing diagram of a MASTER-SLAVE flip flop is shown below

Registers
A register is a group of flip flops connected in series.
A register in its simplest form can only store information and such a register is known as Buffer Register.
In case if the connection among the flip flops is done in such a way that the output of one flip flop forms input to
the other then this stored information can be modified by shifting the bits towards the left or right. Such a register is
called a shift register.
The shift registers are of two types
o Shift Left Register
o Shift Right Register

o Shift Left Register

A shift left register moves the stored information to the left.

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 It can be made up by means of edge triggered D flip flop as shown below.

Initially the output from the shift register Q= 0000 (Q3, Q2, Q1, Q0).
When Din =1,
o during the first raising edge of the clock the stored information becomes
Q=0001.
o During the second raising edge of the clock the output Q becomes Q=0011.
o The third raising edge of the clock results Q=0111, and
o The fourth raising edge results Q=1111.
o From there-after the output remains unchanged as long as the input is Din =1.
Suppose Din is now changed to zero then every successive clock pulse at the raising
edge produces the following outputs.
o Q = 0111
o Q = 0011
o Q = 0001
o Q = 0000
The truth table of a 4bit shift left register is given below.
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 1 1
4 1 1 1 1
5 1 1 1 1 (Unchanged)
6 1 1 1 0
7 1 1 0 0
8 1 0 0 0
9 0 0 0 0

The timing diagram of a 4bit shift left register is given below.

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o Shift Right Register

A shift right register moves the stored information towards the right.
It can be constructed using edge triggered D flip flops as shown below.

Initially the output Q=0000 (Q3, Q2, Q1, Q0).

When Din =1,
o during the first raising edge of the clock the stored information becomes
Q=1000.
o During the second raising edge of the clock the output Q becomes Q=1100.
o The third raising edge of the clock gives Q=1110, and

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 o The fourth raising edge outputs Q=1111.
o From there-after the output Q remains unchanged as long as Din =1.
If Din is changed to zero then every successive clock pulse at its raising edge produces
the following outputs.
o Q = 0111
o Q = 0011
o Q = 0001
o Q = 0000
The truth table of a 4bit shift left register is given below.
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 1 1 1 1 (Unchanged)
6 0 1 1 1
7 0 0 1 1
8 0 0 0 1
9 0 0 0 0

The timing diagram of a 4bit shift right register is given below.

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 Counters
A counter is a special type of register which is designed to count the number of clock pulses arriving as inputs.
The following are the different types of counters
o Ripple Counter
o Synchronous Counter
o Mod Counter
Mod 10 Counter
Mod 6 Counter
Mod 12 Counter
o Ring Counter

o Ripple Counter (Asynchronous Counter)

The ripple counter is known as asynchronous counter.

It is also known as an up counter.
This counter is used to count the number of input clock pulses.
A 4 bit ripple counter may be designed using 4 edge triggered JK flip flops as shown below.

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 Assuming negative edge triggering, the behavior of a 4 bit ripple counter may be
explained as follows
o Initially when CLR becomes low and then back to high the output becomes
Q=0000 (Q3, Q2, Q1, Q0).
o In a JK flip flop when J, K are both high the output toggles once per clock
edge. The clock is connected directly to the first flip flop and the output of the
first flip flop acts a clock to the next flip flop and so on. Similarly Q1, Q2 are
connected as clocks to the successive flip flops as shown in the diagram.
o When the first clock pulse arrives at the following edge the output toggles at
the negative edge and Q0 becomes 1 and Q=0001.
o When the second clock pulse arrives at the negative edge Q1 toggles and the
output becomes Q=0010.
o Similarly when the third clock pulse arrives the output becomes Q=0011.
o Q1 receives negative edge from Q0, Q2 receives negative edge from Q1 and etc.
o When the fifteenth clock pulse arrives the output becomes Q=1111. The next
immediate clock pulse resets all the flip flops to 0000 and the cycle repeats
again.
The truth table of a 4-bit Ripple counter is shown below

CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
The timing diagram of a 4-bit Ripple counter is shown below

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 Drawback of a Ripple Counter
A ripple counter has a drawback known as Ripple Delay problem.
In this counter a Q0 flip flop toggles first and then the Q1 flip flop after that Q2 followed
by Q3.
The worst case occurs when the stored information changes from 0111 to 1000 and 1111
to 0000. In these two cases the delay is maximum.
If Tp is the propagation time for one flip flop then the overall propagation delay is nTp
where n is the number of flip flops.
For this reason of ripple delay, a ripple counter becomes too slow for some applications.
The drawback of a ripple delay can be eliminated using synchronous counter.

o Synchronous Counter
A synchronous counter has no ripple delay problem.
In this counter a clock pulse drives all the flip flops simultaneously. Because of this simultaneous
clocking the correct output appears exactly after one and only one propagation delay time
always.
The block diagram of a synchronous counter is shown below

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 Initially when CLR becomes low and then back to high, the output of the counter
becomes Q=0000.
When the first clock pulse arrives at the negative edge Q0 toggles and the output
becomes Q=0001. Since Q0=1, Q1 toggles.
When the second clock pulse arrives at the following edge both Q0, Q1 toggles
simultaneously and the output becomes Q=0010 with no additional delay.
Similarly when the third clock pulse arrives the output becomes Q=0011 (Q3, Q2, Q1, Q0)
at the falling edge. At this stage Q0=1, Q1=1 and when the fourth clock pulse arrives at
the falling edge Q0, Q1, Q2 toggles simultaneously and the output becomes Q=0100.
The counting goes upto Q=1111 at the fifteenth clock pulse.
The next immediate clock pulse resets the counter to 0000 and the cycle repeats.
The truth table of a Synchronous counter is same as 4-Bit Ripple counter and is shown below

CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
The timing diagram of a Synchronous counter is same as 4-bit Ripple counter and is shown
below

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o Mod Counter
The modulus of a counter may be defined as the number of output states it can have.
A 4-bit ripple counter counts from 0 to 15 and hence its modulus is 16.
Similarly a 3-bit ripple counter can count from 0 to 7 and hence its modulus is 8.
The MOD counters are of different types. Some of them are
MOD-10 Counter
MOD-12 Counter
MOD-6 Counter

MOD-10 Counter
A MOD-10 counter is also known as a decade counter.
It has a modulus of 10 and hence it can count from 0 to 9 (0000 to 1001).
On the tenth clock pulse this counter generates its own clear signal and jumps back to
zero.
MOD-10 Counter state diagram

A MOD-10 counter may be designed using a 4 bit ripple counter as shown below

o Initially when CLR becomes low then the output of the counter becomes
Q=0000.
o When the first clock pulse arrives at the falling edge Q0 toggles and the output
becomes Q=0001.
o Q0 acts as a clock to the next flip flop and similarly Q1, Q2 acts as clocks to their
successive flip flops.
o The counting sequence starts from zero and goes upto 9 as follows
Q = 0000
Q = 0001
Q = 0010
Q = 0011
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 Q = 0100
Q = 0101
Q = 0110
Q = 0111
Q = 1000
Q = 1001
o On the tenth clock edge the output Q becomes Q=1010 (Q3, Q2, Q1, Q0) because
at this stage Q3 =1, Q1 = 1the output from the NAND gate becomes zero y=0
and it causes the counter to reset back to 0000 and the cycle repeats.
The truth table of MOD-10 counter is given below
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
The timing diagram of MOD-10 counter is given below

MOD-6 Counter
A MOD-6 counter has a modulus of 6 and hence it can count from 0 to 5 (0000 to

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 0101).
On the sixth clock pulse this counter generates its own clear signal and jumps back to
zero.
MOD-6 Counter state diagram

A MOD-6 counter may be designed using a 3 bit ripple counter as shown below.

o Initially when CLR becomes low then the output of the counter becomes
Q=0000.
o When the first clock pulse arrives at the falling edge Q3 toggles and the output
becomes Q=0001.
o Q0 acts as a clock to the next flip flop and similarly Q1 acts as a clock to the
next flip flop.
o The counting sequence starts from zero and goes up to 5 as follows.
Q = 0000
Q = 0001
Q = 0010
Q = 0011
Q = 0100
Q = 0101
o On the sixth clock edge the output Q becomes Q=0110 (Q3, Q2, Q1, Q0) because
at this stage Q2 = 1, Q1=1 the output from the NAND gate becomes zero y=0
and it causes the counter to reset back to 000 and the cycle repeats.
The truth table of MOD-6 counter is shown below
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 0 0 0
The timing diagram of MOD-6 counter is shown below
o PENDING

MOD-12 Counter
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 A MOD-12 counter has a modulus of 12 and hence it can count from 0 to 11 (0000 to
1011).
On the twelveth clock pulse this counter generates its own clear signal and jumps back
to zero.
MOD-12 Counter state diagram

A MOD-12 counter may be designed using a 4 bit ripple counter as shown below.

o Initially when CLR becomes low then the output of the counter becomes
Q=0000.
o When the first clock pulse arrives at the falling edge Q0 toggles and the output
becomes Q=0001.
o Q0 acts as a clock to the next flip flop and similarly Q1, Q2 acts as clocks to their
successive flip flops.
o The counting sequence starts from zero and goes up to 11 as follows
Q = 0000
Q = 0001
Q = 0010
Q = 0011
Q = 0100
Q = 0101
Q = 0110
Q = 0111
Q = 1000
Q = 1001
Q = 1010
Q = 1011
o On the twelveth clock edge the output Q becomes Q=1100 (Q3, Q2, Q1, Q0)
because at this stage Q3 =1, Q2 = 1the output from the NAND gate becomes
zero y=0 and it causes the counter to reset back to 0000 and the cycle repeats.
The truth table of MOD-12 counter is given below
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
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 5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 0 0 0 0
The timing diagram of MOD-12 counter is given below
o PENDING

o Ring Counter
A ring counter is also known as a rotate left counter.
It can be made using edge triggered D flip flop as shown below.

o When CLR becomes low and then back to high the initial output Q becomes
Q=0001 (Q3, Q2, Q1, Q0) because the CLR is connected to preset of the first flip
flop.
o The output Q0 sets Q1, and Q1 sets Q2 and etc. in the subsequent clock pulses.
There is a feedback connection from Q3 back to the first flip flop.
o When the first clock pulse arrives at the raising edge the output rotates left and
it becomes Q=0010, the second clock edge results Q=0100 and the third clock
edge results in Q=1000, the fourth clock edge rotates the value towards left and
produces an output Q=0001. The cycle repeats again.
The truth table of a 4 bit ring counter is given below
CLK Q3 Q2 Q1 Q0
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 1 0 0 0
4 0 0 0 1
The timing diagram of a 4 bit ring counter is given below

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