Professional Documents
Culture Documents
0-1
Refined and
optimized
design Fig.3.0-02
This chapter is devoted to the simple model suitable for design not using simulation.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Introduction (12/20/06) Page 3.0-3
Time Dependence
Time Independent Time Dependent
;;;
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0
;; ;;;
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region
Threshold (VG=VT)
;; ;;;
;;;;
VB = 0 VS = 0 VG =VT VD = 0
Polysilicon
p+
;; ;;;
n+ n+
;;;
p- substrate Inverted Region
;;;
VB = 0 VS = 0 VG >VT VD = 0
;;;;;;
;;;
Polysilicon
p+ n+ n+
;;;
VGS≤VT:
VB = 0 VS = 0 vG =VT VD = 0.1V iD
;; ;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region 0 vGS
0 VT 2VT 3VT
VGS=2VT:
;;;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 0.1V iD
iD
Polysilicon
p+
;; ;;; n+ n+
;;;
p- substrate Inverted Region
0 vGS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 0.1V iD
;;;;;;
;;;
Polysilicon
p+ n+ n+
;;;
VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
;;;;
;; ;;;
iD
Polysilicon VGS = 2VT
;; ;;;
p+ n+ n+
;;;
p- substrate Inverted Region
0 vDS
0 0.5VT VT
VDS=0.5VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT
p+
;;
;;;;
;;;
n+ n+
;;;
p- substrate Channel current
0 vDS
0 0.5VT VT
VDS=VT:
;;;
VB = 0 VS = 0 VG = 2VT VD =VT iD
;;
;;;;
;;;
iD VGS = 2VT
Polysilicon
p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04
;;;;;
VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate VGS =VT
0 vDS
0 VT 2VT 3VT
VGS=2VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
;;
;;;;
;;;
VGS =2VT
p+ n+ n+
;;;
p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
;;
;;;;
;;;
iD
Polysilicon
p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05
CMOS Analog Circuit Design © P.E. Allen - 2006
1500
VGS = 2.5
iD(μA)
1000
VGS = 2.0
500
VGS = 1.5
VGS = 1.0
0
SPICE Input File: 0 1 2 3 4 5
vDS (Volts) Fig. 3.1-6
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 +lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 1 (12/20/06) Page 3.1-6
iD(μA)
3000
VDS = 2V
2000
VDS = 1V
1000
0
SPICE Input File: 0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end
CMOS Analog Circuit Design © P.E. Allen - 2006
;;;
SIMPLE LARGE SIGNAL MODEL (SAH MODEL)
;;;
Large Signal Model Derivation +
vGS +
1.) Let the charge per unit area in the channel -
iD - vDS
inversion layer be
n+ n+
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) v(y)
Source dy Drain
p - y
2.) Define sheet conductivity of the inversion 0 L y y+dy
layer per square as Fig.110-03
cm2
coulombs amps 1
S = μoQI(y)
v·s
cm2 = volt = /sq.
3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS = W = -SEy = -S dy dv = SW dy = μoQI(y)W iD dy = -WμoQI(y)dv
4.) Integrating along the channel for 0 to L gives
L vDS vDS
iDdy = - WμoQI(y)dv = WμoCox[vGS-v(y)-VT] dv
0 0 0
5.) Evaluating the limits gives
WμoCox v2(y)vDS WμoCox vDS2
iD = L (vGS-VT)v(y) -
2 0 iD = L (vGS-VT)vDS -
2
Increasing
values of vGS
vDS
Fig. 110-04
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas. vDS
diD μoCoxW
dvDS = L [(vGS-VT) - vDS] = 0
Cutoff Saturation Active
T
V
vDS(sat) = vGS - VT
S-
vG
S=
Useful definitions:
vD
0 vGS
μoCoxW K’W 0 VT Fig. 3.2-4
L = L =
CMOS Analog Circuit Design © P.E. Allen - 2006
Illustration of the Need to Account for the Influence of vDS on the Simple Sah Model
Compare the Simple Sah model to SPICE level 2:
25μA
2
K' = 44.8μA/V
20μA 2
k = 0, v DS(sat) K' = 44.8μA/V
= 1.0V k=0.5, v DS(sat)
= 1.0V
15μA
iD
10μA SPICE Level 2
K' = 29.6μA/V 2
5μA k = 0, vDS(sat)
= 1.0V
0μA
0 0.2 0.4 0.6 0.8 1
vDS (volts)
VGS = 2.0V, W/L = 100μm/100μm, and no mobility effects.
To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS - VT
vDS(sat) = 1 + k
Therefore, in the saturation region, the drain current is
WμoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8μA/V2, excellent correlation is achieved with SPICE 2.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 1 (12/20/06) Page 3.1-12
;;;
Channel modulation effect: VG > VT VD > VDS(sat)
As the value of vDS increases, the
;;;;;;;
B S
effective L decreases causing the
Depletion
current to increase. Polysilicon
;;;;;;;
Region
p+ n+ n+
Illustration:
Leff
0.4
PMOS
0.3
0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6
Most analog designers stay away from minimum channel length to get better gains and
matching at the sacrifice of speed.
p+ n+ n+
+ voltage to change the surface
potential (-2F) p- substrate
Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage
VBS = 0
ID
vDS > vGS-VT
VGS
vGS
VT0 VT1 VT2 VT3
060612-02
In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:
Silicon Constants
MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.25μm CMOS n-well):
SUBTHRESHOLD MODEL
Large-Signal Model for Weak Inversion
The electrons in the substrate at the source side can be expressed as,
s
np(0) = npoexpVt
The electrons in the substrate at the drain side can be expressed as,
-v
s DS
np(L) = npoexp Vt
VGS<VT
The boundary between nonsaturated
and saturated is found as,
Vov = VDS(sat) = VON = VGS -VT = 2nVt 0 vDS
0 1V
Fig. 140-03
5x103
An expression for the electron drift 105 106 107
velocity as a function of the electric Electric Field (V/m) Fig130-1
field is,
μn E
vd 1 + E/Ec
where
vd = electron drift velocity (m/s)
μn = low-field mobility ( 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
CMOS Analog Circuit Design © P.E. Allen - 2006
Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,
(VGS-VT)
1
V’DS(sat) = 1 + 2(VGS-VT -1 (VGS-VT)1 -
2 + ···
if
(VGS-VT)
2 <1
Therefore,
(VGS-VT)
V’DS(sat) VDS(sat) 1 -
2 + ···
Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence
of velocity saturation.
0
0.5 1 1.5 2 2.5 3
vGS (V) Fig130-2
Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.
SiO2
Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig120-06
Gate
Drain-gate overlap
Channel capacitances:
Source-gate overlap
capacitance CGS (C1) capacitance CGD (C3) C2 = gate-to-channel = CoxWeff·(L-2LD) =
Gate CoxWeff·Leff
FOX FOX
Source Drain C4 = voltage dependent channel-
Gate-Channel Channel-Bulk
Capacitance (C2)
Bulk
Capacitance (C4)
bulk/substrate capacitance
Fig. 120-09
Gate
FOX C5 Source/Drain C5 FOX
Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 10-12 220 10-12 F/m
CGDO 220 10-12 220 10-12 F/m
CGBO 700 10-12 700 10-12 F/m
CJ 560 10-6 770 10-6 F/m2
CJSW 350 10-12 380 10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 1 (12/20/06) Page 3.1-32
;;;
Expressions for CGD, CGS and CGB
Cutoff
Cutoff Region: VB = 0 VS = 0 VG < VT VD > 0
CGS
CGB = C2+2C5 = Cox(Weff)(Leff) Polysilicon
CGD
+ 2CGBO(Leff) p+ n+ CGB n+
CGS = C1 Cox(LD)Weff = CGSO(Weff)
;;;
p- substrate
CGD = C3 Cox(LD)Weff = CGDO(Weff)
Saturated
Saturation Region: VB = 0 VS = 0 VG >VT VD >VG -VT
CGB = 2C5 = CGBO(Leff) CGS
Polysilicon
CGD
CGS = C1+(2/3)C2 =
p+ n+ n+
;;;
Cox(LD+0.67Leff)(Weff)
p- substrate Inverted Region
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 Cox(LD)Weff) = CGDO(Weff) Active
;;;
VB = 0 VS = 0 VG >VT VD <VG -VT
Nonsaturated Region: CGS
Polysilicon
CGD
CGB = 2 C 5 = 2CGBO(Leff)
p+ n+ n+
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff p- substrate Inverted Region
Fig120-11
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
CMOS Analog Circuit Design © P.E. Allen - 2006
tox(min) tox(max)
060225-01
3.) Process biases – differences between the drawn and actual dimensions due to process
(etching, lateral diffusion, etc.)
Drawn Dimension
Actual Dimension
060225-03
VOLTAGE VARIATION
What is Voltage Variation?
Voltage variation is the influence of power supply voltage on the component.
(There is also power supply influence on the circuit called power supply rejection ratio,
PSRR. We will deal with this much later.)
Power supply variation comes from:
1.) Influence of depletion region widths on components.
2.) Nonlinearity
3.) Breakdown voltage
Note: Because the large-signal model for the MOSFET includes all the influences of
voltage on the transistor, we will focus on passive components except for breakdown.
Depletion region
STI STI
n- well
n-well
p- substrate
As the voltage at the terminals of the resistor become smaller than the n-well potential,
the depletion region will widen causing the thickness of the resistor to decrease.
L
R = tW VR
where VR is the reverse bias voltage from the resistor to the well.
This effect is worse for well resistors because the doping concentration of the resistor is
smaller.
Voltage coefficient for diffused resistors 200-800 ppm/V
Voltage coefficient for well resistors 8000 ppm/V
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 2 (12/20/06) Page 3.2-7
Voltage Nonlinearity
Conductivity modulation:
As the current in a resistor increases, the conductivity becomes modulated and the
resistance increases. i
i= v
Example of a n-well resistor: R
0.1A
Conductivity
modulation
v
060311-01
TEMPERATURE VARIATIONS
Models for Voltage Dependence of a Component
1.) ith-order Temperature Coefficients
As for voltage, the temperature dependence can be expressed as,
y(T = T0) y(T0) + a1(T- T0) + a2(T- AT0)2+ a3(T- T0)3 + ···
where the coefficients, ai, are defined as,
df(T) | 1 d2f(T) |
a1 = dT T=T0 , a2 = 2 dT2 T=T0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature coefficients.
2.) Fractional Temperature Coefficient or Temperature Coefficient
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional temperature coefficient, TCF, which is defined as,
1 df(T) |
TCF(T=T0) = f(T=T0) dT T=T0 parts per million/°C (ppm/°C)
or more simply,
1 df(T)
TCF = f(T) dT parts per million/°C (ppm/°C)
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 2 (12/20/06) Page 3.2-9
-4T
VGS – VT0 - (T-To) = 3 VGS(ZTC) = VT0 - To - 3
Let K’ = 10μA/V2, W/L = 5 and VT0 = 0.71V.
At T=27°C(300°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(300°K)=1.63V
At T = 27°C (300°K), ID = (10μA/V2)(5/2)(1.63-0.71)2 = 21.2μA
At T=200°C(473°K),VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(473°K)=1.76V
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 2 (12/20/06) Page 3.2-11
275°C
60 300°C
ID (A)
40
150°C
275°C 250°C 200°C
Zero TC Point
20 25°C
100°C
0
0 0.6 1.2 1.8 2.4 3
VGS (V) 0600613-01
;;;
VG > VT VD > VDS(sat)
VGS>VT:
;;;;;;;
B S
Depletion
Polysilicon
;;;;;;;
Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-5
VGS<VT:
;;;
VG <VT VD > VDS(sat)
;;; ;;
B S
Depletion
Polysilicon
;;; ;;
Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-6
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 2 (12/20/06) Page 3.2-13
Go
iD Is = qA
Lp + Ln L N = KT 3exp Vt
Differentiating with respect to temperature gives,
V
V
10-5
200°C Data
10-6 Symbol Min. L
6 μm
250°C
10-7
Leakage Current (A)
5 μm
4 μm
10-8 IR 2 μm
50μm
Lmin 100°C
10-9 1V
Theory
10-10 matched
at 150°C Generation-
Diffusion Recombination
10-11
Leakage Leakage
Dominant Dominant
10-12
1.8 2 2.2 2.4 2.6 2.8
-1
1000/T (°K ) Fig. 3.6-7
Theory:
VG(T)
Is(T) T exp kT 3
id = gmvgs
ID Q
vgs
vGS
VT VGS 060311-03
ΔiD ΔiDʼ Q
vgs
ΔVGS 060311-04
Small-Signal Characteristics:
The small signal model is a linearization of the large signal model at an operating point.
iD = 2 (vGS-VT)2(1+vDS) d + ID = 2 [vgs+(VGS-VT)]2[1+(vds+VDS)]
id+ID = 2 vgs2 + (VGS-VT)vgs + 2 (VGS-VT)2 + 2 vgs2vds + (VGS-VT)vgsvds
+ 2 (VGS-VT)2 vds + 2 vgs2VDS + (VGS-VT)vgsVDS + 2 (VGS-VT)2 VDS
Assume that vgs < VGS-VT, vds < VDS and <<1. Therefore we write:
id+ID (VGS-VT)vgs + 2 (VGS-VT)2vds + 2 (VGS-VT)2(1+VDS)
id = (VGS-VT)vgs+2 (VGS-VT)2vds = gmvgs+gdsvds and ID = 2 (VGS-VT)2(1+VDS)
iD | K’WVDS
K’W
gm = vGS Q = L (1+ V DS ) L VDS
diD | qID
gm = dvGS Q = nkT
diD | ID
gds = dvDS Q VA
Cgd id
G D
+ +
Cgs
vgs rds vds
gmvgs gmbsvbs
- -
Cgb S - S Cbd
vbs Cbs
+
B Fig120-13
NOISE MODELS
MOS Device Noise at Low Frequencies
D D
D
eN2
G B G in2 G * B
Noise Noise
S B Free
Free S
MOSFET MOSFET S
where
8kTgm(1+) KF ID
in =
2
3 + fSCoxL2 f (amperes2)
f = bandwidth at a frequency, f
gmbs
= gm
k = Boltzmann’s constant
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise
CMOS Analog Circuit Design © P.E. Allen - 2006
1/f noise
Thermal noise
fCorner log10 f
060311-06
S S
Circuit 1: Frequency Dependent Noise Model
ei2 Cgd
G D
*
vin ii2 Cgs vgs rds io2
gmvgs
S S
Circuit 2: Input-referenced Noise Model
2
gm2 2Cgs2
2Cgs2 in2 if Cgd < Cgs ii2 = gm2 in2
Cp Cp1 Cp2
i
1.) Large signal i = Rv
Conductivity
modulation
v
2.) Small signal 060311-01
v = Ri
3.) Noise
en2 = 4kTR or in2 = 4kTG
CAPACITOR
Capacitor Models Rp
One of the parasitic capacitors
i C(v) is the top plate and the other is
+ − associated with the bottom
Cp v plate.
Cp
060315-03
C
1.) Large signal Linear
Nonlinear
v
2.) Small signal 060315-04
q = Cv i = C(dv/dt)
060315-05
INDUCTOR
Inductor Models v
L(i) R
R = losses of the inductor + −
Cp = parasitic capacitance to ground i
Cp Cp
Rp = losses due to eddy currents caused by
Rp Rp
magnetic flux
1.) Large Signal L 060316-03
Linear
Nonlinear
i
2.) Small signal 060316-04
d di
= Li dt = v = L dt
i1 M i2 i1 L1-M L2-M i2
3.) Mutual inductance
di1 di2 + + + +
v1 L1 L2 v2 v1 M v2
v1 = L1 dt + M dt M
k= L L − − − −
di1 di2 1 2 060316-05
v2 = M dt + L2 dt
INTERCONNECTS
Types of “Wires”
1.) Metal
Many layers are available in today’s technologies:
- Lower level metals have more resistance (70 m/sq.)
- Upper level metal has the less resistance because it is thicker (50 m/sq.)
2.) Polysilicon
Better resistor than conductor (unpolysicided) (135/sq.)
Silicided polysilicon has a lower resistance (5/sq.)
3.) Diffusion
Reasonable for connections if silicided (5/sq.)
Unsilicided (55/sq.)
4.) Vias
Vias are vertical metal (tungsten plugs or aluminum)
- Connect metal layer to metal layer (3.5/via)
- Connect metal to silicon or polysilicon contact resistance (5/contact)
CMOS Analog Circuit Design © P.E. Allen - 2006
050319-02
Capacitance of Wires
Self, fringing and coupling capacitances:
Wide Spacing Minimum Spacing
CCoupling CCoupling
CFringe CFringe
Ground plane CSelf
050319-03
5V
n-substrate
M2
vout p-well
vin Poly
Metal
M1 Ground
p+
Each square is
1m x 1m
n+
050319-04
Assuming minimum spacing and 40μm of coupling gives Ccoupling = 3.4fF. The RHP
zero is given by,
gm 775μS
RHP zero = Ccoupling + Cgd = 6.4fF = 1.21x1011 radians/sec.(19.3 GHz)
Electromigration
Electromigration occurs if the current density is too large and the pressure of carrier
collisions on the metal atoms causes a slow displacement of the metal.
Black’s law:
1
MTF = AJ 2 e(Ea/kTj)
Metal 050304-04
Where
A = rate constant (cm4/A2/hr)
J = current density (A/cm2)
Ea = activation energy in electron volts (0.5eV for Al and 0.7eV for Cu doped Al)
k = Boltzmann’s constant (8.6x10-5 eV/K)
Electromigration leads to a maximum current density,Jmax. Jmax for copper doped
aluminum is 5x105 A/cm2 at 85°C.
If t = 10,000 Angstroms and Jmax = 5x105 A/cm2, then a 10μm wide lead can
conduct no more than 50mA at 85°C.
n-well p-well
DC Ground
Substrate
What is a Ground?
Ground is simply another power supply whose value is supposed to be zero and is used as
a reference for all other voltages.
• DC ground is a point in the circuit where the DC voltage is supposed to be zero.
• AC ground is a point in the circuit where the AC voltage is supposed to be zero.
C2
AC Ground
t=0
- VDD
Vout DC and AC
Vin C1 +
Ground
AC Ground VSS
050305-03
IA IA+IB IA+IB+IC
Better:
Circuit Circuit Circuit
A B C IC
R
2R IB
3R IA
Best:
Circuit Circuit Circuit
A B C
R IA R IB R IC
050305-04
Kelvin Connections
Avoid unnecessary ohmic drops.
A B A B
X Y
Ohmic Connection Kelvin Connection 041223-12
Present Solution
Keep circuit separate by using multiple substrates and put the multiple substrates in the
same package.
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground
n+ channel vout Analog Ground
stop (1 Ω-cm)
;;;;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
p+ channel stop (1Ω-cm)
n- well "AC ground"
Hot Back-gating due to a
iD
Carrier momentary change in
Put substrate connections reverse bias
as close to the noise source
as possible ΔiD
ID
"AC ground" ΔiD
vGS
p- substrate (10 Ω-cm) VGS
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground vout Analog Ground
;;;;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
;;
VDD
vin vout
L1
Cs1
n- well
Digital Ground VDD(Digital)
;;;;;;
;;;;;
vin vout
Cs3 Cs2
vin vout Rs1 Substrate
;;;;;;
;;;;;
Rs2
Rs3
p+ n+ n+ p+ p+ n+
n- well Cs4
;;;;;
Hot Cs5
Carrier Coupling
Hot
L2 L3
Carrier Coupling
Coupling
;
RL Substrate Noise
vin vout
VGS VDD
VDD(Analog)
vin RL RL
vout
vout
;;;
VGS Analog Ground L4 CL
;;;
L6
n+ n+ p+
VGS
Cs6 Rs4 Cs7
Substrate
Cs5
L5
Inductor
Substrate BJT
;;;;;;;;
Collector Base Emitter Collector
n+ p+ n+ n+
p- well
Fig. SI-04
Heavily Lightly Intrinsic Lightly Heavily Metal
Doped p Doped p Doping Doped n Doped n
Also, there is coupling from power supplies and clock lines to other adjacent signal lines.
CMOS Analog Circuit Design © P.E. Allen - 2006
Number of Samples
i=1
9
8
7
6
5
4
3
2
1
0 X
0 1 2 3 4 5 6 7 8 9 1011121314
041005-01
253
m = 40 = 6.325 s = 2.115
Types of Mismatches
1.) Those controlled or influenced by electrical design
- Transistor operation
- Circuit techniques
- Correction/calibration techniques
2.) Those controlled or influenced by physical design
- Random statistical fluctuations (microscopic fluctuations and irregularities)
- Process bias (geometric variations)
- Pattern shift (misalignment)
- Diffusion interactions
- Stress gradients and package shifts
- Temperature gradients and thermoelectrics
- Electrostatic interactions
ELECTRICAL MATCHING
Matching Principle
Assume that two transistors are matched (large signal model parameters are equal). Then
if all terminal voltages of one transistor are equal to the terminal voltages of the other
transistor, then the terminal currents will be matched.
iC1 iC2 iD1 iD2
iB1 iB2
Q1 Q2 M1 M2
iE1 iE2
041005-02
Note that the terminals may be physically connected together or at the same potential but
not physically connected together.
M3 M4 iD1 iD2
M3 M4
+ M1 VB M2 + M1 M2
Vio Vio
VB M1 M2 - -
M5 M5
041005-03
Cascode current mirror:
The key transistors are M1 and M2. The gates and sources are physically connected
and the drains are equal due to M3 and M4 gate-source drops. As a result, iD1 will be
very close to iD2.
Differential amplifier:
When iD1 and iD2 are equal, the fact that the drains of M1 and M2 are equal should
give the smallest value of the input offset voltage, Vio.
Note: Since the drain voltages of M3 and M4 in both circuits are not necessarily equal,
the gate-source voltages of M3 and M4 are not exactly equal which cause the drain
voltages of M1 and M2 to not be exactly equal.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 5 (12/20/06) Page 3.5-9
Gate-Source Matching
Not as precise as the previous principle but useful for biasing applications.
A. If the gate-source voltages of two or more FETs are iD1 iD2
equal and the FETs are matched and operating in the M1 M2
W2
W1
saturation region, then the currents are related by the W/L L + + L2
1
ratios of the individual FETs. The gate-source voltages vGS1 vGS2
may be directly or indirectly connected. - -
Fig. 290-02
K’W1 2K’iD1
iD1 = 2L1 (vGS1-VT1)2 (vGS1-VT1)2 = (W1/L1)
K’W2 2K’iD2 iD1
iD2 = 2L2 (vGS2-VT2)2 (vGS2-VT2)2 = (W2/L2) W1
+ L1
vGS1
W2
W1
W1/L1
-
If vGS1 = vGS2, then L2 iD1 = L1 iD2
or iD1 = W2/L2 iD2
iD2
M2
W2
B. If the drain currents of two or more transistors are equal and the trans- + L2
vGS2
istors are matched and operating in the saturation region, then the gate- -
Fig. 290-03
source voltages are related by the W/L ratios (ignoring bulk effects).
W2/L2 W2 W1
If iD1=iD2, then vGS1 = VT1+ W1/L1 (vGS2-VT2) or vGS1=vGS2 if L2 = L1
CMOS Analog Circuit Design © P.E. Allen - 2006
Form Provide
This overdrive can be expressed, Channel Current
2ID
VON = VDS(sat) = K’(W/L) 0
0 VT
vGS
VGS 041007-09
f
0 fc 2fc 3fc
VB(f)
f
0 fc 2fc 3fc
VC(f)
f
0 fc 2fc 3fc Fig. 7.5-8
Self-Calibration Techniques
The objective of self-calibration is to increase the matching between two or more
components (generally passive).
The requirements for self-calibration:
1.) A time interval in which to perform the calibration
2.) A means of adjusting the value of one or more of the components.
041007-05
Self-calibration can typically improve the matching by a factor of 2-3 bits (4-8).
041007-06
Assume the amplifier has a DC input offset voltage of Vio. The following shows how to
calibrate one (or both) of the capacitors.
C1 C2
vOUT vx -
+ - - - + +
vOUT
VRef -Vio Vio
+
+ - C1
VRef Vio C2 VRef VRef -Vio
- +
Vio Vio
Variable Components
The correction circuitry should be controlled by logic circuits so that the correction can
be placed into memory to maintain the calibration of the circuit during application.
Implementation for C1 and C2 of the previous example:
C1 C1 C1 C1 C2 C2 C2 C2
C1 1- 1 2K 2K+1 2K+2 2N C2 1- 1 2K 2K+1 2K+2 2N
2K 2K
S1 S2 S3 SN S1 S2 S3 SN
Capacitor C1 Capacitor C2
041007-08
Additional circuitry:
Every self-calibration system will need additional logic circuits to sense when the value
of vx changes from positive to negative (or vice versa) and to store the switch settings in
memory to maintain the calibration.
e t1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 Tim
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
VRef
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
Tim S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
e t2
All resistor are approximately equal
valued to within some tolerance
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
041010-01
†
L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters, IEEE J. of Solid-State Circuits, vol. 24, no. 2, April 1989, pp. 267-273.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 5 (12/20/06) Page 3.5-17
Error (%)
Normal
Error when dynamic +1
element matching is not 0 t
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
used -1
Elements → 1 3 2 3 1 2 1,2 2,3 1,3 1,2 1,3 2,3 1,2,3
+3
Matching Error (%)
+2
Dynamic Element
PHYSICAL MATCHING
Review of Physical Matching
We have examined these topics in the previous chapter. To summarize, the sources of
physical mismatch are:
- Random statistical fluctuations (microscopic fluctuations and irregularities)
- Process bias (geometric variations)
- Pattern shift (misalignment)
- Diffusion interactions
- Stress gradients and package shifts
- Temperature gradients and thermoelectrics
- Electrostatic interactions
†
Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 5 (12/20/06) Page 3.5-21
†
Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 5 (12/20/06) Page 3.5-23
Mismatched Transistors
Assume two transistors have vDS1 = vDS2, K1’ K2’ and VT1 VT2. Therefore we have
iO K2’(vGS - VT2)2
iI = K ’(v - V )2
1 GS T1
How do you analyze the mismatch? Use plus and minus worst case approach. Define
K’ = K’2-K’1 and K’ = 0.5(K2’+K1’) K1’= K’-0.5K’ and K2’= K’+0.5K’
VT = VT2-VT1 and VT = 0.5(VT1+VT2) VT1 =VT -0.5VT and VT2=VT+0.5VT
Substituting these terms into the above equation gives,
K’ VT 2
iO (K’+0.5K’)(vGS - VT - 0.5VT )2 1 + 2K’ 1 - 2(vGS-VT)
Geometric Effects
How does the size and shape of the transistor effect its matching?
Gate Area:
CVth CKp CW/W
Vth = W L Kp = K’ W L W/W = WeffLeff
eff eff eff eff
where CVth, CKp and CW/W are constants determined by measurement.
Values from a 0.35μm CMOS technology:
10.6mV·μm 8.25mV·μm
Vth,NMOS = W L Vth,PMOS = W L
eff eff eff eff
and
W W
0.0056·μm 0.0011·μm
W NMOS = W L W PMOS = W L
eff eff eff eff
The above results suggest that PMOS devices would be better matched than NMOS
devices in this technology.
† Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
BSIM2 Model
Generic composite expression for the model parameters:
LX WX
X = Xo + Leff + Weff
where
Xo = parameter for a given W and L
LX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:
Mobility
• Mobility reduction by the vertical and the lateral field
Drain Current
• Velocity saturation
• Linear region drain current
• Saturation region drain current
• Subthreshold current
μoCoxWeff kT evGS-Vt-Voff
1 - eqVDS/kT
iDS = Leff ·
q
n ·
where NB
Voff = VOF + VOFB ·vBS + VOFD ·vDS and n = NO + PHI - v + ND ·vDS
BS
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 6 (12/20/06) Page 3.6-6
5 6 7 8
Weff,2
1 2 3 4
Weff,1
Leff
Leff,1 Leff,2 Leff,3 Leff,4
• A long, wide device is used as the base to add geometry effects as corrections.
• Procedure:
1.) Oxide thickness and the differences between the drawn and effective channel
dimensions are provided as process input.
2.) A long, wide device is used to determine some base parameters which are used as
the starting point for each individual device extraction in the second phase.
3.) In the second phase, a set of parameters is extracted independently for each device.
This phase represents the fitting of the data for each independent device to the intrinsic
equation structure of the model
4.) In the third phase, the compiled parameters from the second phase are used to
determine the geometry parameters. This represents the imposition of the extrinsic
structure onto the model.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 6 (12/20/06) Page 3.6-8
100μA
10μA iD +
vGS
1μA -
ID(M1)
100nA
10nA
1nA
100pA
0V 0.4V 0.8V 1.2V 1.6V 2V
VGS
BSIM3 Model
The background for the BSIM3 model and the equations are given in detail in the text
MOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer Academic
Publishers, 1999.
The short channel effects included in the BSIM3 model are:
• Normal and reverse short-channel and narrow-width effects on the threshold.
• Channel length modulation (CLM).
• Drain induced barrier lowering (DIBL).
• Velocity saturation.
• Mobility degradation due to the vertical electric field.
• Impact ionization.
• Band-to-band tunnelling.
• Velocity overshoot.
• Self-heating.
1.) Channel quantization.
2.) Polysilicon depletion.
INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of
MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: TSMC 0251P5M.
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.36/0.24
Vth 0.54 -0.50 volts
SHORT 20.0/0.24
Idss 557 -256 uA/um
Vth 0.56 -0.56 volts
Vpt 7.6 -7.2 volts
WIDE 20.0/0.24
Ids0 6.6 -1.5 pA/um
LARGE 50.0/50.0
Vth 0.47 -0.60 volts
Vjbkd 5.8 -7.0 volts
Ijlk -25.0 -1.1 pA
Gamma 0.44 0.61 V0.5
K’ (Uo*Cox/2) 112.0 -23.0 uA/V2
CMOS Analog Circuit Design © P.E. Allen - 2006
Weff v
2
iD = K’
(v - V )v - DS
(1 + v ) (2)
Leff GS T DS 2 DS
where
VT = VT0 + [ 2|F| + vSB 2|F| ] (3)
vDS >VDSAT
Weak inversion
region 1/2
⎛ K ′ Weff ⎞
m= ⎜⎝ ⎟
2L eff ⎠
0 vGS
0 b′ =VT0 AppB-01
Comments:
• Stay away from the extreme regions of mobility degradation and weak inversion
• Use channel lengths greater than Lmin
These results indicate that the first (lowest value of VGS) data point is either bad, or at a
point where the transistor is in weak inversion. This data point will not be included in
subsequent analysis. Performing the linear regression yields the following results.
K'Weff
VT0 = 0.898 V 2
and 2Leff = 21.92 μA/V
vGS
VT0 VT1 VT2 VT3
FigAppB-02
By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line from
which the parameter can be extracted. In order to do this, VT must be determined at
various values of vSB using the technique previously described.
VSB =0V
0.5 0.5
(vSB +2 φF ) − (2 φF ) FigAppB-03
vDS
AppB-03
Using the values of K’, VT , , and extracted previously, use an appropriate extraction
procedure to find the value of adjusting the values of K’, VT , and as needed.
Comments:
• We will assume that the bulk will be connected to the source or the standard
relationship between VT and VBS can be used.
• The saturation voltage is still given by
VDS( sat) = VGS - VT
†
Anurag Kaplish, “Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm,” May 4, 2000, Special Project Report,
School of ECE, Georgia Tech.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Section 7 (12/20/06) Page 3.7-17