Next Generation eWLB

(embedded Wafer Level BGA) Packaging

by

Meenakshi Prashant, Kai Liu, Seung Wook Yoon

Yonggang Jin, Xavier Baraton, S. W. Yoon*, Yaojian Lin*, Pandi C.
Marimuthu*, V. P. Ganesh**, Thorsten Meyer** and Andreas Bahr**

STMicroelectronics STATS
*STATS ChipPAC
ChipPAC Ltd. **Infineon Technologies AG,
Ltd.
629 Lorong 4/6 10 Ang Mo Kio Street 65
10 Ang Mo Kio Street 168 Kallang Way
Toa Payoh #05-17/20Techpoint
65 #05-17/20 Techpoint Singapore 349253
Singapore 319521 Singapore
Singapore 569059569059

Copyright 2010. Reprinted from 2010 Electronics Packaging Technology

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 Next Generation eWLB (embedded Wafer Level BGA) Packaging

Yonggang Jin, Xavier Baraton, S. W. Yoon*, Yaojian Lin*, Pandi C. Marimuthu*,

V. P. Ganesh**, Thorsten Meyer** and Andreas Bahr**

STMicroelectronics, 629 Lorong 4/6 Toa Payoh, 319521 Singapore

*STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
**Infineon Technologies AG, 168 Kallang Way, 349253 Singapore
yonggang.jin@st.com

ABSTRACT forward with this trend, packaging semiconductor devices for

Demand for wafer level packaging (WLP) is being driven
by the need to shrink package size and height, simplify the
supply chain and provide a lower overall cost by using the
infrastructure of a batch process. Fan-in (FI)-WLP typically
has a limitation to be less than 6x6mm in order to pass board
level reliability requirements such as drop test and temperature
cycle due to the mismatch of Si material properties to the
PCB. However, the Fan-out (FO)-WLP, has been
developed and introduced into production to allow for higher
ball count WLP, by extending the package size beyond the
area of the chip. The most prominent type of FO-WLP is the
eWLB technology (embedded Wafer Level Ball Grid Array).
Currently 1st generation eWLB technology is available in the
industry.
This paper will highlight some of the recent advancements
in next generation eWLB technologies including multi-RDL,
thin eWLB and extra large eWLB as well as double-side with
vertical interconnection. These key technologies of next
generation eWLB enable 3D eWLB applications such as SoW
(SiP on Wafer) and 3D SiP. 3D eWLB can be implemented
with through silicon via (TSV) applications as well as discrete
component embedding. The process flow of next generation
eWLB fabrication, assembly and packaging challenges will be
discussed. This paper will also present some of the
achievements in package reliability, mechanical
characterization and performance.
handheld electronics has become more challenging than ever
before. Growing mismatch in interconnect gap, adding
different functional chips for different features and application
in similar system footprint and package size reduction to
increase battery size for extended usage has opened the
window for innovative embedding packaging technology.
To meet the above said challenges eWLB was developed
[1] which offers additional space for routing higher I/O chips
on top of Silicon chip area which is not possible in
conventional WLP or WLB. It also offers comparatively better
electrical, thermal and reliability performance at reduced cost
with possibility to address more Moore [decreasing
technology nodes with low-k dielectrics in SoC] and more
than Moore [heterogeneous integration of chips with different
wafer technology as SiP solution in multi die or 3D eWLB
approaches].
WLP applications are expanding into new areas and are
segmenting based on I/O count and device. The foundation of
passive, discrete, RF and memory device is expanding to logic
ICs and MEMS. The WLP segment has matured over the past
decade, with numerous sources delivering high-volume
applications across multiple wafer diameters and expanding
into various end-market products. With infrastructure and
high volumes in place, a major focus area is cost reduction.

INTRODUCTION
Integrated Circuits fabricated on silicon is assembled in
different forms of electronic packages and are used
extensively in electronic products such as personal, portable,
healthcare, entertainment, industrial, automotive,
environmental and security systems. Current and future
demands of these electronic systems in terms of performance,
power consumption, reliable system at a reasonable cost are
met by developing advanced/appropriate silicon process
technology, innovative packaging solutions with use of chip-
package-system co-design, low cost materials, advanced
assembly and reliable interconnect technologies. In this
article packaging evolution for hand held application is Figure 1. Driving force for wafer level packaging
discussed with special focus on next generation chip
embedding technology called eWLB in detail.
One of the most well known examples of a fan-out WLP
In just one decade hand phone has transformed from a structure is eWLB technology by Infineon Technologies AG.
simple communication device into more complex system This technology uses a combination of front- and back-end
integrating features that allow customers to use it as a manufacturing techniques with parallel processing of all the
multipurpose gadget. The carrier technology has jumped from chips on a wafer, which can greatly reduce manufacturing
1G to 3G, changing at the rate of every two years and with costs. Its benefits include a smaller package footprint
room for potential growth with global adoption. Moving
978-1-4244-8561-1/10/$26.00 2010 IEEE 2010 12th Electronics Packaging Technology Conference
520
compared to conventional leadframe or laminate packages,
medium to high I/O count, maximum connection density, as
well as desirable electrical and thermal performance. It also
offers a high-performance, power-efficient solution for the
wireless market.[2]
Figure 2. Comparison of FI-WLP and eWLB (FO-WLP)
eWLB TECHNOLOGY
eWLB technology is addressing a wide range of factors. At
one end of the spectrum is the packaging cost along with
testing costs. Alongside these are physical constraints such as
its footprint and height. Other parameters that were considered
during the development phase included I/O density, a
particular challenge for small chips with a high pin count; the
need to accommodate systems in package (SiP) approaches,
thermal issues related to power consumption and the device's
electrical performance (including electrical parasitic and
operating frequency).
Figure 3. eWLB wafer after packaging with
reconstitution, RDL and backend processes.
The obvious solution to the challenges was some form of
WLP. But two choices presented themselves: fan-in or fan-
out. Fan-in WLP is an interconnection system processed
directly on the wafer and compatible with motherboard
technology pitch requirements. It combines conventional
front- and back-end manufacturing techniques, with parallel
processing of all chips. There are three stages in the process.
Additional fab steps create an interconnection system on each
die, with a footprint smaller than the die. Solder balls are then
applied and parallel testing is performed on the wafer. Finally,
wafers are sawn into individual units, which are used directly
on the motherboard without the need for interposers or
underfill. The eWLB approach should not be confused with
bumped flip chip devices which have a finer pitch, smaller
bumps and hence need underfill.
521
Figure 4. Schematics of construction of eWLB.
eWLB, meanwhile, is a fan-out process. The die is
surrounded by a suitable material, which spreads the package
footprint outside the die. Tested good dice are embedded in an
artificial plastic wafer (reconstituted wafer) using a wafer
level molding technique. Front end isolation and metallization
processes are then used to fan-out the interconnections to the
surrounding area with lithography and patterning wafer level
processes. Again, solder balls are applied and parallel testing
is performed on wafer. The reconstituted wafer is then sawn
into individual units, which are packed and shipped. With the
fan-in approach, the number of interconnects and their pitch
must be adapted to the chip's size. eWLB, by contrast,
supports a fan out area which is adaptable and which has no
restriction on ball pitch.
Advantage of eWLB
Next generation variations of the eWLB enabling two or
more layers of routing, expanding the package size to
12x12mm, allowing for thinner packages, side by side chips
within the eWLB, and eventually double sided Package on
Package (PoP) eWLB are being jointly developed with our
technology partners for introduction in the near future.
The current BGA package technology is limited by the
organic substrate capability. Moving to eWLB helps
overcome such limitations and also simplifies the supply
chain. Building the routing layers on package itself allows
for higher integration and routing density with less metal
layers. eWLB is a next generation platform that will support
future integration, particularly for wireless devices and this
packaging technology has a number of important features.
Transition to eWLB packaging technology enables a
significant reduction in recurring costs by eliminating the need
for tool up of expensive substrates.
BGA packaging also faces a challenge with technology
nodes beyond 65nm as the device performance density drives
the need for flip chip. But advanced flip chip nodes drive fine
pitch combined with weaker low-k dielectric structures
resulting in flip chip packages that has narrow process margin.
In addition, there is a big trend in being environmentally
friendly, driving lead free and halogen free, or green, material
sets. With ultra low-k and interconnects pitch becoming
smaller and smaller and with the shift to lead free materials,
the technical limitations faced by the packaging industry are
becoming more challenging. eWLB technology provides a
2010 12th Electronics Packaging Technology Conference
window for packaging next generation devices in a generic,
lead-free/halogen free, green packaging scheme.
NEXT GENERATION; 3D eWLB TECHNOLGOY
The first generation of eWLB technology was designed for
a single side and 1layerRDL approach. To address the
advanced requirements in the market for higher performance
and design complexity, new technical items and envelops
should be developed and implemented into the current eWLB
technology as shown below;
Multi-layer RDL eWLB: More than one metal layer can
be present in both sides;
Thin eWLB : Package thickness is reduced to 0.5mm
Multichip eWLB : More than one chip is embedded
Large size eWLB: Package size is increased to 12x12mm2
Double-side eWLB with vertical interconnection: Both
sides of reconstituted wafer have isolation and metal layers,
connected by means of conductive vias in the plastic portion
of the wafer
Multi-layer RDL eWLB Packaging
In situations where a device may have an interconnect pad
arrangement or a flip chip or wafer level component, an
additional layer of lateral connections may be employed to
rearrange the connections in a manner suitable for wafer level
processing. This additional layer is known as a redistribution
layer or RDL and fabricated from a thin layer of metal with
dielectrics in between.
(a)
(b)
Figure 5. (a) Photo and (b) SEM micrograph of cross-
section of 2-layer RDL eWLB.
RDL is for higher electrical performance and complex
routing to meet electrical requirements. It also can provide
embedded passives (R, L, C) using a multi-layer structure.
Excellent performance of transmission lines (TMLs) was
reported in manufacturing eWLB (Insertion loss 0.1 dB/mm
522
@ 10GHz, 0.25 dB/mm @ 60GHz)[4]. Inductors in eWLB
offer significantly better performance compared to inductors
in standard on-chip technologies. Further improvement of the
quality factor of the integrated capacitors by using low-loss
thin-film dielectrics on eWLB was reported as well[5]. There
was another report that a 77 GHz SiGe mixer packaged as an
eWLB had excellent high frequency electrical performance
due to the small contact dimensions and short signal pathways
which decreased parasitic effects[6].
Thin eWLB Packaging
For mobile and handheld applications, portability is a
critical factor for product selection. The thinner package can
provide better board level reliability as well as lighter and
thinner profile in system level. Using advanced thinning
technologies, eWLB was thinned down to 250 m thickness as
shown in Figure 8. The critical technical challenges were
handling the thin wafer and grinding and removing of
Si/epoxy material together using the same process steps. There
was found more than 60% increase in TCoB (temperature
Cycle on Board) performance with thinner eWLB. Drop
reliability also improved significantly.
Figure 6. Thin eWLB after eWLB packaging process.
Multi-chip eWLB Packaging
Side-by-side multichip packaging can provide more design
flexibility for SiP applications because a chip designer has
more freedom in pad location as well as circuit block
allocation. 3D eWLB technology utilizes very fine pitch metal
line width and space as well as multi-layer RDL process, so it
provides better technical solutions for multi-chip packaging.
It can be used for various combinations such as, RF receiver
and digital device, PA (power amplifier) and IPD (integrated
passive devices) and memory and controller. eWLB uses fine
pitch metallization and well controlled interconnection with
wafer fab lithography process thus it has great advantage to
provide better electrical performance compared to wire-
bonding and organic substrate technology.
Extra Large eWLB Packaging
FI-WLP has its size limitation of ~5x5mm due to board
level reliability (BLR) requirement. For 1st gen eWLB of
8x8mm, it passed successfully industry BLR standard tests.
12x12 mm eWLB packages were designed and fabricated as
2010 12th Electronics Packaging Technology Conference
shown in Fig.7 with 1, 2 and 3 dies. It I was found that
12x12mm eWLB passed drop reliability test. To improve
further TCoB reliability, various approaches are explored and
studied in design, process as well as materials with
computational simulation work. With optimmized design works,
12x12mm eWLB successfully passed TC CoB 500 cycles (-
40/125C, 2cycles/hr.).
postage stamp, represents the beest of both worlds. SiP, as the
name implies, is a technologyy that allows the placement of
several integrated circuits inn one package, providing a
complete set of device electtronics in a small area. This
technique saves board space byy integrating devices that were
once spread farther apart on thee circuit board.

(a) (b) (a)

(c) (b)

Figure 8. Applications of double-side eWLB

packaging; (a) Package-on-packkage (PoP) and (b) System-
on-Wafer (SOW).
Figure 7. 12x12mm eWLB packagees with (a) 1-die
(10x10mm2) , (b) 2-die and (c) 3-die .

Double-side eWLB Packaging

There is 3D eWLB approach with verticcal interconnection,
both sides of the reconstituted wafer will have
h isolation and
metal layers, connected using conductive vias.
v It enables 3D
SiP or 3D micro module. Key to the miniatuurization of 3D SiP
is the integration of the packaging steps as a functional part of
the die and system solution. The PBGA replaced the lead
frame by a printed circuit board (PCB) subsstrate, to which the Figure 9. SEM microograph of 3D vertical
die was electrically connected by wire bonding or flip chip interconnection with prefilled via
v for Package-on-package
technology, before covering with molding compound. eWLB (PoP) eWLB packaging;
takes the next step, eliminating the PCB, as well as the need to
use wire-bonding or flip-chip bumps to establish
e electrical
contacts. Without a PCB, the package is inherently
i thinner,
without thinning the die when lower profiless are required.
PoP and SOW takes this integration a sttep further, placing
one package on top of another for greater g integration
complexity and interconnect density. eWLB B makes it a very
flexible choice. eWLB technology also offerso procurement
flexibility, lower cost of ownership, betterr total system and
solution costs and faster time to market. Each step along the
path from SiP to PoP (Package on paackage) to eWLB
represents improvements in these two areeas. Each of these
packages fit unique niches. For examplee, if size is most
important, then stacked die will yield smaller packages.
Moving into PoP increases board space, but b improves cost Figure 10. Package-on--package (PoP) eWLB
structure. eWLB, with its potential to draamatically improve packaging with prefilled via.
cost effectiveness and reduce entire system ms to the size of a

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 Fig.9 shows cross-section of the prefilled via approach for
3D vertical interconnection. It was fabricated with PCB/PWB
technology and assembled using eWLB process. Fig. 10
shows eWLB PoP sample after top eWLB attachment on
bottom eWLB. Top package has 8x8mm and bottom package
size is 12x12mm2 with 3-die multichip.

Package Level Reliability Results

Table 1 shows the package level reliability result of each
next generation 3D eWLB packages. They passed JEDEC
(Joint Electron Device Engineering Council) standard package
reliability test such as MSL (Moisture Sensitivity Level) 1
with Pb-free solder conditions. Test vehicles have 8x8mm
Package with 5x5mm daisy-chain die and 0.5mm pitch. Total
ball I/O is 192 and lead-free solder ball is used. All next
generation eWLB packages successfully passed all industry
standard package level reliability with ball shear test and Figure 11. Weibull Plot of TCoB reliability of next
OS(open-short) test. generation eWLB Packages.

Table 1. Package Level Reliability Results of next Warpage Behavior with Temperature Profile
generation eWLB packages. Among the 3D technologies, Package-on-Package (PoP) is
Condition Status increasingly becoming mainstream due to its flexibility of
MSL1 MSL1, 260C combination and sourcing. The top package to be stacked
- Pass using solder ball interconnects. For successful package on
JEDEC-J-STD-020D Reflow (3x)
Temperature Cycling (TC) package stacking with high assembly yield, warpage of both
after Precon -40C to 125C 1000x Pass the top and the bottom package are critical. If the warpage is
JESD22-A104 too large, open solder joints may occur between the bottom
HAST (w/o bias) after package and motherboard, or between the bottom package and
Precon 130C / 85% RH 96hrs Pass top package. Not only is the warpage at room temperature a
JESD22-A118 concern for co-planarity measurement as a control, but
High Temperature Storage warpage at solder reflow temperatures (up to 260C for lead-
(HTS) 150C 1000h Pass free solder) should also be considered since open solder joints
JESD22-A103 occur during solder solidification. As a result, warpage control
BST after Multiple Reflow 260C Reflow 20x Pass at both temperature extremes is critical for 3D PoP stacking.
* Tested by ball shear test and O/S test

Board Level Reliability Results

For drop reliability, next generation eWLB packages show
good drop reliability as reported in 1st gen eWLB. For 3D
eWLB packages described above, all passed industry standard
drop reliability tests (JEDEC. Fig. 12 shows Weibull plot of
next generation eWLB packages as consolidated data. It
shows quite comparable TCoB results even for 12x12mm
eWLB. Currently there is more works on improving large size
eWLB TCoB performance with design, structure, material,
solder ball and process optimization.
For thinned eWLB of 250um package body thickness
(total package height ~0.5mm), it showed significant
improvement of drop and TCoB performance. As shown in
Fig12, thinned one has two time longer TCoB life time
compared to standard thickness eWLB. It may due to
flexibility of thinned die as shown in Fig.6.
Figure 12. Comparison of warpage behavior of various
package types; fcFBGA, eWLB and EDS with temperature
profile.

Themo-Moire technology used for measure package

warpage with temperature profile. There is warpage

2010 12th Electronics Packaging Technology Conference

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behaviour result with various package types, fcFBGA, eWLB
and EDS (Embedded Die Substrate). As shown in picture,
eWLB showed almost flat during temperature profile and very
stable warpage behaviour. But other packages showed serious
warpage with direction change as shown in Fig. 12. Warpage
variation of thin eWLB was less than 10 m in measured
temperature range up to 260oC. This stable warpage
behaviour of eWLB is good for fine ball pitch SMT
applications as well as PoP or 3D approaches.
Further Wafer Level Integration with 3D eWLB for
Heterogeneous Functionality
There is a need for miniaturization at the IC, module (or
sub-system), and system levels. At the IC level, scaling
continues as it has over the last four decades according to
Moore's Law. In addition, 3D chip stacking technology with
through silicon vias (TSVs) has garnered a lot of attention
recently due to its potential in improving the performance,
form factor, cost, and reliability at the sub-system or module
level [7-8]. There is still a great deal of research and
development required to bring this hetero-integration
technology to cost-effective implementation with the required
reliability and performance needs. In addition to the module
level, we must focus on performance, form factor, cost, and
reliability of the entire system [9].
Figure 13. Total solutions for 3-D packaging with
eWLB, MEMS and TSV technology.
Although active and stacked ICs are a highly functional
and important component of the overall system, they are only
one set of components; many other components including
other actives, passives, power systems, wiring, and connectors
must be considered in a complete system. As a result, there is
a need to think at module and system levels and this need is
largely met by the current technology domain in the areas of
through silicon vias (TSVs), 3D stacking, and wafer level
packaging. There should be further study on integration,
focusing on TSVs, 3D stacking and 3D eWLB with better
electrical and thermal performance, greater system reliability,
and reduced form factor and overall cost. It will go far beyond
this to realize a truly seamless wafer level integrated 3D
packaging module as shown in Fig. 14, that will incorporate
aspects of 3D stacking, as well as Si package with embedded
passive, actives in 3D eWLB packaging with TSV, flip chip,
and micro-bump as well as 3-D WLPs.
525
CONCLUSION
Advanced packaging plays a crucial role in driving
products with increased performance, low power, lower cost
and smaller form factor. There are challenges associated in the
application of cost effective materials and processes for
various reliability requirements. The industry requires
innovation in packaging technology and manufacturing to
meet current demands and the ability to operate equipment in
high volume with large throughput.
eWLB technology is an enhancement to standard WLPs,
allowing the next generation of a WLP platform due to its fan-
out capability. The benefits of standard fan-in WLPs such as
low packaging/assembly cost, minimum dimensions and
height as well as excellent electrical and thermal performance
are true for eWLB as well. The ability to integrate passives
like inductors, resistors and capacitors into the various thin
film layers, active/passive devices into the mold compound
and 3D vertical interconnection opens additional design
possibilities for new Systems-in-Package (SiP) and 3D
stacked packaging. Moreover, next generation, 3D eWLB
technology provides more value-add in performance and
promises to be a new packaging platform that can expand its
application range to various types of devices as well as 3D
TSV integration for true 3D SiP systems.
As the world demand for portable and mobile electronics
has accelerated, the need to make semiconductors smaller,
faster, lighter and cheaper has never been greater. As
witnessed by the dramatic evolution of cellular phones,
product differentiation today is driven by ever-expanding
functionality, feature sets, multi-functionality and faster
communications. At the same time, consumers have made
clear their desires for feature-rich products in compact form
factors to enable maximum portability. Next generation 3D
eWLB technology is successfully enabling semiconductor
manufacturers to provide the smallest possible, highest-
performing semiconductors.
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