Systems Architecture

Lecture 3b: Review of Sequential Logic Circuits

Jeremy R. Johnson
Anatole D. Ruslanov
William M. Mongan

Lec 3b Systems Architecture 1

 Introduction
Objective: To understand how data can be stored in a
computer.

Sequential vs. Combinational Logic

Flip-flop
Timed flip-flop
Implementing computer memory
Review of the simple computer model

References: Dewdney, The New Turing Omnibus (Ch. 38 and 48).

Lec 3b Systems Architecture 2

 Combinational vs. Sequential Circuits
A combinational circuit is a logic circuit without any loops.
The same outputs are always computed for the same inputs.

A sequential circuit contains two-state memory elements

which can remember the state over time. The outputs
depend on both the inputs and the current state. The state
changes over time which is marked off in discrete steps by
pulses emanating from a clock.

The pulses coordinate activity.

The loops maintain the memorized state.

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 Flip-Flop (SR-Latch)
A sequential logic circuit with two states.
The two states are (Q=0, Q=1) and (Q=1,Q=0)
Provided the input (R = 0, S = 0) is not allowed, the flip-flop
can only be in one of these two states.

R
Q

Q
S

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 Flip-Flop States
The state (Q=0,Q=1) corresponds to storing a 0.
The state (Q=1,Q=0) corresponds to storing a 1.
If S (set) is 1, then the state is set to 1.
If R (reset) is 1, then the state is set to 0.
If R & S are 1, the state does not change.
Old Q R S Q Next Q
0 1 1 1 0
0 1 0 1 0 R
Q
0 0 1 1 1
1 1 1 0 1
1 1 0 1 0 Q
S
1 0 1 0 1

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 Flip-Flop States
The transitions of the flip-flop are conveniently described in
the following state transition diagram (finite state machine).
The arcs are labeled by the RS inputs that cause the
transition.
In the diagram, state 0 is when Q = 0 and Q = 1, and state 1 is when
Q = 1 and Q = 0.

01 10 10

1 0

11 01 11

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 A Clocked Flip-Flop

R
Q

clock

Q
S

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 n-bit Register

A state variable containing n bits

Built from an array of n flip-flops

State changes when load selected and the clock is high

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 n-bit Register

X0 R Q

S Q

R Q
X1

S Q

load clock

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 Memory Cell
read = 1/write = 0

R Q
input output

S Q

select
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 Memory
Input

N = 2k words each l bits

Inputs
k address bits
l data-in bits (for write) Address
flag to select read /write Memory Output

Outputs
l data-out bits (for read)
R/W
Built from N l array of memory cells
input, output, flag, select
Decoder used to decode address

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 Memory
read/write input input input input

D
e
c 1
o
d
e
r
7

output output output output

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 LOAD READ/
MAR WRITE
LOAD
PC Memory
INC
MUX s
0123

LOAD
IR(C) IR(O)
LOAD
MBR MUX 0
s 1
Decoder
0 LOAD
q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 1
x13 2
MUX AC
x1 x12 3 s
x2 x11 0
x3 x10 ALU MUX 1
x4 x9 s
x5 x8 LOAD AD
x7
t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 x6
INC CLEAR

Decoder T

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