Professional Documents
Culture Documents
EE IIT Madras
INDIAN INSTITUTE OF TECHNOLOGY MADRAS
Research Directions: Power Quality Research
Laboratory
THEORETICAL ASPECTS
Control Algorithms
(Generation of
Reference Quantities)
EE IIT Madras
INDIAN INSTITUTE OF TECHNOLOGY
MADRAS
Ph.D. Researchers
M.S. Researchers
M.Techs
EE IIT Madras
praveen.239
@gmail.com
haimuralimail
@gmail.com
INDIAN INSTITUTE OF TECHNOLOGY
MADRAS
Projects (Completed)
1. Power Quality Improvement using
Active Power Filters
2. Mitigation of unbalance and harmonics in power distribution
system using Static Var Compensators
Projects (Ongoing)
Future
Projects (Future)
1. Design and development of dedicated Custom Power Park driven by
innovative control algorithm with proper coordination of its devices
2. Development of Integrated Renewable Energy
Power Park with Coordinated Control and Embedded Power Quality Aspects
EE IIT Madras
INDIAN INSTITUTE OF TECHNOLOGY
MADRAS
EE IIT Madras
Power quality has a different meaning to different people. For
instance:
For Genco people it means that generator is not overrated in
terms of real and reactive power, it is not over heated etc.
For Transmission people, it means that more transmission
efficiency, less outage, proper flow of active and reactive power,
balanced and sinusoidal quantities over the transmission network
For Distribution people it means proper voltage of distribution
bus, load harmonics and power factor should not create threat to
utility etc.
Transients
Short Duration Variations <=> RMS variations
Long Duration Variations
Voltage Unbalance
Waveform Distortions
Voltage fluctuations
Power Frequency Variations
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TRANSIENTS
TRANSIENTS in power system refer events
which are undesirable and momentary in nature.
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TRANSIENTS CLASSIFICATION
Waveform Classification
gIMPULSIVE TRANSIENTS
g Lightning
gOSCILLATORY TRANSIENTS
g Capacitor Energization
g Restrike during Capacitor de-energization
g Line or Cable Energization
gMULTIPLE TRANSIENTS
g Current chopping
g Multiple strikes
g Repetitive switching actions
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IMPULSIVE TRANSIENT
gIt is sudden and non-power frequency change in the
steady state condition of voltage or current or both that
is unidirectional in polarity either positive or negative
g It is characterized by the rise and decay times which
can be revealed by dominant frequency in their
spectral content. For example 1.250s 2000V
impulsive transient means that the transient rises from
zero to its peak of 2000V in 1.2 s and then decays to
its half value in 50s.
gThey are damped quickly by the resistive circuit
elements and do not propagate far from their source.
gThe most common cause for the impulsive transient
is lightening EE IIT Madras
IMPULSIVE TRANSIENT
1.
1. High
High frequency
frequency oscillatory
oscillatory transient
transient
2.
2. Medium
Medium frequency
frequency oscillatory
oscillatory transient
transient
3.
3. Low
Low frequency
frequency oscillatory
oscillatory transient
transient
EE IIT Madras
reessuulltt
Offtteenn r al
O
Oscillatory Transients
ooffllooccal
ssyysstteem
m
e
rreesspponsse
o n
r
apaaccititoor
DDuueettooccapizattioionn
erg iza
bbaannkkeennerguennccyy
q e
wwitithh freequ andd
f r
Hz an
330000--900 H2z.0 ppuu
90 0
ituddee 2.0
mmaaggnnitu
EE IIT Madras
SHORT DURATION VOLTAGE VARIATIONS
RMS VARIATIONS
Short duration voltage variations encompasses
voltage dips and short interruptions.
Short duration voltage variations are caused by
fault conditions in the network
the energization of large loads which require high
starting current
intermittent loose connections in the power wiring.
Voltage sag due to SLG fault EE IIT Madras Voltage sag motor starting
AN EXAMPLE ON VOLTAGE SAG
Consider a 50 hp induction motor with a
full load current of 60 A at 480 V ac . It is 4.16kV
connected to 480 V bus through a 480V
transformer of rating 100 kVA, 4.16 kV /
480 V, 5 % leakage reactance as shown in
Current Rating 60 A
50 hp 3-phase IM
figure. 100 kVA, 120 A
5% reactance
It is found that during first half of the
cycle current attains a peak of 860 A. The
voltage sag caused by starting of this
induction motor is computed as follows.
Source:
Source: A
A book
book on
on Power
Power Quality
IIT Madrasby
Quality
EE by Sankaran
Sankaran CRC
CRC Press
Press ))
VOLTAGE SWELL-I
A swell is defined as an increase between 1.1 pu and 1.8 pu in
rms voltage or current at the power frequency for durations from
0.5 cycle to one minute. They are not as common as voltage sag.
It is usually caused by fault conditions, switching off heavy
loads and energization of capacitor banks.
Swells are characterized by their magnitudes and durations.
The severity of voltage swell during fault condition depends on
fault location, system impedance, grounding.
EE IIT Madras
EE IIT Madras
VOLTAGE INTERRUPTION-I
Delayed re-closing of
protective device may cause
momentary or temporary
interruptions.
Source:
Source: Power
Power Quality
Quality Studies
Studies in
in Distribution
Distribution Systems
Systems Involving
EE IIT Madras Involving Spectral
Spectral Decomposition
Decomposition A A
Ph.D.
Ph.D. Dissertation
Dissertation zur
zur Erlangung
Erlangung desdes akademischen
akademischen Grades
Grades Doktoringenieur
Doktoringenieur (Dr.-Ing.)
(Dr.-Ing.)
LONG DURATION VOLTAGE
VARIATIONS-I
Long Duration Variations encompass rms deviations of
voltage longer than one minute. Long duration
variations generally results of system faults but are
caused by load variations on the system and system
switching operations.
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LONG DURATION VOLTAGE
VARIATIONS-II
Over Voltage: An over-voltage is an increase in the rms
ac voltage greater than 110% at the power frequency for a duration
longer than 1 minute. These are result of load switching (e.g.,
switching off a large load), or energizing a capacitor bank), poor
voltage regulation, incorrect tap settings on transformers.
EE IIT Madras
VOLTAGE IMBALANCE-II
Symmetrical component theory is used to determine positive,
negative and zero sequence components as per the following
equation.
v sa 0 (t ) 1 1 1 v sa (t )
v (t ) = 1 1 a a 2 v sb (t )
sa1 3
v sa 2 (t ) 1 a 2 a v sc (t )
t1 +T
2 j ( wt / 2 )
V sa 012 =
T sa 012
v (t ) e dt
tt
V sa 2 = V sa 2 V sa 2
EE IIT Madras
VOLTAGE IMBALANCE-III
Finally ,Voltage Imbalance can be defined as the ratio of
either the negative- or zero sequence component to the
positive sequence component to specify the percent
unbalance as given below.
KU0=Va0 / Va1
Ku2=Va2 / Va1
Figure shows an example of these two ratios for a one week
trend of imbalance on a residential feeder.
EE IIT Madras
WAVEFORM DISTORTION
Waveform distortion is defined as a steady state deviation from
an ideal sine wave of power frequency principally characterized
by the spectral content of the deviation. It can be broadly
classified into five categories
DC Offset
Harmonics
Inter-harmonics
Notching
Noise
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WAVEFORM DISTORT. Contd
DC OFFSET
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WAVEFORM DISTORT. Contd
Harmonics
Harmonics are sinusoidal voltages or currents having
frequencies that are integer multiples of the frequency at
which the supply system is designed to operate. Harmonics
are major threat to healthy operation of power system.
Harmonic distortion originates in the nonlinear
characteristics of devices and loads on the power system.
Harmonic distortion levels are described by the complete
harmonic spectrum with magnitudes and phase angles of
each individual harmonic component.
Sometimes it is common to use a single quantity, the Total
Harmonic Distortion (THD), as a measure of the effective
value of harmonic distortion.
EE IIT Madras
WAVEFORM DISTORT. Contd
Source of Harmonics
General categories of harmonic sources:
1. Saturable devices
Saturable devices produce harmonics due to mainly
iron saturation in transformers, machines etc.
Operating electrical devices around knee point
creates flatness in voltage with 3rd harmonic approx.
30% of fundamental
2. Power electronic based converters/devices
Power electronic based loads draw power only during
portions of the applied voltage waveform. These
include power electronic converters, UPS, SMPS,
Computers monitors, TVs, printers etc.
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WAVEFORM DISTORT. Contd
Harmonics-illustration
EE IIT Madras
WAVEFORM DISTORT. Contd
Harmonics-illustration
The
.. figure shows severe voltage distortion (6-8% THD) on
the secondary bus of a customer that has a large
amount of nonlinear (UPS) loads
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WAVEFORM DISTORT. Contd
EFFECT OF HARMONICS
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WAVEFORM DISTORT. Contd
HARMONICS: ILLUSTRATION
Neutral Conductor Overheating
Neutral overloading appears to be most
common problems in commercial buildings.
In a 3-, 4-w system, the sum of three phase
currents flow through neutral conductor.
I ao = ( I a + Ib + I c ) / 3 = I n
Using, Symmetrical
I a1 = ( I a + a Ib + a I c ) / 3
2
component theory
(Fundamental, harmonics)
I a 2 = ( I a + a Ib + a I c ) / 3
2
Over loaded neutral
The example is shown for PC load which draws 80% of 3rd har.
Which amounts to 240% almost 3 times of power conductor rating
EE IIT Madras
WAVEFORM DISTORT. Contd
Quantification of Harmonics
1. THD: Total Harmonic Distortion:
1/ 2 1/ 2
2
2
It is defined as, I n I n
THDI = n = 2 THDV = n = 2
I1 I1
PF = P = (1 + PH P1 ) PF1
S 2 2 2 2
1 + THDV +THDI +THDV *THDI
Where, Pn = Vn In cos n
n=1
1/ 2
2
2. TDD: Total Demand Distortion: I n
THDI = n = 2
I EE IIT Madras
WAVEFORM DISTORT. Contd
Control of Harmonics
1. Tuned LC filters: Traps the
harmonic component for which a
filter is designed
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WAVEFORM DISTORT. Contd
Interharmonics
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WAVEFORM DISTORT. Contd
Notching
Notching is a periodic voltage disturbance caused by the normal
operation of power electronics devices when current is commutated
from one phase to another. The notches may come sufficiently
close to zero introduces errors in instruments and control systems
that rely on zero crossings to derive frequency or time.
For example of voltage notching
from a three- phase converter
that produce continuous dc
current. The notches occur
when the current commutates
from one phase to another.
During this period, there is a
momentary short circuit
between two phases pulling the
voltage as close to zero as
permitted by system
impedances.
EE IIT Madras
WAVEFORM DISTORT. Contd
Noise
Noise is defined as unwanted electrical signals with broadband
spectral content lower than 200 kHz superimposed upon the
power system voltage or current in phase conductors, or found
on neutral conductors or signal lines.
EE IIT Madras
VOLTAGE FLUCTUATIONS
Flicker can be defined as small amplitude changes in
voltage levels i.e. 0.9 pu to 0.1 pu occurring at frequencies
less then 25 Hertz (25Hz). Flicker is caused by large,
rapidly fluctuating loads such as arc furnaces and electric
welders
EE IIT Madras
CUSTOM POWER DEVICES
Like FACTs devices, Custom Power Devices are also
power electronic based controllers in medium voltage
distribution systems for the purpose of supplying a level of
reliability and/or power quality that is needed by electric
power customers sensitive to power quality variations.
EE IIT Madras
MITIGATION USING CUSTOM POWER DEVICES
Once PQ problems are known, the next step is to mitigate them. In
the following sections, the various strategies/techniques of PQ
problems mitigation will be highlighted. The ultimate aim of any
power quality investigation is to solve/mitigate the power quality
problem. The PQ problems mitigation using custom power devices
involves the following.
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DSTATCOM STRUCTURE
DSTATCOM consists of
EE IIT Madras
1. Averaging and Sampling Control Algorithms
Techniques [Gyugyi 78, 79], [Miller] v sa i sa
i fab
v sb i sb ilab Bca
Bab
1 1 T
Bab = ( vbc ia + v ca ib v ab ic ) dt
3 3V 2 T 0 v sc i sc ilbc ilca
1 1 T
Bbc = ( vbc ia + v ca ib + v ab ic ) dt
3 3V 2 T 0
Bbc
1 1 T
Bca = ( vbc ia v ca ib + v ab ic ) dt
3 3V 2 T 0 (a)
C
Bab =
1 1
i
3 2 V T a
v sa = 0
dv sa dt > 0
+ ib v sb = 0
dv sb dt > 0
ic v sc = 0
dv sc dt > 0
B M1
1 1 L/2 M2 L / 2
Bbc = ia v sa = 0 + ib v sb = 0 + ic v sc =0 (b)
3 2V T dv sa dt > 0 dv sb dt > 0 dv sc dt > 0
Averaging and sampling techniques
1 1
Bca = ia v sa = 0 ib v sb = 0 + ic v sc =0
3 2V T dv sa dt > 0 dv sb dt > 0 dv sc dt > 0
Drawbacks
(a) It has a very slow response.
(b) If by any chance the value of K becomes
negative, the inverter will supply both the source
and the load.
EE IIT Madras
Control Algorithms
4. PQ theory [Akagi 83, 84]
P-q theory can eliminate all unbalances and harmonics caused
by non-linear, time varying loads, provided source voltages
are balanced and the power converter has infinite bandwidth.
p3 (t ) = va ia + bbib + vcic
Total 3-phase power:
= v i + v i + voio
EE IIT Madras = p (t ) + po (t )
Control Algorithms
P-q theory (Contd)
q
ia
a vc
ib
~ ~ b
Furthermore p = p + p po = p o + po q = q + q~ c
ic vb
va
io
o
p + po
From power matrix
o
p = p o + p loss po
P ~
Source p+~
po
q
C
Compensator
EE IIT Madras
Power flow related to o reference frame
P-q theory (Contd) Control Algorithms
Finally we, generate, reference currents in 3-phase
system, by inverse o transformation
va isa ila
ifa vb
L
0 io
isb
1/ 2 1 Source isc O
i = 2 1/ 2 1/ 2 A
vc
fb 3 / 2 i f For compensated system io = 0 i fa
D
3 i fc
i 1/ 2 1/ 2 3 / 2
i f vc ref vc
fc Voltage Voltage source
regulator inverter
g P-q theory is however is ploss
ia ifa
challenged when the source Active filter Dynamic
i fa
ib hysteresis i fb
voltages are unbalanced ic
controller
ifc current control i fc
ifb
g It needs large number of
va vb vc
transducers for measurements
and intensive computation 3-phase 4-wire active power filter
EE IIT Madras
Control Algorithms
Instantaneous Symm.Comp.Theory (Contd..)
Compensation of Star-connected load
According to this theory, the
reference currents for 3-phase,
4-wire distribution systems are...
vba + (v sc v sa )
i fb = ilb (Plavg + Ploss )
v si2
i = a ,b , c
v sc + (v sa v sc )
i fc = ilc (Plavg + Ploss ) 3-phase, 4-wire distribution system
2
v si
i = a ,b ,c
v sab v sc
i fab = ilab ( Plavg + Ploss )
*
v sc i sc
ilbc ilca
v sbc v sa
i fbc = ilbc ( Plavg + Ploss )
*
i *fbc
v sca v sb
i fca = ilca ( Plavg + Ploss )
*
Delta-connected load
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6. GENERALIZED INSTANTANEOUS REACTIVE
POWER THEORY
va ia
L
3- vb ib O
phase
Definitions of Powers: Source vc ic A
D
For the instantaneous space vectors
and are, v t = [va vb vc ]
and i t = [ia ib ic ] the
following terms are defined Three phase systems in reference to
definitions of powers
Instantaneous active power: p = v i = va ia + vbib + vcic
qa T
vb vc vc va va vb
Instantaneous reactive power: q = v i = qb =
ib ic ic ia ia ib
qc
def p def q v
i p = [iap ibp icp ]
T
= v iq = [iaq ibq icq ]T
=
v v v v
def def
Instantaneous apparent power s = v i and power factor = p
s
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REFERENCE CURRENT GENERATION
The compensated source current in vector form in terms
of desired source active and reactive power is given as
qs v s ps v s
i s = i sq + i sp = +
vs vs vs vs
Therefore, reference compensator current is given as
i *f = il i s
Converting above vector form to time domain expressions
1
i*fa = ila isa = ila ( ps vsa + qsb vsc qsc vsb )
vsj2
j = a ,b ,c
1
i*fb = ilb isb = ilb ( ps vsb + qsc vsa qsa vsc )
vsj2
j = a ,b , c
1
i*fc = ilc isc = ilc ( ps vsc + qsa vsb qsb vsa )
vsj2
j = a ,b ,c
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REALIZATION OF DSTATCOM
(Three Phase DSTATCOM Topologies)
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SOME IMPORTANT
Three -Phase DSTATCOM Topologies
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Three-phase, three-leg topology
with 3 dc storage capacitors
T0 PCC
a b c
S1a S3a
vc1 +
- S4a
S1a
S1b S3b
vc2 +
- S4b
S1b
S1c S3c
vc3 + n'
- S4c
S1c
Drawbacks
(a) It uses three capacitors and it is very difficult to regulate
the capacitor voltages
ila
LOAD
isa PCC
The topology however is not LOAD
suitable for compensation of
loads containing dc components in LOAD
EE IIT Madras
THREE-PHASE, THREE-LEG TOPOLOGY
ila
LOAD
isa PCC
The structure consists of LOAD
three-phase VSI connected to
common dc capacitor LOAD
v sc isc i fa
The topology is not suitable
for loads containing zero
sequence currents as zero C
sequence currents through the CSIs
path N-n.
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NEUTRAL CLAMPED INVERTER TOPOLOGY
vsa i sa ila
LOAD
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3-PHASE 4-LEG TOPOLGY
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NEUTRAL CLAMPED INVERTER
CHOPPER TOPOLOGY
This topology was proposed as a
part of my research work and called
as neutral clamped inverter chopper
topology. vsa ila
isa
It can compensate the unbalance,
LOAD
Chopper VSI
Due to dc offset current in load i1 i fa i fb i fc
currents, the dc currents also pass + Rf
S7 S1 S3 S5
through the dc capacitors. The D7 C1
vc1 io
voltage across capacitors is - a Lf
n' c
maintained constant by separate PI Rch ich Lch
+
b
S2
D8 S4 S6
control loop. But due to DC offset S8
vc2
HC6
HC5
Lf Rf
MS-1
S1 S3 S5
HV4 + G1 G3 G5
1:2 vc1
C1 -
230 V HV6
n'
50 Hz
S4 S6
S2
+
HV5 G4 G6 G2
vc2
C2 -
Auxiliary supply
EE IIT
Circuit for 3-phase 4-wire Madras
compensated system Power
DESIGN AND DEVELOPMENT OF
DSTATCOM-II
Logic GND
+ + Input
- LA 55-P
LV 25-V Input voltage io current
io
M - M
Outout
Outout Ro
Rvo voltage
voltage
GND -HT GND
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CONVERSION OF POWER QUANTITIES TO
LOW LEVEL SIGNALS-II
Circuit details
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PCB for signal conditioning
BLANKING CIRCUIT-I
S1 S3 S5
+ G1 G3 G5
vc1
C1 -
n'
S4 S6
S2
+ G4 G6 G2
vc2
C2 -
EE IIT Madras
BLANKING CIRCUIT-II
+5V
Rext CL100
Cext
TO OPTO ISOLATOR
Vcc G1
Sa 1.2k
16 15 14 2 4 S a shot
MODULE
13 S a shot S a shot GND
10 12
74LS123 4
S a shot
Sa 1.2k
G4
74LS123
3 2 8 CL100
1 7408 4050
B1 A1 GND
220
CLR Sa +5V
Circuit details
Sa
EXPERIMENTAL W/V
S a shot
G1 = Sa Sa shot
G4 = Sa Sa shot
Sa
S a shot
td td
EE IIT Madras
PCB for blanking circuit
ISOLATION CIRCUIT FOR IPM
2812 Blanking Opto-Isolation-
Processor Circuit driver Circuit
VCC(+15V)
1 8
NC
2 7
220 ohm
I/P from blanking I/P .01 micro f
circuit 360 ohm
3 6
GND O/P
O/P to IPM
4 5
NC GND
D4 Cdc 7915
D2 -15V
220 / V2-0-V2
Circuit details
S1 S3 S5
+ G1 G3 G5
vc1
C1 -
n'
S4 S6
S2
+
G4 G6 G2
vc2
C2 -
EE IIT Madras
Isolated power supply module
INTERFACING CIRCUIT DETAILS -I
expansion
XTAL1/0scin
Analog
30 MHz
A/D
converter
Parallel Port JTAG
JTAG Controller
TMS320F2812
I/O expansion
IBM Compatible External
JTAG
Interfacing description
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INTERFACING CIRCUIT DETAILS -II
Interfacing various
EE IIT components
Madras to DSP
e s sor
INTERFACING l Proc FA
Si gna 812PG
CIRCUIT i gital 20F2
D
M S3
DETAILS -III T
Level-3
INTEGRATED
u it
c
cir
SIGNAL i s ing
r on
nc h
CONDITIONING, Level-2 Sy
du le
mo
PROCESSING n ing
it io
d
con
MODULES nal
sig
ated n it
r u
FOR POWER teg ly
In p p
su
wer
QUALITY p o
dc
Level-1 ted
Integrated Signal Conditioning,
EE IITBlanking
Madras and Protection ul Module
a
g
with Synchronizing and DSP units components to DSP Re
POWER COMPONENTS-I
S1 S3 S5 Lf
C1 G1 G3 G5
+
vc1 Rf
-
n' a
b c
i0 + G4 G6 G2 i0
vc2
C2 - i 2 S4 S6 S2
DSP based
DSTATCOM-clip
EE IITPower
Intelligent Madras Modules
7. POWER COMPONENTS OF
DSTATCOM-Neutral Clamped VSI
S1 S3 S5 Lf
C1 G1 G3 G5
+
vc1 Rf
-
n' a
b c
i0 + G4 G6 G2 i0
v
C2 - c2 S2
i 2 S4 S6
Switching
Performance Mitsubishis Intelligent Power
EE IIT Madras
Modules: PM50RVA120
POWER COMPONENTS OF
DSTATCOM-H Bridge VSI
ila
LOAD
isa PCC
LOAD
LOAD
v sc i fa
Opto-isolation Mod
ule #1 Opto-isolation Module
C dc VSIs #2
IPM #1
IPM #2
Mitsubishis
EE IIT Madras two Intelligent Power Modules
(PM50RVA120) to form H-bridge VSI
INTEGRATED CONTROL HARDWARE
SET-UP FOR H-BRIDGE DSTATCOM
a d s
L o
ce cto rs
o u r du
l ta g e S ter ce I n
Vo Inver r fa
Inte
ff ect s
l E er
Haalnsduc
Tr
n
m mo
C o g
t o uplin
f
EE IIT Madras
n
Poi Co
POWER COMPONENTS
SEMIKRONs
EE IITtwo level VSI
Madras
THREE-LEVEL VOLTAGE
SOURCE INVERTER
ifa ifc
S1 S3 S5 Lf
G1 G3 G5
Rf
Vdc a
b c i0
G4 G6 G2
S4 S6 S2
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OTHER FACILITIES TO CONDUCT PQ
RESEARCH EXPERIMENTAL STUDY
EE IIT Madras
DSP DETAILS
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DSP VERSUS DAS
(a) DSP systems are stand alone systems while DAS are
system dependent
(b) DSP systems are less costly over DAS for similar
specification
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DSP FEATURES AND
SELECTION
EE IIT Madras
Based on the requirements of load
compensation it is found that TMS 320F2812
is the most suitable choice. It possesses the
following features:
1.Host Plateform: TMS320F2812
2. Number of Processor: 1
3. Clock speed: 150MHz
4. External Memory: 1.0 MW
5. Expansion Options: 3 expansion connectors
6. Softwares: Driver for CCS + Full C2000 Code Composer Studio
7. USB Emulator: XDS510 USB Emulator with USB cable and
drivers
8. Necessary cables and accessories
EE IIT Madras
SEQUENCE OF STEPS TO CONFIGURE 320F2812 TO
DEVELOP SOURCE CODE
Start
Configure SCSR1,SCSR2
Disalbling Watch Dog,Configure
ADCTRL3 Powering ON ADC
Give SOC
Reset and Configure
ADCTRL1,ADCTRL2,MAX_CONV
and CHSELSEQ Regs
ADCIN(A0-A9) RESULT(0-9)
Do Computations on Acquired
Signals
Give SOC by setting corresponding
bit in ADCTRL2
No
EOS INT Flag is
NOP
set?
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EXPERIMENTAL STUDIES
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Experimental Results Contd..
Unbalanced source
currents (load
currents) with neutral
current before
compensation
Balanced source
currents and neutral
current after
compensation without
PI Controller
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Experimental Results Contd..
EE IIT Madras
Experimental Results Contd..
Capacitor voltages
after including PI
controller with a
reference voltage of
440 Volts
EE IIT Madras
Experimental Results Contd..
EE IIT Madras
THANKS
EE IIT Madras